SD8901

The SD8901 is a ring demodulator/balanced mixer. Designedto utilize Calogic’s ultra high speed and low capacitancelateral DMOS process. The SD8901 offers significantperformance improvements over JFET and diode balancedmixers when low third order harmonic distortion has been aproblem.

PACKAGE INFORMATIONPart

Package

Temperature Range-55oC to 125oC-55oC to 125oC-55oC to 125oC

SD8901HDHermetic TO-78

SD8901CYPlastic Surface Mount XSD8901Sorted Chips in Carriers

•High Frequency Operation•Wide Dynamic Range•Low Capacitance

APPLICATIONS

•Communications•RF Mixers

PIN CONFIGURATIONSFunctional block diagramSO-14TO-78LO15IF27RF23CIF2LO1LO2IF1RF2RF1TOP VIEWLO 1 SUBLO 2 SUBIF 2 SUBNCRF2SUBRF1SUBIF1SUBNC1234567IF1RF1RF2CASELO1LO2IF24532166721LO2RF1IF14SUBSTRATEBOTTOM VIEW CD4SD8901CORPORATIONABSOLUTE MAXIMUM RATINGS (TA = +25oC unless otherwise noted)VDSVDBVSBVGSVGBVGD

Drain to Source. . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 VDrain to Substrate. . . . . . . . . . . . . . . . . . . . . . . . 22.5 VSource to Substrate. . . . . . . . . . . . . . . . . . . . . . . 22.5 VGate to Source. . . . . . . . . . . . . . . . . . . . -22.5 V to 30 VGate to Substrate. . . . . . . . . . . . . . . . . . . . -0.3V to 30 VGate to Drain. . . . . . . . . . . . . . . . . . . . . . -22.5V to 30 V

IDDrain Current. . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mAOperating Temperature. . . . . . . . . . . . . . . . . . . . -55 to 125oCStorage Temperature. . . . . . . . . . . . . . . . . . . . . . -65 to 150oCPower Dissipation (A Package)*. . . . . . . . . . . . . . . . 640 mW* Derate 5 mW/ oC above 25oC

ELECTRICAL CHARACTERISTCIS (TA = +25oC unless otherwise noted)

SYMBOLSTATICV(BR)DSV(BR)SDV(BR)DBV(BR)SBVTDrain-SourceBreakdown VoltageSource-DrainBreakdown VoltageDrain-SubstrateBreakdown VoltageSource-SubstrateBreakdown VoltageThreshold Voltage151522.522.50.1150rDS(ON)Drain-Source\"ON\" Resistance302319∆rDS(ON)DYNAMICCggLcIMD3fMAXLO1 - LO2 CapacitanceConversion Loss Third Order Intercept Maximum Operation Frequency4.48+35250pFdBMHzVDS = 0 V, VBS = -5.5 VVGS = 4 VSee Figure 1, PLO = +17 dBmResistance Matching37ΩID = 1 mAVSB = 0 V2.075V25VGS = VSB = -5 VIs = 10 nAVGD = VDB = - 5 VID = 10 nASource OpenVGB = 0 V, ID = 10 nADrain OpenVGB = 0 V, ID = 10 nAVDS = VGS = VTIS = 1 µA, VSB = 0VVGS = 5 VVGS = 10 V VGS = 15 VVGS = 20 VVGS = 5 VCHARACTERISTICSMINTYPMAXUNITTEST CONDITIONSNote: Guaranteed by design, not subject to production testPERFORMANCE COMPARISON403rd ORDER INPUTINTERCEPT POINT(+dBM)302010005SD8901U350DIODE RING101520253035POWER LOCAL OSC. (+dBm)SD8901CORPORATIONFIGURE 1.SD8901+VGGuT1-1TORT4-1uT4-1L OSIGNALuLOW-PASSIMAGE TERMINATINGFILTER(OPTIONAL)u680 pFT4-1-Vu680 pFi-fFIGURE 2. First and third Quadrand I-E Characteristic Showing Effect of Gate Voltage Leading to Large-SignalOverload Distortion.ID(ma)50.0016 V12 V8 V10.00/DIV04 V0 V-50.00-5.000VDS01.000/DIV(V)5.000