DDR sdram for stable read operation

专利名称：DDR sdram for stable read operation发明人：Young-Jin Yoon,Kwan-Weon Kim申请号：US10283535申请日：20021029

公开号：US20030053340A1公开日：20030320

专利附图：

摘要：A global input/output precharge apparatus includes a latch for cross-couplingand latching a global input/output line and a complementary global input/output line; aglobal input/output line delay for delaying the global input/output line and thecomplementary global input/output line by a predetermined time delay; a global

input/output line precharge logic for pre-charging the global input/output line feed-backed from the global input/output line delay; a first precharge logic for applying apower voltage to the global input/output line when a first logic state is feed-backed onthe output of the global input/output line precharge logic and applying a groundvoltage to the global input/output line when a second logic state is feed-backed on theoutput of the global input/output line precharge logic; and a second precharge logic forapplying the power voltage to the complementary global input/output line when thefirst logic state is feed-backed on the output of the global input/output line prechargelogic and applying the ground voltage to the complementary global input/output linewhen the second logic state is feed-backed on the output of the global input/output lineprecharge logic.

申请人：HYNIX SEMICONDUCTOR INC.

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