Method for manufacturing an interconnect structure

专利名称：Method for manufacturing an interconnect

structure for stacked semiconductor device

发明人：Tadatomo Suga申请号：US09997878申请日：20011130公开号：US06472293B2公开日：20021029

专利附图：

摘要：In a multi-layer interconnection structure, the wiring length is to be reduced,and the interconnection is to be straightened, at the same time as measures need to betaken against radiation noise. To this end, there is disclosed a semiconductor device in

which plural semiconductor substrates, each carrying semiconductor elements, arebonded together. On each semiconductor substrate is deposited an insulating layerthrough which is formed a connection wiring passed through the insulating layer so as tobe connected to the interconnection layer of the semiconductor element. On a junctionsurface of at least one of the semiconductor substrates is formed an electricallyconductive layer of an electrically conductive material in which an opening is bored inassociation with the connection wiring. The semiconductor substrates are bondedtogether by the solid state bonding technique to interconnect the connection wiringsformed on each semiconductor substrate.

申请人：OKI ELECTRIC INDUSTRY CO., LTD.,SANYO ELECTRIC CO., LTD.,SONYCORPORATION,KABUSHIKI KAISHA TOSHIBA,NEC CORPORATION,SHARP KABUSHIKIKAISHA,HITACHI, LTD.,FUJITSU LIMITED,MATSUSHITA ELECTRONICSCORPORATION,MITSUBISHI DENKI KABUSHIKI KAISHA,ROHM CO., LTD.

代理机构：Sonnenschein, Nath & Rosenthal

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