74LVX3245

Revised September 2003

74LVX3245

8-Bit Dual Supply Translating Transceiver with 3-STATE Outputs

General Description

The LVX3245 is a dual-supply, 8-bit translating transceiverthat is designed to interface between a 3V bus and a 5Vbus in a mixed 3V/5V supply environment. The Transmit/Receive (T/R) input determines the direction of data flow.Transmit (active-HIGH) enables data from A Ports to BPorts; Receive (active-LOW) enables data from B Ports toA Ports. The Output Enable input, when HIGH, disablesboth A and B Ports by placing them in a high impedancecondition. The A Port interfaces with the 3V bus; the B Portinterfaces with the 5V bus.

The LVX3245 is suitable for mixed voltage applicationssuch as notebook computers using 3.3V CPU and 5Vperipheral components.

Features

sBidirectional interface between 3V and 5V busessInputs compatible with TTL level

s3V data flow at A Port and 5V data flow at B PortsOutputs source/sink 24 mA

sGuaranteed simultaneous switching noise level anddynamic threshold performancesImplements proprietary EMI reduction circuitrysFunctionally compatible with the 74 series 245

Ordering Code:

Order Number74LVX3245WM74LVX3245QSC74LVX3245MTC

Package Number

M24BMQA24MTC24

Package Description

24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300\" Wide24-Lead Quarter Size Outline Package (QSOP), JEDEC MO-137, 0.150\" Wide24-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide

Devices also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.

Logic SymbolConnection Diagram

Pin Descriptions

Pin Names

OET/RA0–A7B0–B7

Description

Output Enable InputTransmit/Receive Input

Side A Inputs or 3-STATE OutputsSide B Inputs or 3-STATE Outputs

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74LVX3245Truth Table

InputsOELLH

H = HIGH Voltage LevelL = LOW Voltage LevelX = Immaterial

Outputs

T/RLHX

Bus B Data to Bus ABus A Data to Bus BHIGH-ZState

Logic Diagram

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74LVX3245Absolute Maximum Ratings(Note 1)

Supply Voltage (VCCA, VCCB)DC Input Voltage (VI) @ OE, T/RDC Input/Output Voltage (VI/O)@ An@ Bn

DC Input Diode Current (IIN)@ OE, T/RDC Output Diode Current (IOK)DC Output Source or Sink Current (IO)DC VCC or Ground Currentper Output Pin (ICC or IGND)and Max Current @ ICCA@ ICCB

Storage Temperature Range (TSTG)DC Latch-Up Source or Sink Current

−0.5V to +7.0V−0.5V to VCCA + 0.5V−0.5V to VCCA + 0.5V−0.5V to VCCB + 0.5V

±20 mA±50 mA±50 mA±50 mA±100 mA±200 mA

−65°C to +150°C

±300 mA

Recommended Operating Conditions (Note 2)

Supply VoltageVCCAVCCB

Input Voltage (VI) @ OE, T/RInput/Output Voltage (VI/O)@ An@ Bn

Free Air Operating Temperature (TA)Minimum Input Edge Rate (∆t/∆V)VIN from 30% to 70% of VCCVCC @ 3.0V, 4.5V, 5.5V

Note 1: The “Absolute Maximum Ratings” are those values beyond whichthe safety of the device cannot be guaranteed. The device should not beoperated at these limits. The parametric values defined in the ElectricalCharacteristics tables are not guaranteed at the absolute maximum ratings.The “Recommended Operating Conditions” table will define the conditionsfor actual device operation.

Note 2: Unused Pins (inputs and I/Os) must be held HIGH or LOW. Theymay not float.

2.7V to 3.6V4.5V to 5.5V0V to VCCA0V to VCCA0V to VCCB

−40°C to +85°C

8 ns/V

DC Electrical Characteristics

SymbolVIHAVIHBVILAVILBVOHA

Minimum HIGH LevelOutput VoltageMaximum LOW LevelInput Voltage

Parameter

Minimum HIGH Level Input Voltage

VCCA(V)

An, T/R, 3.6OEBnAn, T/R,OEBn

2.73.33.33.62.73.33.33.03.02.72.7

VOHBVOLA

Maximum LOW LevelOutput Voltage

3.03.03.03.02.72.7

VOLBIIN

Maximum InputLeakage Current@ OE, T/R

IOZA

Maximum 3-STATEOutput Leakage@ An

IOZB

Maximum 3-STATEOutput Leakage@ Bn

3.6

5.5

±0.5

±5.0

µA

3.6

5.5

±0.5

±5.0

µA

VI = VIL, VIHOE = VCCAVO = VCCA, GNDVI = VIL, VIHOE = VCCAVO = VCCB, GND

3.6

5.5

±0.1

±1.0

µA

VI = VCCB, GND

3.03.0

VCCB(V)5.05.04.55.55.05.04.55.54.54.54.54.54.54.54.54.54.54.54.54.5

2.992.652.52.34.54.250.0020.210.110.220.0020.18

TA = +25°CTyp

2.02.02.02.00.80.80.80.82.92.352.32.14.43.860.10.360.360.420.10.36

TA = −40°C to +85°CGuaranteed Limits

2.02.02.02.00.80.80.80.82.92.252.22.04.43.760.10.440.440.50.10.44

VVVV

IOUT = −100 µAIOH = −24 mAIOH = −12 mAIOH = −24 mAIOUT = −100 µAIOH = −24 mAIOUT =100 µAIOL = 24 mAIOL = 12 mAIOL = 24 mAIOUT = 100 µAIOL = 24 mAV

VOUT ≤ 0.1V or≥ VCC −0.1VV

VOUT ≤ 0.1V or≥ VCC − 0.1V

Units

Conditions

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74LVX3245DC Electrical Characteristics (Continued)

Symbol∆ICC

MaximumICCT/Input @

ICCA

Quiescent VCCASupply Current

ICCB

Quiescent VCCBSupply Current

VOLPAVOLPBVOLVAVOLVBVIHDAVIHDBVILDAVILDB

Quiet Output MaximumDynamic VOL

Quiet Output MinimumDynamic VOL

Minimum HIGH LevelDynamic Input VoltageMaximum LOW LevelDynamic Input Voltage

3.63.33.33.33.33.33.33.33.3

5.55.05.05.05.05.05.05.05.0

80.81.5−0.8−1.22.02.00.80.8

80

µA

3.6

5.5

5

50

µA

Parameter

BnAn, T/R,OE

VCCA(V)3.63.6

VCCB(V)5.55.5

TA = +25°CTyp1.0

1.350.35

TA = −40°C to +85°CGuaranteed Limits

1.50.5

UnitsmAmA

ConditionsVI = VCCB − 2.1VVI = VCCA −0.6VAn = VCCA or GNDBn = VCCB or GND,OE = GND, T/R = GNDAn = VCCA or GNDBn = VCCB or GND,OE = GND, T/R = VCCAVVVV

(Note 3) (Note 4)(Note 3) (Note 4)(Note 3) (Note 5)(Note 3) (Note 5)

Note 3: Worst case package.

Note 4: Max number of outputs defined as (n). Data inputs are driven 0V to VCC level; one output at GND.

Note 5: Max number of Data Inputs (n) switching. (n−1) inputs switching 0V to VCC level. Input-under-test switching: VCC level to threshold (VIHD), 0V to threshold (VILD), f = 1 MHz.

AC Electrical Characteristics

TA = +25°CCL = 50 pF

Symbol

Parameters

VCCA = 3.3V (Note 6)VCCB = 5.0V (Note 7)Min

tPHLtPLHtPHLtPLHtPZLtPZHtPZLtPZHtPHZtPLZtPHZtPLZtOSHLtOSLH

Propagation DelayA to B

Propagation DelayB to AOutput EnableTime OE to BOutput EnableTime OE to AOutput DisableTime OE to BOutput DisableTime OE to AOutput to OutputSkew (Note 8)Data to Output

Note 6: Voltage Range 3.3V is 3.3V ± 0.3V.Note 7: Voltage Range 5.0V is 5.0V ± 0.5V.

Note 8: Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device. Thespecification applies to any outputs switching in the same direction, either HIGH-to-LOW (tOSHL) or LOW-to-HIGH (tOSLH). Parameter guaranteed by design.

TA = −40°C to +85°C

CL = 50 pFVCCA = 3.3V (Note 6)VCCB = 5.0V (Note 7)Min1.01.01.01.01.01.01.01.01.01.01.01.0

Max8.58.08.08.08.59.09.09.58.07.58.57.01.5

TA = −40°C to +85°C

CL = 50 pFVCCA = 2.7VVCCB = 5.0V (Note 7)Min1.01.01.01.01.01.01.01.01.01.01.01.0

Max9.08.58.58.59.09.59.510.08.58.09.07.51.5

nsnsnsnsnsnsUnits

Typ5.45.65.15.74.86.36.36.85.34.25.33.71.0

Max8.07.57.57.58.08.58.59.07.57.08.06.51.5

1.01.01.01.01.01.01.01.01.01.01.01.0

ns

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74LVX3245Capacitance

SymbolCINCI/OCPD

Input CapacitanceInput/OutputCapacitancePower DissipationCapacitance (Note 9)

Note 9: CPD is measured at 10 MHz

ParameterTyp4.515

A →BB →A

5540

UnitspFpFpF

VCC = OpenVCCA = 3.3VVCCB = 5.0VVCCB = 5.0VVCCA = 3.3V

Conditions

8-Bit Dual Supply Translating Transceiver

The LVX3245 is a dual supply device capable of bidirec-tional signal translation. This level shifting ability providesan efficient interface between low voltage CPU local buswith memory and a standard bus defined by 5V I/O levels.The device control inputs can be controlled by either thelow voltage CPU and core logic or a bus arbitrator with 5VI/O levels.

Manufactured on a sub-micron CMOS process, theLVX3245 is ideal for mixed voltage applications such asnotebook computers using 3.3V CPU’s and 5V peripheraldevices.

Power Up Considerations

To insure that the system does not experience unneces-sary ICC current draw, bus contention, or oscillations duringpower up, the following guidelines should be adhered to(refer to Table 1):

•Power up the control side of the device first. This is theVCCA.

figured as inputs. With VCCA receiving power first, the AI/O Port should be configured as inputs to help guardagainst bus contention and oscillations.

•A side data inputs should be driven to a valid logic level.This will prevent excessive current draw.The above steps will ensure that no bus contention or oscil-lations, and therefore no excessive current draw occursduring the power up cycling of these devices. These stepswill help prevent possible damage to the translator devicesand potential damage to other system components.

•OE should ramp with or ahead of VCCA. This will helpguard against bus contention.•The Transmit/Receive control pin (T/R) should ramp withVCCA, this will ensure that the A Port data pins are con-

TABLE 1. Low Voltage Translator Power Up Sequencing Table

Device Type74LVX3245

VCCA3V(power up 1st)

VCCB5Vconfigurable

T/Rrampwith VCCA

OErampwith VCCA

A Side I/Ologic0V or VCCA

B Side I/Ooutputs

Floatable Pin Allowed

No

Please reference Application Note AN-5001 for more detailed information on using Fairchild’s LVX Low Voltage Dual Supply CMOS Translating Transceivers.

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74LVX3245Physical Dimensions inches (millimeters) unless otherwise noted

24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300\" Wide

Package Number M24B

24-Lead Quarter Size Outline Package (QSOP), JEDEC MO-137, 0.150\" Wide

Package Number MQA24

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74LVX3245 8-Bit Dual Supply Translating Transceiver with 3-STATE OutputsPhysical Dimensions inches (millimeters) unless otherwise noted (Continued)

24-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide

Package Number MTC24

Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied andFairchild reserves the right at any time without notice to change said circuitry and specifications.LIFE SUPPORT POLICY

FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORTDEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILDSEMICONDUCTOR CORPORATION. As used herein:1.Life support devices or systems are devices or systemswhich, (a) are intended for surgical implant into thebody, or (b) support or sustain life, and (c) whose failureto perform when properly used in accordance withinstructions for use provided in the labeling, can be rea-sonably expected to result in a significant injury to theuser.

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2.A critical component in any component of a life supportdevice or system whose failure to perform can be rea-sonably expected to cause the failure of the life supportdevice or system, or to affect its safety or effectiveness.

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