First-In/First-Out Dual-Port memory2048 x 9 organization (IDT7203)4096 x 9 organization (IDT7204)8192 x 9 organization (IDT7205)16384 x 9 organization (IDT7206)High-speed: 12ns access timeLow power consumption— Active: 770mW (max.)
— Power-down: 44mW (max.)
Asynchronous and simultaneous read and writeFully expandable in both word depth and width
Pin and functionally compatible with IDT720X familyStatus Flags: Empty, Half-Full, FullRetransmit capability
High-performance CMOS technology
Military product compliant to MIL-STD-883, Class BStandard Military Drawing for #5962-88669 (IDT7203),5962-89567 (IDT7203), and 5962-89568 (IDT7204) arelisted on this function
Industrial temperature range (-40oC to +85oC) is avail-able, tested to military electrical specifications
DESCRIPTION:The IDT7203/7204/7205/7206 are dual-port memory buff-ers with internal pointers that load and empty data on a first-in/first-out basis. The device uses Full and Empty flags toprevent data overflow and underflow and expansion logic toallow for unlimited expansion capability in both word size anddepth.
Data is toggled in and out of the device through the use ofthe Write (W) and Read (R) pins.
The devices 9-bit width provides a bit for a control or parityat the user’s option. It also features a Retransmit (RT) capa-bility that allows the read pointer to be reset to its initial positionwhen RT is pulsed LOW. A Half-Full Flag is available in thesingle device and width expansion modes.
The IDT7203/7204/7205/7206 are fabricated using IDT’shigh-speed CMOS technology. They are designed for appli-cations requiring asynchronous and simultaneous read/writesin multiprocessing, rate buffering, and other applications.Military grade product is manufactured in compliance withthe latest revision of MIL-STD-883, Class B.
••••••••
•.
FUNCTIONAL BLOCK DIAGRAM
DATA INPUTS(D0–D8)W
WRITECONTROLWRITEPOINTERRAM ARRAY2048 x 94096 x 98192 x 916384 x 9READPOINTERTHREE-STATEBUFFERSR
READCONTROLFLAGLOGICDATA OUTPUTS(Q0–Q8)RSRESETLOGICFL/RTEFFFXI
The IDT logo is a registered trademark of Integrated Device Techology, Inc.
EXPANSIONLOGICXO/HF2661 drw 01MILITARY AND COMMERCIAL TEMPERATURE RANGES
©1996 Integrated Device Technology, Inc.
For latest information contact IDT's web site at www.idt.com or fax-on-demand at 408-492-8391.
DECEMBER 1996
DSC-2661/9
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IDT7203/7204/7205/7206 CMOS ASYNCHRONOUS FIFO2048 x 9, 4096 x 9, 8192 x 9 and 16384 x 9
MILITARY AND COMMERCIAL TEMPERATURE RANGES
PIN CONFIGURATIONS
WD8D3D2D1D0XIFFQ0Q1Q2Q3Q8GND12345678910111213142827262524232221201918171615P28-1P28-2D28-1D28-3SO28-3Q3Q8GNDNCRQ4Q5PLCC/LCCTOP VIEW
UnitVSymbolVCCMVCCCGNDVIH(1)VIH(1)VIL(1)ParameterMilitary SupplyVoltageCommercial SupplyVoltageSupply VoltageInput High VoltageCommercialInput High VoltageMilitaryInput Low VoltageCommercial andMilitaryMin.4.54.502.02.2—VccD4D5D6D7FL/RTRSEFXO/HFQ7Q6Q5Q4R2661 drw 02aINDEXD2D1D0XIFFQ0Q1NCQ23231301432D3D8WNCVccD4D5141516171819205678910111213J32-1&L32-1292827262524232221D6D7NCFL/RTRSEFXO/HFQ7Q62661 drw 02bDIPTOP VIEW
NOTES:
1.The THINDIPs P28-2 and D28-3 are only available for the 7203/7204/7205.
2.The small outline package SO28-3 is only available for the 7204.3.Consult factory for CERPACK pinout.
ABSOLUTE MAXIMUM RATINGS(1)
SymbolVTERMRatingTerminalVoltage withRespect toGNDOperatingTemperatureTemperatureUnder BiasStorageTemperatureDC OutputCurrentCommercial–0.5 to + 7.0Military–0.5 to +7.0RECOMMENDED DC OPERATINGCONDITIONSTyp.5.05.00———Max.5.55.50——0.8UnitVVVVVVTATBIASTSTGIOUT0 to +70 –55 to +125–55 to + 12550–55 to +125–65 to +135–65 to +15550° C° C° CmANOTE:2661 tbl 011.Stresses greater than those listed under ABSOLUTE MAXIMUM RAT-INGS may cause permanent damage to the device. This is a stress ratingonly and functional operation of the device at these or any other conditionsabove those indicated in the operational sections of this specification is notimplied. Exposure to absolute maximum rating conditions for extendedperiods may affect reliability.
NOTE:
1.1.5V undershoots are allowed for 10ns once per cycle.
2661 tbl 02
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IDT7203/7204/7205/7206 CMOS ASYNCHRONOUS FIFO2048 x 9, 4096 x 9, 8192 x 9 and 16384 x 9
MILITARY AND COMMERCIAL TEMPERATURE RANGES
DC ELECTRICAL CHARACTERISTICS FOR THE 7203 AND 7204
(Commercial: VCC = 5.0V±10%, TA = 0°C to +70°C; Military: VCC = 5.0V±10%, TA = –55°C to +125°C)IDT7203/7204Commercial tA = 12, 15, 20, 25, 35, 50 nsSymbolILI(2)ILO(3)VOHVOLICC1(4)ICC2(4)ICC3(L)(4)ICC3(S)(4)Parameter Input Leakage Current (Any Input)Output Leakage CurrentOutput Logic “1” Voltage IOH = –2mAOutput Logic “0” Voltage IOL = 8mAActive Power Supply CurrentStandby Current (R=W=RS=FL/RT=VIH)Power Down Current (All Input = VCC - 0.2V)Power Down Current (All Input = VCC - 0.2V)Min.–1–102.4—————Typ.————————Max.110—0.4120(5)1228IDT7203/7204Military(1)tA = 20, 30, 40, 50, 65, 80, 120 nsMin.–1–102.4—————Typ.————————Max.110—0.4150(5)25412UnitµAµAVVmAmAmAmA2661 tbl 03
NOTES:
1.Speed grades 65, 80, and 120ns are only available in the ceramic DIP.2.Measurements with 0.4 ≤ VIN ≤ VCC.3.R ≥ VIH, 0.4 ≤ VOUT ≤ VCC.
4. ICC measurements are made with outputs open (only capacitive loading).5. Tested at f = 20MHz.
DC ELECTRICAL CHARACTERISTICS FOR THE 7205 AND 7206
(Commercial: VCC = 5.0V±10%, TA = 0°C to +70°C; Military: VCC = 5.0V±10%, TA = –55°C to +125°C)IDT7205/7206CommercialtA = 15, 20, 25, 35, 50 nsSymbolILI(1)ILO(2)VOHVOLICC1(3)ICC2(3)ICC3(L)(3)Parameter Input Leakage Current (Any Input)Output Leakage CurrentOutput Logic “1” Voltage IOH = –2mAOutput Logic “0” Voltage IOL = 8mAActive Power Supply CurrentStandby Current (R=W=RS=FL/RT=VIH)Power Down Current (All Input = VCC - 0.2V)Min.–1–102.4————Typ.———————Max.110—0.4120(4)128Min.–1–102.4————IDT7205/7206MilitarytA = 20, 30, 50 nsTyp.———————Max.110—0.4150(4)2512UnitµAµAVVmAmAmA2661 tbl 04
NOTES:1.Measurements with 0.4 ≤ VIN ≤ VCC.2.R ≥ VIH, 0.4 ≤ VOUT ≤ VCC.
3.ICC measurements are made with outputs open (only capacitive loading).4.Tested at f = 20MHz.
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IDT7203/7204/7205/7206 CMOS ASYNCHRONOUS FIFO2048 x 9, 4096 x 9, 8192 x 9 and 16384 x 9
MILITARY AND COMMERCIAL TEMPERATURE RANGES
AC ELECTRICAL CHARACTERISTICS(1)
(Commercial: VCC = 5V ± 10%, TA = 0°C to +70°C; Military: VCC = 5V ± 10%, TA = –55°C to +125°C)Commercial7203S/L127204S/L127203S/L157204S/L157205L157206L15—25—1015555—2515101102515151025151510—————15————15——15101040—15—————15—————————————2525251515—15152525—1515———Com'l & Mil.7203S/L207204S/L207205L207206L20Max.33.3—20—————15—————————————3030302020—20203030—2020————30—1020555—3020101203020201030202010—————20————20——201010Com'l7203S/L257204S/L257205L257206L25—35—1025555—3525101503525251035252510—————25————25——25101028.5—25—————18—————————————3535352525—25253535—2525———MilitaryCom'l7203S/L307203S/L357204S/L307204S/L357205L307205L357206L307206L35—40—1030555—4030101804030301040303010—————30————30——30101025—30—————20—————————————4040403030—30304040—3030————45—10355105—4535101804535351045353510—————35————35——35101522.2MHz—35—————20—————————————4545453030—30304545—3535———nsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsns2661 tbl 05
SymbolfStRCtAtRRtRPWtRLZtWLZtDVtRHZtWCtWPWtWRtDStDHtRSCtRStRSStRTRtRTCtRTtRTStRSRtEFLtRTFtREFtRFFtRPEtWEFtWFFtWHFtRHFtWPFtXOLtXOHtXItXIRtXISParametersShift FrequencyRead Cycle TimeAccess TimeRead Recovery TimeRead Pulse Width(2)Read LOW to Data Bus LOW(3)Write HIGH to Data Bus Low-Z(3, 4)Data Valid from Read HIGHRead HIGH to Data Bus High-Z(3)Write Cycle TimeWrite Pulse Width(2)Write Recovery TimeData Set-up TimeData Hold TimeReset Cycle TimeReset Pulse Width(2)Reset Set-up Time(3)Reset Recovery TimeRetransmit Cycle TimeRetransmit Pulse Width(2)Retransmit Set-up Time(3)Retransmit Recovery TimeReset to EF LOWRetransmit LOW to Flags ValidRead LOW to EF LOWRead HIGH to FF HIGHRead Pulse Width after EF HIGHWrite HIGH to EF HIGHWrite LOW to FF LOWWrite LOW to HF Flag LOWRead HIGH to HF Flag HIGHWrite Pulse Width after FF HIGHRead/Write LOW to XO LOWRead/Write HIGH to XO HIGHXI Pulse Width(2)XI Recovery TimeXI Set-up TimeMin.Max.Min.Max.Min.—20—812335—201289020121282012128—————12————12——128850—12—————12—————————————1217201214—12141717—1212———Min.Max.Min.Max.Min.Max.UnittHFH, tFFHReset to HF and FF HIGHNOTES:1.Timings referenced as in AC Test Conditions.2.Pulse widths less than minimum are not allowed.3.Values guaranteed by design, not currently tested.4.Only applies to read data flow-through mode.
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IDT7203/7204/7205/7206 CMOS ASYNCHRONOUS FIFO2048 x 9, 4096 x 9, 8192 x 9 and 16384 x 9
MILITARY AND COMMERCIAL TEMPERATURE RANGES
AC ELECTRICAL CHARACTERISTICS(1) (Continued)
(Commercial: VCC = 5V ± 10%, TA = 0°C to +70°C; Military: VCC = 5V ± 10%, TA = –55°C to +125°C)Military7203S/L407204S/L40Com'l & Mil.7203S/L507204S/L507205L507206L50Min.—65—155010155—6550153056550501565505015—————50————50——50101515—50—————30—————————————6565654545—45456565—5050———7203S/L657204S/L65Military(2)7203S/L807204S/L807203S/L1207204S/L120SymbolfStRCtAtRRtRPWtRLZtWLZtDVtRHZtWCtWPWtWRtDStDHtRSCtRStRSStRSRtRTCtRTtRTStRSRtEFLtHFH, tFFHtRTFtREFtRFFtRPEtWEFtWFFtWHFtRHFtWPFtXOLtXOHtXItXIRtXISParametersShift FrequencyRead Cycle TimeAccess TimeRead Recovery TimeRead Pulse Width(3)Read LOW to Data Bus LOW(4)Write HIGH to Data Bus Low-Z(4, 5)Data Valid from Read HIGHRead HIGH to Data Bus High-Z(4)Write Cycle TimeWrite Pulse Width(3)Write Recovery TimeData Set-up TimeData Hold TimeReset Cycle TimeReset Pulse Width(3)Reset Set-up Time(4)Reset Recovery TimeRetransmit Cycle TimeRetransmit Pulse Width(3)Retransmit Set-up Time(4)Retransmit Recovery TimeReset to EF LOWReset to HF and FF HIGHRetransmit LOW to Flags ValidRead LOW to EF Flag LOWRead HIGH to FF HIGHRead Pulse Width after EF HIGHWrite HIGH to EF HIGHWrite LOW to FF LOWWrite LOW to HF LOWRead HIGH to HF HIGHWrite Pulse Width after FF HIGHRead/Write LOW to XO LOWRead/Write HIGH to XO HIGHXI Pulse Width(3)XI Recovery TimeXI Set-up TimeMin.—50—10405105—5040102005040401050404010—————40————40——401015Max.20—40—————25—————————————5050503535—35355050—4040———Max.Min.—80—156510155—80651530108065651580656515—————65————65——651015Max.Min.12.5—65—————30—————————————8080806060—60608080—6565————100—208010205—10080204010100808020100808020—————80————80——801015Max.Min.10—80—————30—————————————1001001006060—6060100100—8080————140—2012010205—1401202040101401201202014012012020—————120————120——1201015Max.7—120—————35—————————————1401401406060—6060140140—120120———UnitMHznsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsns2661 tbl 06
NOTES:1.Timings referenced as in AC Test Conditions.
2.Speed grades 65, 80, and 120ns are only available in the ceramic DIP.3.Pulse widths less than minimum are not allowed.4.Values guaranteed by design, not currently tested.5.Only applies to read data flow-through mode.
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IDT7203/7204/7205/7206 CMOS ASYNCHRONOUS FIFO2048 x 9, 4096 x 9, 8192 x 9 and 16384 x 9
MILITARY AND COMMERCIAL TEMPERATURE RANGES
AC TEST CONDITIONSInput Pulse LevelsInput Rise/Fall TimesInput Timing Reference LevelsOutput Reference LevelsOutput LoadGND to 3.0V5ns1.5V1.5VSee Figure 1 2661 tbl 075V
1.1KΩ
D.U.T.
680Ω30pF*
CAPACITANCE(1) (TA = +25°C, f = 1.0 MHz)
SymbolCIN(1)COUT(1,2)ParameterInput CapacitanceOutput CapacitanceConditionVIN = 0VVOUT = 0VMax.1010UnitpFpFFigure 1. Output Load
OR EQUIVALENT CIRCUIT
2661 drw 03
NOTES:1.This parameter is sampled and not 100% tested.2.With output deselected.
2661 tbl 08*Includes jig and scope capacitances.
SIGNAL DESCRIPTIONSInputs:
DATA IN (D0–D8) — Data inputs for 9-bit wide data.
Controls:
RESET (RS) — Reset is accomplished whenever the Reset(RS) input is taken to a LOW state. During reset, both internalread and write pointers are set to the first location. A reset isrequired after power-up before a write operation can take place.Both the Read Enable (R) and Write Enable (W) inputs mustbe in the HIGH state during the window shown in Figure 2(i.e. tRSS before the rising edge of RS) and should notchange until tRSR after the rising edge of RS.
WRITE ENABLE (W) — A write cycle is initiated on the fallingedge of this input if the Full Flag (FF) is not set. Data set-up andhold times must be adhered-to, with respect to the rising edgeof the Write Enable (W). Data is stored in the RAM arraysequentially and independently of any on-going read operation.After half of the memory is filled, and at the falling edge of thenext write operation, the Half-Full Flag (HF) will be set to LOW,and will remain set until the difference between the write pointerand read pointer is less-than or equal to one-half of the totalmemory of the device. The Half-Full Flag (HF) is reset by therising edge of the read operation.
To prevent data overflow, the Full Flag (FF) will go LOW onthe falling edge of the last write signal, which inhibits further writeoperations. Upon the completion of a valid read operation, theFull Flag (FF) will go HIGH after tRFF, allowing a new valid writeto begin. When the FIFO is full, the internal write pointer isblocked from W, so external changes in W will not affect the FIFOwhen it is full.
READ ENABLE (R) — A read cycle is initiated on the fallingedge of the Read Enable (R), provided the Empty Flag (EF) is notset. The data is accessed on a First-In/First-Out basis, inde-pendent of any ongoing write operations. After Read Enable (R)goes HIGH, the Data Outputs (Q0 through Q8) will return to ahigh-impedance condition until the next Read operation. Whenall the data has been read from the FIFO, the Empty Flag (EF)will go LOW, allowing the “final” read cycle but inhibiting furtherread operations, with the data outputs remaining in a high-impedance state. Once a valid write operation has been accom-plished, the Empty Flag (EF) will go HIGH after tWEF and a validRead can then begin. When the FIFO is empty, the internal readpointer is blocked from R so external changes will not affect theFIFO when it is empty.
FIRST LOAD/RETRANSMIT (FL/RT) — This is a dual-purpose input. In the Depth Expansion Mode, this pin isgrounded to indicate that it is the first device loaded (seeOperating Modes). The Single Device Mode is initiated bygrounding the Expansion In (XI).
The IDT7203/7204/7205/7206 can be made to retransmitdata when the Retransmit Enable Control (RT) input is pulsedLOW. A retransmit operation will set the internal read pointer tothe first location and will not affect the write pointer. The statusof the Flags will change depending on the relative locations ofthe read and write pointers. Read Enable (R) and Write Enable(W) must be in the HIGH state during retransmit. This feature isuseful when less than 2048/4096/8192/16384 writes are per-formed between resets. The retransmit feature is not compat-ible with the Depth Expansion Mode.
EXPANSION IN (XI) — This input is a dual-purpose pin.Expansion In (XI) is grounded to indicate an operation in thesingle device mode. Expansion In (XI) is connected to Expan-sion Out (XO) of the previous device in the Depth Expansion orDaisy-Chain Mode.
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IDT7203/7204/7205/7206 CMOS ASYNCHRONOUS FIFO2048 x 9, 4096 x 9, 8192 x 9 and 16384 x 9
MILITARY AND COMMERCIAL TEMPERATURE RANGES
Outputs:
FULL FLAG (FF) — The Full Flag (FF) will go LOW, inhibitingfurther write operations, when the device is full. If the readpointer is not moved after Reset (RS), the Full Flag (FF) will goLOW after 2048/4096/8192/16384 writes.
EMPTY FLAG (EF) — The Empty Flag (EF) will go LOW,inhibiting further read operations, when the read pointer is equalto the write pointer, indicating that the device is empty.EXPANSION OUT/HALF-FULL FLAG (XO/HF) — This is adual-purpose output. In the single device mode, when Expan-sion In (XI) is grounded, this output acts as an indication of a half-full memory.
After half of the memory is filled, and at the falling edge of thenext write operation, the Half-Full Flag (HF) will be set to LOW
and will remain set until the difference between the write pointerand read pointer is less than or equal to one half of the totalmemory of the device. The Half-Full Flag (HF) is then reset bythe rising edge of the read operation.
In the Depth Expansion Mode, Expansion In (XI) is con-nected to Expansion Out (XO) of the previous device. Thisoutput acts as a signal to the next device in the Daisy Chain byproviding a pulse to the next device when the previous devicereaches the last location of memory. There will be an XO pulsewhen the Write pointer reaches the last location of memory, andan additional XO pulse when the Read pointer reaches the lastlocation of memory.
DATA OUTPUTS (Q0-Q8) — Q0-Q8 are data outputs for 9-bit wide data. These outputs are in a high-impedance conditionwhenever Read (R) is in a HIGH state.
tRSCtRSRStRSSWtRSSRtEFLEFtHFH, tFFHHF, FF2661 drw 04tRSRNOTE:
1. W and R = VIH around the rising edge of RS.
Figure 2. Reset
tRCtARtRLZQ0–Q8tRRtRPWtAtRHZDATAOUTVALIDtDVDATAOUTVALIDtWCtWPWtWRWtDSD0–D8tDHDATAINVALID2661 drw 05DATAINVALIDFigure 3. Asynchronous Write and Read Operation
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MILITARY AND COMMERCIAL TEMPERATURE RANGES
LAST WRITER
IGNOREDWRITEFIRST READW
tWFFFF
2661 drw 06tRFFFigure 4. Full FlagTiming From Last Write to First Read
LAST READW
IGNOREDREADFIRST WRITER
tREFEF
tADATAOUT
VALID2661 drw 07tWEFFigure 5. Empty Flag Timing From Last Read to First Write
tRTCtRTRTtRTSW,RRTFtRTRHF, EF, FFFLAG VALID2661 drw 08NOTE:
1. EF, FF and HF may change status during Retransmit, but flags will be valid at tRTC.
Figure 6. Retransmit
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MILITARY AND COMMERCIAL TEMPERATURE RANGES
WtWEFEFtRPER2661 drw 09Figure 7. Minimum Timing for an Empty Flag Coincident Read Pulse.
RtRFFFFtWPFW2661 drw 10Figure 8. Minimum Timing for an Full Flag Coincident Write Pulse.
WtRHFRtWHFHALF-FULL OR LESSMORE THAN HALF-FULLHALF-FULL OR LESS2661 drw 11HFFigure 9. Half-Full Flag Timing
W
WRITE TOLAST PHYSICALLOCATIONREAD FROMLAST PHYSICALLOCATIONtXOLtXOHR
tXOLtXOHXO
2661 drw 12
Figure 10. Expansion Out
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IDT7203/7204/7205/7206 CMOS ASYNCHRONOUS FIFO2048 x 9, 4096 x 9, 8192 x 9 and 16384 x 9
MILITARY AND COMMERCIAL TEMPERATURE RANGES
tXIXItXISWWRITE TOFIRST PHYSICALLOCATIONtXIRtXISREAD FROMFIRST PHYSICALLOCATION2661 drw 11RFigure 11. Expansion In
OPERATING MODES:
Care must be taken to assure that the appropriate flag ismonitored by each system (i.e. FF is monitored on the devicewhere W is used; EF is monitored on the device where R isused). For additional information, refer to Tech Note 8: Oper-ating FIFOs on Full and Empty Boundary Conditions andTech Note 6: Designing with FIFOs.Single Device Mode
A single IDT7203/7204/7205/7206 may be used when theapplication requirements are for 2048/4096/8192/16384 wordsor less. The IDT7203/7204/7205/7206 is in a Single DeviceConfiguration when the Expansion In (XI) control input isgrounded (see Figure 12).
Depth Expansion
The IDT7203/7204/7205/7206 can easily be adapted toapplications when the requirements are for greater than 2048/4096/8192/16384 words. Figure 14 demonstrates Depth Ex-pansion using three IDT7203/7204/7205/7206s. Any depthcan be attained by adding additional IDT7203/7204/7205/7206s. The IDT7203/7204/7205/7206 operates in the DepthExpansion mode when the following conditions are met:1.The first device must be designated by grounding the FirstLoad (FL) control input.
2.All other devices must have FL in the HIGH state.
3.The Expansion Out (XO) pin of each device must be tied tothe Expansion In (XI) pin of the next device. See Figure 14.4.External logic is needed to generate a composite Full Flag(FF) and Empty Flag (EF). This requires the ORing of allEFs and ORing of all FFs (i.e. all must be set to generate thecorrect composite FF or EF). See Figure 14.
5.The Retransmit (RT) function and Half-Full Flag (HF) arenot available in the Depth Expansion Mode.For additional information, refer to Tech Note 9: CascadingFIFOs or FIFO Modules.USAGE MODES:
Width Expansion
Word width may be increased simply by connecting thecorresponding input control signals of multiple devices. Sta-tus flags (EF, FF and HF) can be detected from any one device.Figure 13 demonstrates an 18-bit word width by using twoIDT7203/7204/7205/7206s. Any word width can be attainedby adding additional IDT7203/7204/7205/7206s (Figure 13).Bidirectional Operation
Applications which require data buffering between twosystems (each system capable of Read and Write operations)can be achieved by pairing IDT7203/7204/7205/7206s asshown in Figure 16. Both Depth Expansion and Width Expan-sion may be used in this mode.
Data Flow-Through
Two types of flow-through modes are permitted, a readflow-through and write flow-through mode. For the read flow-through mode (Figure 17), the FIFO permits a reading of asingle word after writing one word of data into an empty FIFO.The data is enabled on the bus in (tWEF + tA) ns after the risingedge of W, called the first write edge, and it remains on the busuntil the R line is raised from LOW-to-HIGH, after which thebus would go into a three-state mode after tRHZ ns. The EF linewould have a pulse showing temporary deassertion and thenwould be asserted.
In the write flow-through mode (Figure 18), the FIFOpermits the writing of a single word of data immediately afterreading one word of data from a full FIFO. The R line causesthe FF to be deasserted but the W line being LOW causes it tobe asserted again in anticipation of a new data word. On therising edge of W, the new word is loaded in the FIFO. The Wline must be toggled when FF is not asserted to write new datain the FIFO and to increment the write pointer.
Compound Expansion
The two expansion techniques described above can beapplied together in a straightforward manner to achieve largeFIFO arrays (see Figure 15).
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IDT7203/7204/7205/7206 CMOS ASYNCHRONOUS FIFO2048 x 9, 4096 x 9, 8192 x 9 and 16384 x 9
MILITARY AND COMMERCIAL TEMPERATURE RANGES
(HALF–FULL FLAG)WRITE (W)9DATA IN (D)FULL FLAG (FF)RESET (RS)(HF)READ (R)IDT7203/7204/7205/72069DATA OUT (Q)EMPTY FLAG (EF)RETRANSMIT (RT)EXPANSION IN (XI)2661 drw 14Figure 12. Block Diagram of 2048 x 9/4096 x 9/8192 x 9/16384 x 9 FIFO Used in Single Device Mode
HF18DATA IN(D)WRITE (W)FULL FLAG (FF)
RESET (RS)
IDT7203/7204/7205/72069XI99HFIDT7203/7204/7205/72069XI18READ (R)
EMPTY FLAG (EF)RETRANSMIT (RT)
DATA OUT (Q)
2661 drw 15
NOTE:
1.Flag detection is accomplished by monitoring the FF, EF and HF signals on either (any) device used in the width expansion configuration.
Do not connect any output signals together.
Figure 13. Block Diagram of 2048 x 18/4096 x 18/8192 x 18/16384 x 18 FIFO Memory Used in Width Expansion Mode
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IDT7203/7204/7205/7206 CMOS ASYNCHRONOUS FIFO2048 x 9, 4096 x 9, 8192 x 9 and 16384 x 9
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TRUTH TABLES
TABLE I – RESET AND RETRANSMIT
SINGLE DEVICE CONFIGURATION/WIDTH EXPANSION MODEInputsModeResetRetransmitRead/WriteRS011RTX01XI000Internal StatusRead PointerLocation ZeroLocation ZeroIncrement(1)Write PointerLocation ZeroUnchangedIncrement(1)EF0XXOutputsFF1XXHF1XX2661 tbl 09
NOTE:1. Pointer will Increment if flag is HIGH.
TABLE II – RESET AND FIRST LOAD
DEPTH EXPANSION/COMPOUND EXPANSION MODEInputsModeReset First DeviceReset all Other DevicesRead/WriteRS001FL01XXI(1)(1)(1)Internal StatusRead PointerLocation ZeroLocation ZeroXWrite PointerLocation ZeroLocation ZeroXEF00XOutputsFF11X 2661 tbl 10NOTES:1. XI is connected to XO of previous device. See Figure 14.
2. RS = Reset Input, FL/RT = First Load/Retransmit, EF = Empty Flag Output, FF = Full Flag Output, XI = Expansion Input, HF = Half-Full Flag Output
XOWD
9FF9IDT7203/7204/7205/7206XIXOFULL
9FFIDT7203/7204/7205/7206XIXOFF9RS
IDT7203/7204/7205/7206XIEFEFFLEMPTY
EF9FLRQVCC
FL2661 drw 16Figure 14. Block Diagram of 6149 x 9/12298 x 9/24596 x 9/49152 x 9 FIFO Memory (Depth Expansion)
5.0412
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IDT7203/7204/7205/7206 CMOS ASYNCHRONOUS FIFO2048 x 9, 4096 x 9, 8192 x 9 and 16384 x 9
MILITARY AND COMMERCIAL TEMPERATURE RANGES
Q0–Q8Q0–Q8IDT7203/IDT7204/IDT7205/IDT7206DEPTHEXPANSIONBLOCKD0-D8D0–DN
D9-DN
NOTES:
1. For depth expansion block see section on Depth Expansion and Figure 14.2. For Flag detection see section on Width Expansion and Figure 13.
Q9–Q17
•••
Q9–Q17IDT7203/IDT7204/IDT7205/IDT7206DEPTHEXPANSIONBLOCKD9-D17•••
D18-DN
D(N-8)-DN
Q(N-8)-QNQ(N-8)-QNIDT7203/IDT7204/IDT7205/IDT7206DEPTHEXPANSIONBLOCKD(N-8)-DN2661 drw 17
R, W, RS•••
Figure 15. Compound FIFO Expansion
WAFFADA 0-8IDT7203/IDT7204/7201A7205/7206RBEFBHFBQB 0-8SYSTEM ASYSTEM B
QA 0-8RAHFAEFAIDT7203/7204/7205/7206DB 0-8WBFFB2661 drw 18Figure 16. Bidirectional FIFO Operation
DATAIN
W
tRPER
EF
tWEFtWLZDATAOUT
Figure 17. Read Data Flow-Through Mode
tAtREFDATA VALIDOUT2661 drw 19
5.0413
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IDT7203/7204/7205/7206 CMOS ASYNCHRONOUS FIFO2048 x 9, 4096 x 9, 8192 x 9 and 16384 x 9
MILITARY AND COMMERCIAL TEMPERATURE RANGES
R
tW
tRFFFF
tWFFDATAIN
tDATAOUT
AWPFtDHINDATAVALIDtDSDATAOUTVALID2661 drw 20
Figure 18. Write Data Flow-Through Mode
ORDERING INFORMATION
IDT
XXXX
X
XXSpeed
XPackage
XProcess/TemperatureRangeBlankB
Commercial (0°C to +70°C)Military (–55°C to +125°C)
Compliant to MIL-STD-883, Class BPlastic DIP
Plastic THINDIPCeramic DIP
Ceramic THINDIP (all except 7206)Plastic Leaded Chip Carrier
Leadless Chip Carrier (Military only)Small Outline IC (7204 only)Commercial 7203/04 OnlyCommercial OnlyCommercial OnlyMilitary Only
Commercial OnlyMilitary 7203/04 OnlyMilitary 7203/04DB Only
Standard Power (7203/7204 only)Low Power2048 x 9 FIFO4096 x 9 FIFO8192 x 9 FIFO16384 x 9 FIFO
Access Time (tA)Speed in ns
DeviceTypePower
PTPDTDJLSO12152025303540506580120SL7203720472057206
2661 drw 21
5.0414
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