CD4067BMSCD4097BMS
CMOS Analog
Multiplexers/Demultiplexers
PinoutCD4067BMSTOP VIEWDecember 1992
Features•High Voltage Types (20V Rating)•CD4067BMS Single 16 Channel Multiplexer/Demultiplexer•CD4097BMS Differential 8 Channel Multiplexer/Demulti-plexer•Low ON Resistance: 125Ω (typ) Over 15Vp-p SignalInput Range for VDD - VSS = 15V•High OFF Resistance: Channel Leakage of±10pA (typ)at VDD - VSS = 18V•Matched Switch Characteristics: RON = 5Ω (typ) forVDD - VSS = 15V•Very Low Quiescent Power Dissipation Under All Digi-tal Control Input and Supply Conditions: 0.2µW (typ)at VDD - VSS = 10V•Binary Address Decoding on Chip•5V, 10V and 15V Parametric Ratings•100% Tested for Quiescent Current at 20V•Maximum Input Current of 1µA at 18V Over Full Pack-age Temperature Range; 100nA at 18V and +25oC•Standardized Symmetrical Output CharacteristicsCOMMON OUT/IN17263544536271809A10B1124VDD23822921102011191218131714161515INHIBIT14C13D***CHANNELIN/OUTVSS12Applications•Analog and Digital Multiplexing and Demultiplexing•A/D and D/A Conversion•Signal Gating*When these devices are used as demultiplexers the “CHANNELIN/OUT” terminals are the outputs and the “COMMON OUT/IN” ter-minals are the inputs.COMMON XOUT/IN1726354CHANNEL XIN/OUT4536271809A10B11VSS1224VDD23022121220319418517COMMON YOUT/IN166Y CHANNEL15714C13INHIBITIN/OUTY CHANNELIN/OUTCD4097BMSTOP VIEWDescriptionCD4067BMS and CD4097BMS CMOS analog multiplexers/demultiplexers* are digitally controlled analog switches havinglow ON Impedance, low OFF leakage current, and internaladdress decoding. In addition, the ON resistance is relativelyconstant over the full input-signal range.The CD4067BMS is a 16 channel multiplexer with four binarycontrol inputs, A, B, C, D and an inhibit input, arranged so thatany combination of the inputs selects one switch.The CD4097BMS is a differential 8 channel multiplexer havingthree binary control inputs A, B, C and an inhibit input. The inputspermit selection of one of eight pairs of switches. A logic “1”present at the inhibit input turns all channels off.The CD4067BMS and CD4097BMS are supplied in these 24lead outline packages:Braze Seal DIPFrit Seal DIPCeramic Flatpack*CD4067B Only*H4V†H6M*H1Z†HFN*H4P†H4P†CD4097BCAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.1-888-INTERSIL or 321-724-7143|Copyright © Intersil Corporation 1999
File Number
3190
7-1
元器件交易网www.cecb2b.com
Specifications CD4067BMS, CD4097BMS
Absolute Maximum RatingsDC Supply Voltage Range, (VDD) . . . . . . . . . . . . . . .-0.5V to +20V(Voltage Referenced to VSS Terminals)Input Voltage Range, All Inputs . . . . . . . . . . . . .-0.5V to VDD +0.5VDC Input Current, Any One Input . . . . . . . . . . . . . . . . . . . . . . . .±10mAOperating Temperature Range. . . . . . . . . . . . . . . .-55oC to +125oCPackage Types D, F, K, HStorage Temperature Range (TSTG). . . . . . . . . . .-65oC to +150oCLead Temperature (During Soldering) . . . . . . . . . . . . . . . . .+265oCAt Distance 1/16 ± 1/32 Inch (1.59mm± 0.79mm) from case for10s MaximumReliability InformationThermal Resistance . . . . . . . . . . . . . . . .θjaθjcCeramic DIP and FRIT Package. . . . .80oC/W20oC/WFlatpack Package . . . . . . . . . . . . . . . .70oC/W20oC/WMaximum Package Power Dissipation (PD) at +125oCFor TA = -55oC to +100oC (Package Type D, F, K). . . . . .500mWFor TA = +100oC to +125oC (Package Type D, F, K) . . . . .DerateLinearity at 12mW/oC to 200mWDevice Dissipation per Output Transistor . . . . . . . . . . . . . . .100mWFor TA = Full Package Temperature Range (All Package Types)Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+175oCTABLE1.DC ELECTRICAL PERFORMANCE CHARACTERISTICSGROUP ASUBGROUPS12VDD = 18V, VIN = VDD or GNDInput Leakage CurrentIILVIN = VDD or GNDVDD = 20312VDD = 18VInput Leakage CurrentIIHVIN = VDD or GNDVDD = 20312VDD = 18VON-State ResistanceRL = 10K Returned toVDD - VSS/2RONVDD = 5VVIS = VSS to VDD3123VDD = 10VVIS = VSS to VDD123VDD = 15VVIS = VSS to VDD123N Threshold VoltageP Threshold VoltageFunctional (Note 4)VNTHVPTHFVDD = 10V, ISS = -10µAVSS = 0V, IDD = 10µAVDD = 2.8V, VIN = VDD or GNDVDD = 20V, VIN = VDD or GNDVDD = 18V, VIN = VDD or GNDVDD = 3V, VIN = VDD or GNDInput Voltage Low(Note 2)Input Voltage High(Note 2)Input Voltage Low(Note 2)Input Voltage High(Note 2)VILVIHVDD = 5V = VIS Thru 1KVEE = VSSRL = 1K to VSS|ISS| < 2µA on allOFF ChannelsVDD = 15V = VIS Thru 1KVEE = VSSRL = 1K to VSS|ISS| < 2µA on allOFF Channels11778A8B1, 2, 31, 2, 3LIMITSTEMPERATURE+25oC+125oC-55oC+25oC+125oC-55oC+25oC+125oC-55oC+25oC+125oC-55oC+25oC+125oC-55oC+25oC+125oC-55oC+25oC+25oC+25oC+25oC+125oC-55oC+25oC, +125oC, -55oC+25oC, +125oC, -55oC+25oC, +125oC, -55oC+25oC, +125oC, -55oC-3.51.5-VVMIN----100-1000-100-------------2.80.7MAX10100010---100100010010501300800400500310240320220-0.72.8UNITSµAµAµAnAnAnAnAnAnAΩΩΩΩΩΩΩΩΩVVVPARAMETERSupply CurrentSYMBOLIDDCONDITIONS(NOTE 1)VDD = 20V, VIN = VDD or GNDVOH >VOL Specifications CD4067BMS, CD4097BMS TABLE1.DC ELECTRICAL PERFORMANCE CHARACTERISTICSGROUP ASUBGROUPS12VDD = 18VIOZHVOUT = VDDVDD = 20V312VDD = 18VNOTES:1.All voltages referenced to device GND, 100% testing beingimplemented.2.Go/No Go test with limits applied to inputs.3LIMITSTEMPERATURE+25oC+125oC -55oC+25oC+125oC -55oCMIN-0.1-1.0-0.1---MAX---0.11.00.1UNITSµAµAµAµAµAµAPARAMETEROFF Channel LeakageAny Channel OFF or AllChannels OFF(Common OUT/IN)SYMBOLIOZLCONDITIONS(NOTE 1)VOUT = 0VVDD = 20V3.For accuracy, voltage is measured differentially to VDD. Limitis 0.050V max.4.VDD = 2.8/3.0V, RL = 200KVDD = 20V/18V, RL = 10K - 25KTABLE2.AC ELECTRICAL PERFORMANCE CHARACTERISTICSGROUP ASUBGROUPSTEMPERATURE910, 11910, 11+25oC+125oC, -55oC+25oC+125oC, -55oCLIMITSMIN----MAX6081650878UNITSnsnsnsnsPARAMETERPropagation Delay(Signal In to Output)Propagation DelayAddress or Inhibit toSignal Out.(Channel Turning On)NOTES:SYMBOLTPHLTPLHTPZHTPZLCONDITIONSVDD = 5V, VIN = VDD or GND(Notes 1, 2)VDD = 5V, VIN = VDD or GND(Notes 2, 3)1.CL = 50pF, RL = 200K, Input TR, TF < 20ns.2.-55oC and +125oC limits guaranteed, 100% testing being implemented.3.CL = 50pF, RL = 10K, Input TR, TF < 20ns.TABLE3.ELECTRICAL PERFORMANCE CHARACTERISTICSLIMITSPARAMETERSupply CurrentSYMBOLIDDCONDITIONSVDD = 5V, VIN = VDD or GNDNOTES1, 2TEMPERATURE-55oC, +25oC+125oCVDD = 10V, VIN = VDD or GND1, 2-55oC, +25oC+125oCVDD = 15V, VIN = VDD or GND1, 2-55oC, +25oC+125oCInput Voltage LowInput Voltage HighVILVIHVDD = VIS = 10VVEE = VSSRL = 1K to VSSIIS < 2µAON OFF ChannelVDD = 10VVDD = 15V1, 21, 2+25oC, +125oC,-55oC+25oC, +125oC,-55oC+25oC+25oC+25oC+25oCMIN-------+7MAX515010300106003-UNITSµAµAµAµAµAµAVVPropagation DelayAddress or Inhibit toSignal Out.(Channel Turning On)Propagation DelaySignal In to OutputTPZHTPZL1, 2, 41, 2, 4--270190nsnsTPHLTPLHVDD = 10VVDD = 15VVIS = VDD orGND1, 2, 31, 2, 3--3020nsns7-3 元器件交易网www.cecb2b.com Specifications CD4067BMS, CD4097BMS TABLE3.ELECTRICAL PERFORMANCE CHARACTERISTICS (Continued)LIMITSPARAMETERPropagation DelayAddress or Inhibit toSignal Out(Channel Turning Off)Input CapacitanceNOTES:1.All voltages referenced to device GND.2.The parameters listed on Table 3 are controlled via design or process and are not directly tested. These parameters are characterizedon initial design release and upon design changes which would affect these characteristics.3.CL = 50pF, RL = 200K, Input TR, TF < 20ns.4.CL = 50pF, RL = 10K, Input TR, TF < 20ns.5.CL = 50pF, RL = 300Ω, Input TR, TF < 20ns.TABLE4.POST IRRADIATION ELECTRICAL PERFORMANCE CHARACTERISTICSLIMITSPARAMETERSupply CurrentN Threshold VoltageN Threshold VoltageDeltaP Threshold VoltageP Threshold VoltageDeltaFunctionalSYMBOLIDDVNTH∆VTNVTP∆VTPFCONDITIONSVDD = 20V, VIN = VDD or GNDVDD = 10V, ISS = -10µAVDD = 10V, ISS = -10µAVSS = 0V, IDD = 10µAVSS = 0V, IDD = 10µAVDD = 18V, VIN = VDD or GNDVDD = 3V, VIN = VDD or GNDPropagation Delay TimeTPHLTPLHVDD = 5V1, 2, 3, 4+25oCNOTES1, 41, 41, 41, 41, 41TEMPERATURE+25oC+25oC+25oC+25oC+25oC+25oCMIN--2.8-0.2-VOH >VDD/2-MAX25-0.2±12.8±1VOL Specifications CD4067BMS, CD4097BMS TABLE6.APPLICABLE SUBGROUPSCONFORMANCE GROUPGroup AGroup BSubgroup B-5Subgroup B-6Group DMIL-STD-883METHODSample 5005Sample 5005Sample 5005Sample 5005GROUP A SUBGROUPS1, 2, 3, 7, 8A, 8B, 9, 10, 111, 2, 3, 7, 8A, 8B, 9, 10, 11, Deltas1, 7, 91, 2, 3, 8A, 8B, 9Subgroups 1, 2 3Subgroups 1, 2, 3, 9, 10, 11READ AND RECORDNOTE:1. 5% Parameteric, 3% Functional; Cumulative for Static 1 and 2.TABLE7.TOTAL DOSE IRRADIATIONMIL-STD-883METHOD5005TESTPRE-IRRAD1, 7, 9POST-IRRADTable 4READ AND RECORDPRE-IRRAD1, 9POST-IRRADTable 4CONFORMANCE GROUPSGroup E Subgroup 2TABLE8.BURN-IN AND IRRADIATION TEST CONNECTIONSOSCILLATORFUNCTIONPART NUMBERCD4067BMSStatic Burn-In 1 Note 1Static Burn-In 2 Note 1Dynamic Burn-In Note 1Irradiation Note 2PART NUMBERCD4097BMSStatic Burn-In 1 Note 1Static Burn-In 2 Note 1Dynamic Burn-In Note 1Irradiation Note 2NOTE:1.Each pin except VDD and GND will have a series resistor of 10K± 5%, VDD = 18V± 0.5V2.Each pin except VDD and GND will have a series resistor of 47K±5%; Group E, Subgroup 2, sample size is 4 dice/wafer, 0 failures,VDD = 10V± 0.5V3.Pin 10 is at 14kHz, Pin 11 is at 7kHz, Pin 13 is at 1.7kHz, Pin 14 is at 3.5kHz4.Pin 10 is at 14kHz, Pin 11 is at 7kHz, Pin 14 is at 3.5kHZ1, 171, 17-1, 172 - 16, 18 - 231212, 1312242 - 11, 13 - 16,18 - 24242 - 11, 13 - 16,18 - 241, 172 - 9, 15, 16,18 - 2310, 11, 14(Note 4)11-12 - 231212, 1512242 - 11, 13 - 24242 - 11, 13 - 2412 - 9, 16 - 2310, 11, 13, 14(Note 3)OPENGROUNDVDD9V± -0.5V50kHz25kHz7-5 元器件交易网www.cecb2b.com CD4067BMS, CD4097BMS Functional DiagramINHIBIT3INHIBIT41 of 16 DECODERSXIN/OUTOUT/INVDD = 24VSS = 12YIN/OUT01XOUT/IN1 of 8 DECODERS01IN/OUT15VDD = 24VSS = 12701YOUT/IN7CD4067CD4067 TRUTH TABLEAX0101010101010101BX0011001100110011CX0000111100001111DX0000000011111111Inh10000000000000000SELECTEDCHANNELNone012345678910111213141510%tPZL90%50%10%tr = 20ns90%50%CD4097CD4097 TRUTH TABLEAX01010101BX00110011CX00001111Inh100000000SELECTEDCHANNELNone0X, 0Y1X, 1Y2X, 2Y3X, 3Y4X, 4Y5X, 5Y6X, 6Y7X, 7Ytf = 20ns90%50%TURN-ONTIME10%10%tPLZTURN-OFF TIMEFIGURE 1.WAVEFORM CHANNEL BEING TURNED ON, OFFtr = 20ns90%50%10%90%10%TURN-ONTIME tPZH90%50%10%tf = 20nstPHZTURN-OFF TIMEFIGURE 2.PROPAGATION DELAY WAVEFORM, CHANNELBEING TURNED OFF, ON7-6 元器件交易网www.cecb2b.com CD4067BMS, CD4097BMS 16CHANNEL IN/OUTVDD241516141713181219112010219228237263544536271809TGTGTGTGTGTG*****10A11B14C13D15BINARY 1 OF 16 DECODERS WITH INHIBITTGTG1TGCOMMONOUT/INTGINHIBITTGTGTGTGTGTGVDD12VSS*ALL INPUTS PROTECTED BYCMOS PROTECTION NETWORKVSSFIGURE 3.CD4067BMS LOGIC DIAGRAM7-7 元器件交易网www.cecb2b.com CD4067BMS, CD4097BMS VDD247156165188CHANNELIN/OUT Y4319202211220237263548CHANNELIN/OUT X4356271809TGTGTGTG1TGCOMMONX OUT/INTGBINARY 1 OF 8 DECODERS WITH INHIBIT****10A11B14C13TGTGTGINHIBITTGTGTG17TGCOMMONY OUT/INTGTGTGVDD12VSS*ALL INPUTS PROTECTED BYCMOS PROTECTION NETWORKVSSFIGURE 4.CD4097BMS LOGIC DIAGRAM7-8 元器件交易网www.cecb2b.com CD4067BMS, CD4097BMS Typical Performance CharacteristicsSUPPLY VOLTAGE (VDD - VSS) = 5VCHANNEL ON RESISTANCE (RON) (Ω)CHANNEL ON RESISTANCE (RON) (Ω)6005004003002001000-4-3-2-101234INPUT SIGNAL VOLTAGE (VIS) (V)+25oC-55oCAMBIENT TEMPERATURE(TA) = +125oC300250200150100500-10.0-7.5+25oC-55oCAMBIENT TEMPERATURE(TA) = +125oCSUPPLY VOLTAGE (VDD - VSS) = 10V-5.0-2.502.55.07.510.0INPUT SIGNAL VOLTAGE (VIS) (V)FIGURE 5.TYPICAL ON RESISTANCE vs INPUT SIGNALVOLTAGE (ALL TYPES)FIGURE 6.TYPICAL ON RESISTANCE vs INPUT SIGNALVOLTAGE (ALL TYPES)CHANNEL ON RESISTANCE (RON) (Ω)CHANNEL ON RESISTANCE (RON) (Ω)600500400300200AMBIENT TEMPERATURE(TA) = +25oCSUPPLY VOLTAGE (VDD - VSS) = 5VSUPPLY VOLTAGE (VDD - VSS) = 15V300250200150100500AMBIENT TEMPERATURE(TA) = +125oC+25oC-55oC10V1000-10.0-7.5-5.0-2.502.55.07.510.0INPUT SIGNAL VOLTAGE (VIS) (V)15V-10.0-7.5-5.0-2.502.55.07.510.0INPUT SIGNAL VOLTAGE (VIS) (V)FIGURE 7.TYPICAL ON RESISTANCE vs INPUT SIGNALVOLTAGE (ALL TYPES)FIGURE 8.TYPICAL ON RESISTANCE vs INPUT SIGNALVOLTAGE (ALL TYPES)7-9 元器件交易网www.cecb2b.com CD4067BMS, CD4097BMS Chip Dimensions and Pad LayoutsCD4067BMSHDimensions in parentheses are in millimetersand are derived from the basic inch dimensions as indicated. Grid graduations are in mils (10-3 inch)CD4097BMSHSpecial ConsiderationsIn applications where separate power sources are used todrive VDD and the signal inputs, the VDD current capabilityshould exceed VDD/RL (RL = effective external load). Thisprovision avoids permanent current flow or clamp action onthe VDD supply when power is applied or removed from theCD4067BMS or CD4097BMS.When switching from one address to another, some of theON periods of the channels of the multiplexers will overlapmomentarily, which may be objectionable in certain applica-tions. Also when a channel is turned on or off by an addressinput, there is a momentary conductive path from the chan-nel to VSS, which will dump some charge from any capacitorconnected to the input or output of the channel. The inhibitinput turning on a channel will similarly dump some chargeto VSS.The amount of charge dumped is mostly a function of thesignal level above VSS. Typically, at VDD - VSS = 10V, a100pF capacitor connected to the input or output of thechannel will lose 3 to 4% of its voltage at the moment thechannel turns on or off. This loss of voltage is essentiallyindependent of the address or inhibit signal transition time, ifthe transition time is less than 1 - 2µs. When the inhibit sig-nal turns a channel off, there is no charge dumping to VSS.Rather, there is a slight rise in the channel voltage level(65mV typ.) due to capacitive coupling from inhibit input tochannel input or output. Address inputs also couple somevoltage steps onto the channel signal levels.In certain applications, the external load resistor current mayinclude both VDD and signal-line components. To avoiddrawing VDD current when switch current flows into thetransmission gate inputs, the voltage drop across the bidi-rectional switch must not exceed 0.8 volt (calculated fromRON values shown in ELECTRICAL CHARACTERISTICSCHART - Table 1). no VDD current will flow through RL if theswitch current flows into terminal 1 on the CD4067BMS, ter-minals 1 and 17 on the CD4097BMS.METALLIZATION:PASSIVATION:BOND PADS:Thickness: 11kÅ−14kÅ, AL.10.4kÅ - 15.6kÅ, Silane0.004 inches X 0.004 inches MINDIE THICKNESS:0.0198 inches - 0.0218 inchesAll Intersil semiconductor products are manufactured, assembled and tested underISO9000 quality systems certification.Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time withoutnotice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurateand reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties whichmay result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.For information regarding Intersil Corporation and its products, see web sitehttp://www.intersil.com10 因篇幅问题不能全部显示，请点此查看更多更全内容