DDR SDRAM
512Mb G-die DDR SDRAM Specification
66 TSOP-II
with Lead-Free and Halogen-Free
(RoHS compliant)
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K4H510438GK4H510838GK4H511638GTable of Contents
DDR SDRAM
1.0 Key Features ...............................................................................................................................42.0 Ordering Information...................................................................................................................43.0 Operating Frequencies................................................................................................................44.0 Pin Description............................................................................................................................55.0 Package Physical Dimension.....................................................................................................66.0 Block Diagram (32Mbit x 4 / 16Mbit x8 / 8Mbit x16 I/O x4 Banks)............................................77.0 Input/Output Function Description............................................................................................88.0 Command Truth Table.................................................................................................................99.0 General Description...................................................................................................................1010.0 Absolute Maximum Rating .....................................................................................................1011.0 DC Operating Conditions........................................................................................................1012.0 DDR SDRAM IDD Spec Items & Test Conditions..................................................................1113.0 Input/Output Capacitance ......................................................................................................1114.0 Detailed test condition for DDR SDRAM IDD1 & IDD7A ......................................................1215.0 DDR SDRAM IDD spec table ..................................................................................................1316.0 AC Operating Conditions .......................................................................................................1417.0 AC Overshoot/Undershoot specification for Address and Control Pins............................1418.0 Overshoot/Undershoot specification for Data, Strobe and Mask Pins...............................1519.0 AC Timming Parameters & Specifications ...........................................................................1620.0 System Characteristics for DDR SDRAM..............................................................................1721.0 Component Notes....................................................................................................................1822.0 System Notes...........................................................................................................................2023.0 IBIS : I/V Characteristics for Input and Output Buffers........................................................21
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K4H510438GK4H510838GK4H511638GRevision History
Revision1.01.1
MonthSeptemberNovember
Year20092009
- Initial Release
- Changed tRAS max data of -BO(266Mbps) on page 16
History
DDR SDRAM
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K4H510438GK4H510838GK4H511638G1.0 Key Features
• VDD : 2.5V ± 0.2V, VDDQ : 2.5V ± 0.2V for DDR266, 333 • VDD : 2.6V ± 0.1V, VDDQ : 2.6V ± 0.1V for DDR400
• Double-data-rate architecture; two data transfers per clock cycle• Bidirectional data strobe [DQS] (x4,x8) & [L(U)DQS] (x16) • Four banks operation
• Differential clock inputs(CK and CK)
• DLL aligns DQ and DQS transition with CK transition• MRS cycle with address key programs
-. Read latency : DDR266(2.5 Clock), DDR333(2.5 Clock), DDR400(3 Clock) -. Burst length (2, 4, 8)
-. Burst type (sequential & interleave)
• All inputs except data & DM are sampled at the positive going edge of the system clock(CK)• Data I/O transactions on both edges of data strobe • Edge aligned data output, center aligned data input• LDM,UDM for write masking only (x16)• DM for write masking only (x4, x8)• Auto & Self refresh
• 7.8us refresh interval(8K/64ms refresh) • Maximum burst refresh cycle : 8
• 66pin TSOP II Lead-Free & Halogen-Free package• RoHS compliant
DDR SDRAM
2.0 Ordering Information
Part No.K4H510438G-LC/LB0K4H510438G-LC/LB3K4H510838G-LC/LCCK4H510838G-LC/LB3K4H511638G-LC/LCCK4H511638G-LC/LB3
Org.128M x 464M x 8
Max Freq.
B0(DDR266@CL=2.5) B3(DDR333@CL=2.5) CC(DDR400@CL=3) B3(DDR333@CL=2.5)
32M x 16
CC(DDR400@CL=3) B3(DDR333@CL=2.5)
SSTL_2SSTL_2InterfaceSSTL_2
Package
66pin TSOP II
Lead-Free & Halogen-Free66pin TSOP II
Lead-Free & Halogen-Free66pin TSOP II
Lead-Free & Halogen-Free
Note11, 211, 211, 2
Note :
1. \"L\" of part number(12th digit) stands for RoHS compliant and Halogen-Free product.2. \"-B3\"(DDR333, CL=2.5) can support \"-B0\"(DDR266, CL=2.5)
3.0 Operating Frequencies
CC(DDR400@CL=3)
Speed @CL2Speed @CL2.5Speed @CL3CL-tRCD-tRP
166MHz200MHz3-3-3
B3(DDR333@CL=2.5)
133MHz166MHz
-2.5-3-3
B0(DDR266@CL=2.5)
100MHz133MHz
-2.5-3-3
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K4H510438GK4H510838GK4H511638G4.0 Pin Description
DDR SDRAM
32Mb x 1664Mb x 8128Mb x 4VDDDQ0VDDQDQ1DQ2VSSQDQ3DQ4VDDQDQ5DQ6VSSQDQ7NCVDDQLDQSNCVDDNCLDMWECASRASCSNCBA0BA1AP/A10A0A1A2A3VDDVDDDQ0VDDQNCDQ1VSSQNCDQ2VDDQNCDQ3VSSQNCNCVDDQNCNCVDDNCNCWECASRASCSNCBA0BA1AP/A10A0A1A2A3VDDVDDNCVDDQNCDQ0VSSQNCNCVDDQNCDQ1VSSQNCNCVDDQNCNCVDDNCNCWECASRASCSNCBA0BA1AP/A10A0A1A2A3VDD123456789101112131415161718192021222324252627282930313233666564636261605958VSSNCVSSQNCDQ3VDDQNCNCVSSQNCDQ2VDDQNCNCVSSQDQSNCVREFVSSDMCKCKCKENCA12A11A9A8A7A6A5A4VSSVSSDQ7VSSQNCDQ6VDDQNCDQ5VSSQNCDQ4VDDQNCNCVSSQDQSNCVREFVSSDMCKCKCKENCA12A11A9A8A7A6A5A4VSSVSSDQ15VSSQDQ14DQ13VDDQDQ12DQ11VSSQDQ10DQ9VDDQDQ8NCVSSQUDQSNCVREFVSSUDMCKCKCKENCA12A11A9A8A7A6A5A4VSS66Pin TSOPII(400mil x 875mil)(0.65mm Pin Pitch)Bank AddressBA0~BA1Auto Precharge
A10
575655545352515049484746454443424140393837363534512Mb TSOP-II Package Pinout
Organization128Mx464Mx832Mx16
Row AddressA0~A12A0~A12A0~A12
Column AddressA0~A9, A11, A12A0-A9, A11A0-A9
DM is internally loaded to match DQ and DQS identically.
Row & Column address configuration
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K4H510438GK4H510838GK4H511638G5.0 Package Physical Dimension(0.80)(0.50)#66#34DDR SDRAMUnit : mm10.16 ± 0.10(1.50)(0.80)0.665 ± 0.050.210 ± 0.051.00 ± 0.1022.22 ± 0.10(R0.125- 0.0351.20 MAX+0.075 0.15)(10°)(0.50)#1(1.50)#33(10°)(10°)11.76 ± 0.20(10.76)0.05 MIN(0.71)0.65TYP[0.65 ± 0.08]0.075 MAX 0.25(R(R 0.25Detail ADetail B))NOTE1. ( ) IS REFERENCE2. [ ] IS ASS’Y OUT QUALITYDetail A0.25± 0.08Detail B(0° ∼ 8°)0.30± 0.0866Pin TSOP(II) Package Dimension 6 of 24
[(R 0.1(10°)[(4°)0.10 MAX5)Rev. 1.1 November 2009
0.45 ~ 0.750.25TYPK4H510438GK4H510838GK4H511638G6.0 Block Diagram (32M x 4 / 16Mb x 8 / 8Mb x 16 I/O x4 Banks) DDR SDRAMx4/x8/16LWEI/O ControlCK, CKData Input RegisterSerial to parallelLDM (x4/x8)LUDM (x16)Bank Selectx8/x16/3216Mx8/ 8Mx16/ 4Mx32Output Buffer2-bit prefetchSense AMPRefresh CounterRow BufferRow Decoder16Mx8/ 8Mx16/ 4Mx3216Mx8/ 8Mx16/ 4Mx3216Mx8/ 8Mx16/ 4Mx32x8/x16/32x4/x8/16x4/x8/16DQiAddress RegisterCK, CKADDColumn DecoderLCBRLRASCol. BufferLatency & Burst LengthStrobeGen.DLLData StrobeLCKEProgramming RegisterLRASLCBRLWELCASLWCBRCK, CKLDM (x4/x8)LUDM (x16)Timing RegisterDM Input RegisterCK, CKCKECSRASCASWELDM (x4/x8)LUDM (x16) 7 of 24
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7.0 Input/Output Function Description
SYMBOLCK, CK
TYPEInput
DESCRIPTION
DDR SDRAM
Clock : CK and CK are differential clock inputs. All address and control input signals are sam-pled on the positive edge of CK and negative edge of CK. Output (read) data is referenced to both edges of CK. Internal clock signals are derived from CK/CK.
Clock Enable : CKE HIGH activates, and CKE LOW deactivates internal clock signals, and device input buffers and output drivers. Taking CKE Low provides PRECHARGE POWER-DOWN and SELF REFRESH operation (all banks idle), or ACTIVE POWER-DOWN (row ACTIVE in any bank). CKE is synchronous for POWER-DOWN entry and exit, and for SELF REFRESH entry. CKE is asynchronous for SELF REFRESH exit, and for output disable. CKE must be maintained high throughput READ and WRITE accesses. Input buffers, excluding CK, CK and CKE are disabled during POWER-DOWN. Input buffers, excluding CKE are disabled during SELF REFRESH. CKE is an SSTL_2 input, but will detect an LVCMOS Low level after Vdd is applied upon 1st power up, After VREF has become stable during the power on and ini-tialization sequence, it must be maintained for proper operation of the CKE receiver. For proper SELF-REFRESH entry and exit, VREF must be maintained to this input.
Chip Select : CS enables(registered LOW) and disables(registered HIGH) the command decoder. All commands are masked when CS is registered HIGH. CS provides for external bank selection on systems with multiple banks. CS is considered part of the command code.Command Inputs : RAS, CAS and WE (along with CS) define the command being entered.Input Data Mask : DM is an input mask signal for write data. Input data is masked when DM is sampled HIGH along with that input data during a WRITE access. DM is sampled on both edges of DQS. Although DM pins are input only, the DM loading matches the DQ and DQS loading. For the x16, LDM corresponds to the data on DQ0~D7 ; UDM corresponds to the data on DQ8~DQ15. DM may be driven high, low, or floating during READs.
Bank Addres Inputs : BA0 and BA1 define to which bank an ACTIVE, READ, WRITE or PRE-CHARGE command is being applied.
Address Inputs : Provide the row address for ACTIVE commands, and the column address and AUTO PRECHARGE bit for READ/WRITE commands, to select one location out of the mem-ory array in the respective bank. A10 is sampled during a PRECHARGE command to deter-mine whether the PRECHARGE applies to one bank (A10 LOW) or all banks (A10 HIGH). If only one bank is to be precharged, the bank is selected by BA0, BA1. The address inputs also provide the op-code during a MODE REGISTER SET command. BA0 and BA1 define which mode register is loaded during the MODE REGISTER SET command (MRS or EMRS).Data Input/Output : Data bus
Data Strobe : Output with read data, input with write data. Edge-aligned with read data, cen-tered in write data. Used to capture write data. For the x16, LDQS corresponds to the data onDQ0~D7 ; UDQS corresponds to the data on DQ8~DQ15.LDQS is NC on x4 and x8.
No Connect : No internal electrical connection is present.DQ Power Supply : +2.5V ± 0.2V. (+2.6V ±0.1V for DDR400)DQ Ground.
Power Supply : +2.5V ± 0.2V. (+2.6V ±0.1V for DDR400)Ground.
SSTL_2 reference voltage.
CKEInput
CSRAS, CAS, WE
InputInput
LDM,(UDM)Input
BA0, BA1Input
A [0 : 12]Input
DQI/O
LDQS,(U)DQSI/O
NCVDDQVSSQVDDVSSVREF
-SupplySupplySupplySupplyInput
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DDR SDRAM
CKEn-1CKEnHHHLHHHH
XXHLHXXXXXLHLH
CSLLLLHLLLLLHLXHLHLHL
RASLLLHXLHHHLXVXXHXVX
X
XH
XH
XH
CASLLLHXHLLHHXVXXHXV
WELLHHXHHLLLXVXXHXV
XX
899
XX
VX
LH
VVV
LHLH
X
X
BA0,1A10/AP
A0 ~ A9,A11 ~ A12
Note1, 21, 233334444, 675
(V=Valid, X=Don′t Care, H=Logic High, L=Logic Low)8.0 Command Truth Table
COMMAND
RegisterRegister
Extended MRS Mode Register SetAuto Refresh
Refresh
Self
Refresh
EntryExit
OP CODEOP CODE
XX
Row Address
ColumnAddressColumnAddress
Bank Active & Row Addr.Read &
Column AddressWrite &
Column AddressBurst StopPrecharge
Bank SelectionAll Banks
EntryExitEntry
Precharge Power Down Mode
Exit
DM(UDM/LDM for x16 only)No operation (NOP) : Not defined
Auto Precharge DisableAuto Precharge EnableAuto Precharge DisableAuto Precharge Enable
HHLHLHH
Active Power Down
Note :
1. OP Code : Operand Code. A0 ~ A12& BA0 ~ BA1 : Program keys. (@EMRS/MRS)2. EMRS/MRS can be issued only at all banks precharge state.
A new command can be issued 2 clock cycles after EMRS or MRS.3. Auto refresh functions are same as the CBR refresh of DRAM.
The automatical precharge without row precharge command is meant by \"Auto\". Auto/self refresh can be issued only at all banks precharge state.4. BA0 ~ BA1 : Bank select addresses.
If both BA0 and BA1 are \"Low\" at read, write, row active and precharge, bank A is selected. If BA0 is \"High\" and BA1 is \"Low\" at read, write, row active and precharge, bank B is selected. If BA0 is \"Low\" and BA1 is \"High\" at read, write, row active and precharge, bank C is selected. If both BA0 and BA1 are \"High\" at read, write, row active and precharge, bank D is selected.5. If A10/AP is \"High\" at row precharge, BA0 and BA1 are ignored and all banks are selected.6. During burst write with auto precharge, new read/write command can not be issued. Another bank read/write command can be issued after the end of burst.
New row active of the associated bank can be issued at tRP after the end of burst.7. Burst stop command is valid at every burst length.
8. DM(x4/8) sampled at the rising and falling edges of the DQS and Data-in are masked at the both edges (Write DM latency is 0). UDM/LDM(x16 only) sampled at the rising and falling edges of the UDQS/LDQS and Data-in are masked at the both edges (Write UDM/LDM latency is 0).
9. This combination is not defined for any function, which means \"No Operation(NOP)\" in DDR SDRAM.
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DDR SDRAM
32M x 4Bit x 4 Banks / 16M x 8Bit x 4 Banks / 8M x 16Bit x 4 Banks Double Data Rate SDRAM
9.0 General Description
The K4H510438G / K4H510838G / K4H511638G is 536,870,912 bits of double data rate synchronous DRAM organized as 4x33,554,432 / 4x 16,777,216 / 4x 8,388,608 words by 4/8/16bits, fabricated with SAMSUNG′s high performance CMOS technology. Syn-
chronous features with Data Strobe allow extremely high performance up to 400Mb/s per pin. I/O transactions are possible on bothedges of DQS. Range of operating frequencies, programmable burst length and programmable latencies allow the device to be usefulfor a variety of high performance memory system applications.
10.0 Absolute Maximum Rating
Parameter
Voltage on any pin relative to VSS
Voltage on VDD & VDDQ supply relative to VSS
Storage temperatureShort circuit current
SymbolVIN, VOUTVDD, VDDQ
TSTGIOS
Value-0.5 ~ 3.6-1.0 ~ 3.6-55 ~ +150
50
UnitVV°CmA
Note : Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded.
Functional operation should be restricted to recommend operation condition.
Exposure to higher than recommended voltage for extended periods of time could affect device reliability.
Recommended operating conditions(Voltage referenced to VSS=0V, TA=0 to 70°C)11.0 DC Operating Conditions
Parameter
Supply voltage(for device with a nominal VDD of 2.5V for DDR266/333)Supply voltage(for device with a nominal VDD of 2.6V for DDR400)I/O Supply voltage(for device with a nominal VDD of 2.5V for DDR266/333)I/O Supply voltage(for device with a nominal VDD of 2.5V for DDR400)I/O Reference voltage
I/O Termination voltage(system)Input logic high voltageInput logic low voltage
Input Voltage Level, CK and CK inputsInput Differential Voltage, CK and CK inputsV-I Matching: Pullup to Pulldown Current RatioInput leakage currentOutput leakage current
Output High Current(Normal strengh driver) ;VOUT = VTT + 0.84VOutput High Current(Normal strengh driver) ;VOUT = VTT - 0.84VOutput High Current(Half strengh driver) ;VOUT = VTT + 0.45VOutput High Current(Half strengh driver) ;VOUT = VTT - 0.45V
Symbol
VDDVDDVDDQVDDQVREFVTTVIH(DC)VIL(DC)VIN(DC)VID(DC)VI(Ratio)
IIIOZIOHIOLIOHIOL
Min
2.32.52.32.50.49*VDDQVREF-0.04VREF+0.15
-0.3-0.30.360.71-2-5-16.816.8-99
Max
2.72.72.72.70.51*VDDQVREF+0.04VDDQ+0.3VREF-0.15VDDQ+0.3VDDQ+0.6
1.425
Unit
VVVVVVVVVV-uAuAmAmAmAmA
Note
12
34
Note :
1. VREF is expected to be equal to 0.5*VDDQ of the transmitting device, and to track variations in the dc level of same. Peak-to peak noise on VREF may notexceed +/-2% of the dc value.
2. VTT is not applied directly to the device. VTT is a system supply for signal termination resistors, is expected to be set equal to VREF, and must track vari-ations in the DC level of VREF
3. VID is the magnitude of the difference between the input level on CK and the input level on CK.
4. The ratio of the pullup current to the pulldown current is specified for the same temperature and voltage, over the entire temperature and voltage range,for device drain to source voltages from 0.25V to 1.0V. For a given output, it represents the maximum difference between pullup and pulldown driversdue to process variation. The full variation in the ratio of the maximum to minimum pullup and pulldown current will not exceed 1.7 for device drain tosource voltages from 0.1 to 1.0.
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12.0 DDR SDRAM IDD Spec Items & Test Conditions
Conditions
Operating current - One bank Active-Precharge;
tRC=tRCmin; tCK=7.5ns for DDR266, 6ns for DDR333, 5ns for DDR400; DQ,DM and DQS inputs changing once per clock cycle;
address and control inputs changing once every two clock cycles.
Operating current - One bank operation ; One bank open, BL=4, Reads - Refer to the following page for detailed test condition
Precharge power-down standby current; All banks idle; power - down mode;CKE = SymbolIDD0 IDD1 IDD2P Precharge Floating standby current; CS# > =VIH(min);All banks idle; CKE > = VIH(min), tCK=7.5ns for DDR266, 6ns for DDR333, 5ns for DDR400; Address and other control inputs changing once per clock cycle; Vin = Vref for DQ,DQS and DM Precharge Quiet standby current; CS# > = VIH(min); All banks idle; CKE > = VIH(min); tCK=7.5ns for DDR266, 6ns for DDR333, 5ns for DDR400; Address and other control inputs sta-ble at >= VIH(min) or = Active standby current; CS# >= VIH(min); CKE>=VIH(min); one bank active; active - precharge; tRC=tRASmax; tCK=7.5ns for DDR266, 6ns for DDR333, 5ns for DDR400; DQ, DQS and DM inputs changing twice per clock cycle; address and other control inputs changing once per clock cycle Operating current - burst read; Burst length = 2; reads; continuous burst; One bank active; address and control inputs changing once per clock cycle; CL=2.5 at tCK=7.5ns for DDR266, tCK=6ns for DDR333, CL=3 at tCK=5ns for DDR400; 50% of data changing on every transfer; lout = 0 m A Operating current - burst write; Burst length = 2; writes; continuous burst; One bank active address and control inputs changing once per clock cycle; CL=2.5 at tCK=7.5ns for DDR266, 6ns for DDR333, 5ns for DDR400; DQ, DM and DQS inputs changing twice per clock cycle, 50% of input data changing at every burst Auto refresh current; tRC = tRFC(min) which is 10*tCK for DDR266 at tCK=7.5ns; 12*tCK for DDR333 at tCK=6ns, 14*tCK for DDR400 at tCK=5ns; distributed refresh Self refresh current; CKE =< 0.2V; External clock on; tCK=7.5ns for DDR266, 6ns for DDR333, 5ns for DDR400.Operating current - Four bank operation ; Four bank interleaving with BL=4-Refer to the following page for detailed test condition IDD2F IDD2Q IDD3P IDD3N IDD4R IDD4W IDD5IDD6IDD7A 13.0 Input/Output Capacitance Parameter Input capacitance (A0 ~ A12, BA0 ~ BA1, CKE, CS, RAS,CAS, WE)Input capacitance( CK, CK ) Data & DQS input/output capacitance Input capacitance(DM for x4/8, UDM/LDM for x16) ( TA= 25°C, f=100MHz) Symbol CIN1CIN2COUTCIN3 Min 2244 Max 3355 DeltaCap(max) 0.50.250.5 Unit pFpFpFpF Note 441,2,3,41,2,3,4 Note : 1.These values are guaranteed by design and are tested on a sample basis only. 2. Although DM is an input -only pin, the input capacitance of this pin must model the input capacitance of the DQ and DQS pins. This is required to match signal propagation times of DQ, DQS, and DM in the system.3. Unused pins are tied to ground. 4. This parameteer is sampled. For DDR266 and DDR333 VDDQ = +2.5V +0.2V, VDD = +3.3V +0.3V or +0.25V+0.2V. For DDR400, VDDQ = +2.6V +0.1V, VDD = +2.6V +0.1V. For all devices, f=100MHz, tA=25°C, Vout(dc) = VDDQ/2, Vout(peak to peak) = 0.2V. DM inputs are grouped with I/O pins - reflecting the fact that they are matched in loading (to facilitate trace matching at the board level). 11 of 24 Rev. 1.1 November 2009 K4H510438GK4H510838GK4H511638G 14.0 Detailed test condition for DDR SDRAM IDD1 & IDD7A IDD1 : Operating current: One bank operation 1. Typical Case: For DDR266,333: VDD = 2.5V, T=25°C; For DDR400: VDD=2.6V,T=25°C Worst Case : VDD = 2.7V, T= 10°C DDR SDRAM 2. Only one bank is accessed with tRC(min), Burst Mode, Address and Control inputs on NOP edge are changing once per clock cycle. lout = 0mA3. Timing patterns - B0(133Mhz, CL=2.5) : tCK = 7.5ns, CL=2.5, BL=4, tRCD = 3*tCK, tRC = 9*tCK, tRAS = 6*tCKRead : A0 N N R0 N N P0 N N A0 N - repeat the same timing with random address changing*50% of data changing at every burst - B3(166Mhz, CL=2.5) : tCK=6ns, CL=2.5, BL=4, tRCD=3*tCK, tRC = 10*tCK, tRAS=7*tCKRead : A0 N N R0 N N P0 N N A0 N - repeat the same timing with random address changing*50% of data changing at every burst - CC(200Mhz,CL = 3) : tCK = 5ns, CL = 3, BL = 4, tRCD = 3*tCK , tRC = 11*tCK, tRAS = 8*tCK Read : A0 N N R0 N N N N P0 N N - repeat the same timing with random address changing*50% of data changing at every transfer Legend : A=Activate, R=Read, W=Write, P=Precharge, N=DESELECT IDD7A : Operating current: Four bank operation 1. Typical Case: For DDR266,333: VDD = 2.5V, T=25°C; For DDR400: VDD=2.6V,T=25°C Worst Case : VDD = 2.7V, T= 10°C 2. Four banks are being interleaved with tRC(min), Burst Mode, Address and Control inputs on NOP edge are not changing. lout = 0mA4. Timing patterns - B0(133Mhz, CL=2.5) : tCK = 7.5ns, CL=2.5, BL=4, tRRD = 2*tCK, tRCD = 3*tCK, Read with autoprecharge Read : A0 N A1 R0 A2 R1 A3 R2 N R3 N A0 N A1 R0 - repeat the same timing with random address changing*50% of data changing at every burst - B3(166Mhz,CL=2.5) : tCK=6ns, CL=2.5, BL=4, tRRD=2*tCK, tRCD=3*tCK, Read with autoprecharge Read : A0 N A1 R0 A2 R1 A3 R2 N R3 N A0 N A1 R0 - repeat the same timing with random address changing*50% of data changing at every burst - CC(200Mhz,CL = 3) : tCK = 5ns, CL = 3, BL = 4, tRCD = 3*tCK , tRC = 11*tCK, tRAS = 8*tCK Read : A0 N A1 R0 A2 R1 A3 R2 N R3 N A0 N A1 R0 - repeat the same timing with random address changing*50% of data changing at every transfer Legend : A=Activate, R=Read, W=Write, P=Precharge, N=DESELECT 12 of 24 Rev. 1.1 November 2009 K4H510438GK4H510838GK4H511638G 15.0 DDR SDRAM IDD spec table Symbol IDD0IDD1IDD2PIDD2FIDD2QIDD3PIDD3NIDD4RIDD4WIDD5 IDD6 NormalLow powerIDD7A DDR SDRAM (VDD=2.7V, T = 10°C) 128Mx4 (K4H510438G) B3(DDR333@CL=2.5) 6575523201535809511053210 B0(DDR266@CL=2.5) 556552320153575809053175 UnitNotes mAmAmAmAmAmAmAmAmAmAmAmAmA Symbol IDD0IDD1IDD2PIDD2FIDD2QIDD3PIDD3NIDD4RIDD4WIDD5 IDD6 NormalLow powerIDD7A 64Mx8 (K4H510838G) CC(DDR400@CL=3) 759052320204011011013053240 B3(DDR333@CL=2.5) 65805232015409510011053220 UnitNotes mAmAmAmAmAmAmAmAmAmAmAmAmA Symbol IDD0IDD1IDD2PIDD2FIDD2QIDD3PIDD3NIDD4RIDD4WIDD5 IDD6 NormalLow powerIDD7A 32Mx16 (K4H511638G) CC(DDR400@CL=3) 8010052320204514013513553255 B3(DDR333@CL=2.5) 709052320154012012011553230 UnitNotes mAmAmAmAmAmAmAmAmAmAmAmAmA 13 of 24 Rev. 1.1 November 2009 K4H510438GK4H510838GK4H511638G 16.0 AC Operating Conditions Parameter/Condition Input High (Logic 1) Voltage, DQ, DQS and DM signalsInput Low (Logic 0) Voltage, DQ, DQS and DM signals.Input Differential Voltage, CK and CK inputsInput Crossing Point Voltage, CK and CK inputs SymbolVIH(AC)VIL(AC)VID(AC)VIX(AC) 0.70.5*VDDQ-0.2 MinVREF + 0.31 VREF - 0.31VDDQ+0.6Max DDR SDRAM UnitVVVV 12Note 0.5*VDDQ+0.2 Note : 1. VID is the magnitude of the difference between the input level on CK and the input level on CK. 2. The value of VIX is expected to equal 0.5*VDDQ of the transmitting device and must track variations in the dc level of the same. 17.0 AC Overshoot/Undershoot specification for Address and Control Pins Parameter Maximum peak amplitude allowed for overshoot Maximum peak amplitude allowed for undershoot The area between the overshoot signal and VDD must be less than or equal to The area between the undershoot signal and GND must be less than or equal to Specification DDR4001.5 V1.5 V4.5 V-ns4.5 V-ns DDR3331.5 V1.5 V4.5 V-ns4.5 V-ns DDR2661.5 V1.5 V4.5 V-ns4.5 V-ns VDD 5432 Volts (V)10-1-2-3-4-5 0 OvershootMaximum Amplitude = 1.5V Area Maximum Amplitude = 1.5VGND0.68751.52.53.54.55.56.31257.00.51.02.03.04.05.06.06.5 Tims(ns)undershoot AC overshoot/Undershoot Definition 14 of 24 Rev. 1.1 November 2009 K4H510438GK4H510838GK4H511638G DDR SDRAM Specification DDR4001.2 V1.2 V2.4 V-ns2.4 V-ns DDR3331.2 V1.2 V2.4 V-ns2.4 V-ns DDR2661.2 V1.2 V2.4 V-ns2.4 V-ns 18.0 Overshoot/Undershoot specification for Data, Strobe and Mask Pins Parameter Maximum peak amplitude allowed for overshoot Maximum peak amplitude allowed for undershoot The area between the overshoot signal and VDD must be less than or equal to The area between the undershoot signal and GND must be less than or equal to VDDQ Overshoot5432 Volts (V)10-1-2-3-4-5 00.51.01.421.52.02.53.03.54.04.55.05.55.686.06.57.0 Tims(ns) undershootMaximum Amplitude = 1.2VGND Area Maximum Amplitude = 1.2VDQ/DM/DQS AC overshoot/Undershoot Definition 15 of 24 Rev. 1.1 November 2009 K4H510438GK4H510838GK4H511638G 19.0 AC Timming Parameters & Specifications Parameter Row cycle timeRefresh row cycle timeRow active timeRAS to CAS delayRow precharge timeRow active to Row active delayWrite recovery time Last data in to Read commandClock cycle timeCL=2.0CL=2.5CL=3.0Clock high level width Clock low level width DQS-out access time from CK/CKOutput data access time from CK/CKData strobe edge to ouput data edgetCHtCLtDQSCKtACtDQSQSymboltRCtRFCtRAStRCDtRPtRRDtWRtWTRtCK CC(DDR400@CL=3.0)MinMax557040151510152-650.450.45-0.55-0.65-0.90.40.7200.250.20.20.35 0.35 0.60.60.70.7-0.65-0.65100.40.42.21.75752007.8 tHP-tQHStCLminor tCHmin0.4--0.50.6tHP-tQHStCLminor tCHmin0.4+0.65+0.65-12100.550.55+0.55+0.650.41.10.61.2870K B3(DDR333@CL=2.5)MinMax6072421818121517.56-0.450.45-0.6-0.7-0.90.40.7500.250.20.20.35 0.35 0.750.750.80.8-0.7-0.7120.450.452.21.75752007.8--0.550.6tHP-tQHStCLminor tCHmin0.4+0.7+0.71212-0.550.55+0.6+0.70.41.10.61.2570K DDR SDRAM B0(DDR266@CL=2.5)MinMax657545202015151107.5-0.450.45-0.75-0.75-0.90.40.7500.250.20.20.35 0.35 0.90.91.01.0-0.75-0.75150.50.52.21.75752007.8--0.750.6 +0.75 +0.751212-0.550.55+0.75+0.750.51.10.61.25120K UnitNote nsnsnsnsnsnsnstCKnstCKtCKnsnsnstCKtCKtCKnstCKtCKtCKtCKtCKnsnsnsnsnsnsnsnsnsnsnsnstCKusnsnsnstCK22Read PreambletRPRERead PostambletRPSTCK to valid DQS-intDQSSDQS-in setup timetWPRESDQS-in hold timetWPREDQS falling edge to CK rising-setup timetDSSDQS falling edge from CK rising-hold timetDSHDQS-in high level widthtDQSHDQS-in low level widthtDQSLAddress and Control Input setup time(fast)tISAddress and Control Input hold time(fast)tIHAddress and Control Input setup tISAddress and Control Input hold time(slow)Data-out high impedence time from CK/CKData-out low impedence time from CK/CKMode register set cycle timeDQ & DM setup time to DQSDQ & DM hold time to DQS Control & Address input pulse widthDQ & DM input pulse width Exit self refresh to non-Read commandExit self refresh to read commandRefresh interval timeOutput DQS valid windowClock half period Data hold skew factorDQS write postamble timeActive to Read with Auto prechargecommand Autoprecharge write recovery + Precharge timePower Down Exit TimetIHtHZtLZtMRDtDStDHtIPWtDIPWtXSNRtXSRDtREFItQHtHPtQHStWPSTtRAPtDALtPDEX1315, 17~1915, 17~19 16~1916~191111j, kj, k1818 142120,21211215 18 20(tWR/tCK)+(tRP/tCK) 1(tWR/tCK)+(tRP/tCK) 1(tWR/tCK)+(tRP/tCK) 1tCKtCK23 16 of 24 Rev. 1.1 November 2009 K4H510438GK4H510838GK4H511638G 20.0 System Characteristics for DDR SDRAM DDR SDRAM The following specification parameters are required in systems using DDR333, DDR266 & DDR400 devices to ensure proper system performance. these characteristics are for system simulation purposes and are guaranteed by design.Table 1 : Input Slew Rate for DQ, DQS, and DM AC CHARACTERISTICS PARAMETER DQ/DM/DQS input slew rate measured betweenVIH(DC), VIL(DC) and VIL(DC), VIH(DC) SYMBOLDCSLEW DDR400MIN0.5 MAX4.0 DDR333MIN0.5 MAX4.0 DDR266MIN0.5 MAX4.0 UnitsV/ns Notesa, l Table 2 : Input Setup & Hold Time Derating for Slew Rate Input Slew Rate 0.5 V/ns0.4 V/ns0.3 V/ns ∆tIS0+50+100 ∆tIH000 Unitspspsps Notesiii Table 3 : Input/Output Setup & Hold Time Derating for Slew Rate Input Slew Rate 0.5 V/ns0.4 V/ns0.3 V/ns ∆tDS0+75+150 ∆tDH0+75+150 Unitspspsps Noteskkk Table 4 : Input/Output Setup & Hold Derating for Rise/Fall Delta Slew Rate Delta Slew Rate+/- 0.0 V/ns+/- 0.25 V/ns+/- 0.5 V/ns ∆tDS0+50+100 ∆tDH0+50+100 Unitspspsps Notesjjj Table 5 : Output Slew Rate Characteristice (X4, X8 Devices only) Slew Rate Characteristic Pullup Slew RatePulldown slew Typical Range (V/ns)1.2 ~ 2.51.2 ~ 2.5 Minimum(V/ns)1.01.0 Maximum(V/ns) 4.54.5 Notesa,c,d,f,g,hb,c,d,f,g,h Table 6 : Output Slew Rate Characteristice (X16 Devices only) Slew Rate Characteristic Pullup Slew RatePulldown slew Typical Range (V/ns)1.2 ~ 2.51.2 ~ 2.5 Minimum(V/ns)0.70.7 Maximum(V/ns) 5.05.0 Notesa,c,d,f,g,hb,c,d,f,g,h Table 7 : Output Slew Rate Matching Ratio Characteristics AC CHARACTERISTICS PARAMETER Output Slew Rate Matching Ratio (Pullup to Pulldown) DDR400MIN0.67 MAX1.5 DDR333MIN0.67 MAX1.5 DDR266MIN0.67 MAX1.5 Notese, l 17 of 24 Rev. 1.1 November 2009 K4H510438GK4H510838GK4H511638G 21.0 Component Notes 1. All voltages referenced to Vss. DDR SDRAM 2. Tests for ac timing, IDD, and electrical, ac and dc characteristics, may be conducted at nominal reference/supply voltage levels, but the related specifications and device operation are guaranteed for the full voltage range specified. 3. Figure 1 represents the timing reference load used in defining the relevant timing parameters of the part. It is not intended to be either a precise representation of the typical system environment nor a depiction of the actual load presented by a production tester. System designers will use IBIS or other simulation tools to correlate the timing reference load to a system environment. Manufacturers will correlate to their production test conditions (generally a coaxial transmission line terminated at the tester elec- tronics). VDDQ 50Ω Output(VOUT) 30pF Figure 1 : Timing Reference Load 4. AC timing and IDD tests may use a VIL to VIH swing of up to 1.5 V in the test environment, but input timing is still referenced to VREF (or to the crossing point for CK/CK), and parameter specifications are guaranteed for the specified ac input levels under nor- mal use conditions. The minimum slew rate for the input signals is 1 V/ns in the range between VIL(AC) and VIH(AC). 5. The ac and dc input level specifications are as defined in the SSTL_2 Standard (i.e., the receiver will effectively switch as a result of the signal crossing the ac input level and will remain in that state as long as the signal does not ring back above (below) the dc input LOW (HIGH) level. 6. Inputs are not recognized as valid until VREF stabilizes. Exception: during the period before VREF stabilizes, CKE ≤ 0.2VDDQ is recognized as LOW. 7. Enables on.chip refresh and address counters. 8. IDD specifications are tested after the device is properly initialized. 9. The CK/CK input reference level (for timing referenced to CK/CK) is the point at which CK and CK cross; the input reference level for signals other than CK/CK, is VREF. 10. The output timing reference voltage level is VTT. 11. tHZ and tLZ transitions occur in the same access time windows as valid data transitions. These parameters are not referenced to a specific voltage level but specify when the device output is no longer driving (HZ), or begins driving (LZ). 12. The maximum limit for this parameter is not a device limit. The device will operate with a greater value for this parameter, but sys tem performance (bus turnaround) will degrade accordingly. 13. The specific requirement is that DQS be valid (HIGH, LOW, or at some point on a valid transition) on or before this CK edge. A valid transition is defined as monotonic and meeting the input slew rate specifications of the device. when no writes were previ ously in progress on the bus, DQS will be transitioning from High- Z to logic LOW. If a previous write was in progress, DQS could be HIGH, LOW, or transitioning from HIGH to LOW at this time, depending on tDQSS. 14. A maximum of eight AUTO REFRESH commands can be posted to any given DDR SDRAM device.15. For command/address input slew rate ≥ 1.0 V/ns 16. For command/address input slew rate ≥ 0.5 V/ns and < 1.0 V/ns 18 of 24 Rev. 1.1 November 2009 K4H510438GK4H510838GK4H511638G Component Notes 17. For CK & CK slew rate ≥ 1.0 V/ns DDR SDRAM 18. These parameters guarantee device timing, but they are not necessarily tested on each device. They may be guaranteed by device design or tester correlation. 19. Slew Rate is measured between VOH(AC) and VOL(AC). 20. Min (tCL, tCH) refers to the smaller of the actual clock low time and the actual clock high time as provided to the device (i.e. this value can be greater than the minimum specification limits for tCL and tCH).....For example, tCL and tCH are = 50% of the period, less the half period jitter (tJIT(HP)) of the clock source, and less the half period jitter due to crosstalk (tJIT(crosstalk)) into the clock traces. 21. tQH = tHP - tQHS, where: tHP = minimum half clock period for any given cycle and is defined by clock high or clock low (tCH, tCL). tQHS accounts for 1) The pulse duration distortion of on-chip clock circuits; and 2) The worst case push-out of DQS on one tansition followed by the worst case pull-in of DQ on the next transition, both of which are, separately, due to data pin skew and output pattern effects, and p- channel to n-channel variation of the output drivers. 22. tDQSQ Consists of data pin skew and output pattern effects, and p-channel to n-channel variation of the output drivers for any given cycle.23. tDAL = (tWR/tCK) + (tRP/tCK) For each of the terms above, if not already an integer, round to the next highest integer. Example: For DDR266 at CL=2.5 and tCK=7.5ns tDAL = (15 ns / 7.5 ns) + (20 ns/ 7.5ns) = (2) + (3) tDAL = 5 clocks 19 of 24 Rev. 1.1 November 2009 K4H510438GK4H510838GK4H511638G22.0 System Notes a. Pullup slew rate is characteristized under the test conditions as shown in Figure 2. Test point Output 50ΩVSSQ Figure 2 : Pullup slew rate test load b. Pulldown slew rate is measured under the test conditions shown in Figure 3. VDDQ 50Ω Output Test point Figure 3 : Pulldown slew rate test load DDR SDRAM c. Pullup slew rate is measured between (VDDQ/2 - 320 mV +/- 250 mV) Pulldown slew rate is measured between (VDDQ/2 + 320 mV +/- 250 mV) Pullup and Pulldown slew rate conditions are to be met for any pattern of data, including all outputs switching and only one output switching. Example : For typical slew rate, DQ0 is switching For minmum slew rate, all DQ bits are switching from either high to low, or low to high. The remaining DQ bits remain the same as for previous state.d. Evaluation conditions Typical : 25 °C (T Ambient), VDDQ = 2.5V(for DDR266/333) and 2.6V(for DDR400), typical process Minimum : 70 °C (T Ambient), VDDQ = 2.3V(for DDR266/333) and 2.5V(for DDR400), slow - slow process Maximum : 0 °C (T Ambient), VDDQ = 2.7V(for DDR266/333) and 2.7V(for DDR400), fast - fast process e. The ratio of pullup slew rate to pulldown slew rate is specified for the same temperature and voltage, over the entire temperature and voltage range. For a given output, it represents the maximum difference between pullup and pulldown drivers due to process variation.f. Verified under typical conditions for qualification purposes.g. TSOPII package divices only. h. Only intended for operation up to 400 Mbps per pin. i. A derating factor will be used to increase tIS and tIH in the case where the input slew rate is below 0.5V/ns as shown in Table 2. The Input slew rate is based on the lesser of the slew rates detemined by either VIH(AC) to VIL(AC) or VIH(DC) to VIL(DC), similarly for rising transitions. j. A derating factor will be used to increase tDS and tDH in the case where DQ, DM, and DQS slew rates differ, as shown in Tables 3 & 4. Input slew rate is based on the larger of AC-AC delta rise, fall rate and DC-DC delta rise, Input slew rate is based on the lesser of the slew rates determined by either VIH(AC) to VIL(AC) or VIH(DC) to VIL(DC), similarly for rising transitions. The delta rise/fall rate is calculated as: {1/(Slew Rate1)} - {1/(Slew Rate2)} For example : If Slew Rate 1 is 0.5 V/ns and slew Rate 2 is 0.4 V/ns, then the delta rise, fall rate is - 0.5ns/V . Using the table given, this would result in the need for an increase in tDS and tDH of 100 ps. k. Table 3 is used to increase tDS and tDH in the case where the I/O slew rate is below 0.5 V/ns. The I/O slew rate is based on the lesser on the lesser of the AC - AC slew rate and the DC- DC slew rate. The inut slew rate is based on the lesser of the slew rates deter mined by either VIH(AC) to VIL(AC) or VIH(DC) to VIL(DC), and similarly for rising transitions. l. DQS, DM, and DQ input slew rate is specified to prevent double clocking of data and preserve setup and hold times. Signal transi tions through the DC region must be monotonic. 20 of 24 Rev. 1.1 November 2009 K4H510438GK4H510838GK4H511638G23.0 IBIS : I/V Characteristics for Input and Output BuffersDDR SDRAM Output Driver V-I CharacteristicsDDR SDRAMDDR SDRAM Output driver characteristics are defined for full and half strength operation as selected by the EMRS bit A1. Figures 4 and 5 show the driver characteristics graphically, and tables 8 and 9 show the same data in tabular format suitable for inputinto simulation tools. The driver characteristcs evaluation conditions are:Typical 25×CMinimum70×CMaximum 0×CVDD/VDDQ = 2.5V, typical processVDD/VDDQ = 2.3V, slow-slow processVDD/VDDQ = 2.7V, fast-fast processOutput Driver Characteristic Curves Notes:1. The full variation in driver current from minimum to maximum process, temperature and voltage will lie within the outer bounding linesthe of the V-I curve of Figures 4 and 5.2. It is recommended that the \"typical\" IBIS V-I curve lie within the inner bounding lines of the V-I curves of Figures 4 and 5.3. The full variation in the ratio of the \"typical\" IBIS pullup to \"typical\" IBIS pulldown current should be unity +/- 10%, for device drain tosource voltages from 0.1 to1.0. This specification is a design objective only. It is not guaranteed.160Iout(mA)1401201008060402000.00.51.01.52.02.5MaximumTypical HighTypical LowMinimumPulldown Characteristics for Full Strength Output Driver Vout(V)0.00-20-401.02.0Iout(mA)-60-80-100-120-140-160-180-200-220MinumumTypical LowTypical HighMaximumPullup Characteristics for Full Strength Output Driver Vout(V)Figure 4. I/V characteristics for input/output buffers:Pulldown(above) and pullup(below) 21 of 24 Rev. 1.1 November 2009 K4H510438GK4H510838GK4H511638G Pulldown Current (mA) Voltage(V)0.10.20.30.40.50.60.70.80.91.01.11.21.31.41.51.61.71.81.92.02.12.22.32.42.52.62.7 DDR SDRAM pullup Current (mA) Maximum9.618.226.033.941.849.456.863.269.976.382.588.393.899.1103.8108.4112.1115.9119.6123.3126.5129.5132.4135.0137.3139.2140.8 TypicalLow6.012.218.124.129.834.639.443.747.551.354.156.257.959.360.160.561.061.562.062.562.963.363.864.164.664.865.0 TypicalHigh6.813.520.126.633.039.144.249.855.260.365.269.974.278.482.385.989.192.295.397.299.1100.9101.9102.8103.8104.6105.4 Minimum4.69.213.818.423.027.732.236.839.642.644.846.247.147.447.748.048.448.949.149.449.649.849.950.050.250.450.5 TypicalLow-6.1-12.2-18.1-24.0-29.8-34.3-38.1-41.1-41.8-46.0-47.8-49.2-50.0-50.5-50.7-51.0-51.1-51.3-51.5-51.6-51.8-52.0-52.2-52.3-52.5-52.7-52.8 TypicalHigh-7.6-14.5-21.2-27.7-34.1-40.5-46.9-53.1-59.4-65.5-71.6-77.6-83.6-89.7-95.5-101.3-107.1-112.4-118.7-124.0-129.3-134.6-139.9-145.2-150.5-155.3-160.1 Minimum-4.6-9.2-13.8-18.4-23.0-27.7-32.2-36.0-38.2-38.7-39.0-39.2-39.4-39.6-39.9-40.1-40.2-40.3-40.4-40.5-40.6-40.7-40.8-40.9-41.0-41.1-41.2 Maximum-10.0-20.0-29.8-38.8-46.8-54.4-61.8-69.5-77.3-85.2-93.0-100.6-108.1-115.5-123.0-130.4-136.7-144.2-150.5-156.9-163.2-169.6-176.0-181.3-187.6-192.9-198.2 Table 8. Full Strength Driver Characteristics 22 of 24 Rev. 1.1 November 2009 K4H510438GK4H510838GK4H511638G9080706050DDR SDRAMMaximumTypical HighTypical LowMinimumIout(mA)Iout(mA)4030201000.01.02.0Pulldown Characteristics for Weak Output Driver Vout(V)0.00-10-20-30-40-50-60-70-80-901.02.0Iout(mA)MinumumTypical LowTypical HighMaximumPullup Characteristics for Weak Output Driver VOUT(V)Figure 5. I/V characteristics for input/output buffers:Pulldown(above) and pullup(below) 23 of 24 Rev. 1.1 November 2009 K4H510438GK4H510838GK4H511638G Pulldown Current (mA) Voltage(V)0.10.20.30.40.50.60.70.80.91.01.11.21.31.41.51.61.71.81.92.02.12.22.32.42.52.62.7 DDR SDRAM pullup Current (mA) Maximum5.09.914.619.223.628.032.235.839.543.246.750.053.156.158.761.463.565.667.769.871.673.374.976.477.778.879.7 TypicalLow3.46.910.313.616.919.622.324.726.929.030.631.832.833.534.034.334.534.835.135.435.635.836.136.336.536.736.8 TypicalHigh3.87.611.415.118.722.125.028.231.334.136.939.542.044.446.648.650.552.253.955.056.157.157.758.258.759.259.6 Minimum2.65.27.810.413.015.718.220.822.424.125.426.226.626.827.027.227.427.727.828.028.128.228.328.328.428.528.6 TypicalLow-3.5-6.9-10.3-13.6-16.9-19.4-21.5-23.3-24.8-26.0-27.1-27.8-28.3-28.6-28.7-28.9-28.9-29.0-29.2-29.2-29.3-29.5-29.5-29.6-29.7-29.8-29.9 TypicalHigh-4.3-8.2-12.0-15.7-19.3-22.9-26.5-30.1-33.6-37.1-40.3-43.1-45.8-48.4-50.7-52.9-55.0-56.8-58.7-60.0-61.2-62.4-63.1-63.8-64.4-65.1-65.8 Minimum-2.6-5.2-7.8-10.4-13.0-15.7-18.2-20.4-21.6-21.9-22.1-22.2-22.3-22.4-22.6-22.7-22.7-22.8-22.9-22.9-23.0-23.0-23.1-23.2-23.2-23.3-23.3 Maximum-5.0-9.9-14.6-19.2-23.6-28.0-32.2-35.8-39.5-43.2-46.7-50.0-53.1-56.1-58.7-61.4-63.5-65.6-67.7-69.8-71.6-73.3-74.9-76.4-77.7-78.8-79.7 Table 9. Weak Driver Characteristics 24 of 24 Rev. 1.1 November 2009 因篇幅问题不能全部显示，请点此查看更多更全内容