BSIFEATURESVery Low Power/Voltage CMOS SRAM256K X 8 bitDESCRIPTIONBS62LV2005•Wide Vcc operation voltage : 4.5V ~ 5.5V•Very low power consumption :Vcc= 5.0V C-grade : 35mA (Max.) operating currentI-grade : 40mA (Max.) operating current0.6uA (Typ.) CMOS standby current•High speed access time : -70 70ns(Max.) at Vcc = 5.0V-55 55ns(Max.) at Vcc = 5.0V •Automatic power down when chip is deselected•Three state outputs and TTL compatible•Fully static operation•Data retention supply voltage as low as 1.5V•Easy expansion with CE2, CE1, and OE optionsThe BS62LV2005 is a high performance, very low power CMOS Static Random Access Memory organized as 262,144 words by 8 bitsand operates from a wide range of 4.5V to 5.5V supply voltage.Advanced CMOS technology and circuit techniques provide both highspeed and low power features with a typical CMOS standby current of0.6uA and maximum access time of 55ns in 5V operation.Easy memory expansion is provided by an active LOW chip enable (CE1), an active HIGH chip enable (CE2), and active LOWoutput enable (OE) and three-state output drivers. The BS62LV2005 has an automatic power down feature, reducing thepower consumption significantly when chip is deselected.The BS62LV2005 is available in the JEDEC standard 32 pin450mil Plastic SOP, 8mmx13.4mm STSOP and 8mmx20mm TSOP.PRODUCT FAMILYPRODUCTFAMILYBS62LV2005TCBS62LV2005STCBS62LV2005SCBS62LV2005TIBS62LV2005STIBS62LV2005SIOPERATING TEMPERATUREVccRANGESPEED(ns)Vcc=5.0VPOWER DISSIPATIONSTANDBYOperating(ICCSB1, Max)(ICC, Max)PKG TYPETSOP-32STSOP-32SOP-32TSOP-32STSOP-32SOP-32Vcc=5.0VVcc=5.0V+0C to +70C-40OC to +85OCOO4.5V ~ 5.5V55 / 706uA35mA4.5V ~ 5.5V55 / 7025uA40mAPIN CONFIGURATIONSBLOCK DIAGRAM32313029282726252423222120191817OEA10CE1DQ7DQ6DQ5DQ4DQ3GNDDQ2DQ1DQ0A0A1A2A3A13A17A15A16A14A12A7A6A5A4•12345678910111213141516BS62LV2005TCBS62LV2005STCBS62LV2005TIBS62LV2005STIA17A16A14A12A7A6A5A4A3A2A1A0DQ0DQ1DQ2GNDA11A9A8A13WECE2A15VCCA17A16A14A12A7A6A5A4AddressInputBuffer20RowDecoder1024Memory Array1024 x 20482048DQ0DQ1DQ2DQ3DQ4DQ5DQ6DQ78DataInputBuffer8Column I/OWrite DriverSense Amp8256Column Decoder16ControlAddress Input BufferBrilliance Semiconductor Inc.reserves the right to modify document contents without notice.R0201-BS62LV2005•1234567BS62LV2005SC8BS62LV2005SI91011121314151632313029282726252423222120191817VCCA15CE2WEA13A8A9A11OEA10CE1DQ7DQ6DQ5DQ4DQ38DataOutputBufferCE1CE2WEOEVddGndA11A9A8A3A2A1A0A101Revision 2.4April 2002元器件交易网www.cecb2b.com
BSIPIN DESCRIPTIONSBS62LV2005 These 18 address inputsselect one of the 262,144x 8-bit wordsin the RAMCE1 is active LOW and CE2 is active HIGH. Both chip enables mustbe active whendata read from or write to the device. If either chip enable is not active, the device isdeselected and is in a standby power mode. The DQ pins will be in the highimpedance state when the device is deselected.NameA0-A17 Address InputCE1 Chip Enable 1 InputCE2 Chip Enable 2 InputFunctionWE Write Enable InputThe write enable input is active LOW and controls read and writeoperations. With thechip selected, when WE is HIGH and OE is LOW, output data will be present on theDQ pins; when WE is LOW, the data present on the DQ pins will bewritten into theselected memory location.OE Output Enable InputThe output enable input is active LOW. If the output enable is active while the chip isselected and the write enable is inactive, data will be present on the DQ pins and theywill be enabled. The DQ pins will be in the high impedance statewhen OE is inactive.DQ0-DQ7 Data Input/OutputPortsVccGndThese 8 bi-directional ports are used to read data from or write data into the RAM.Power SupplyGroundTRUTH TABLEMODEWECE1CE2OEI/O OPERATIONVccCURRENTNot selected(Power Down)Output DisabledReadWriteXXHHLHXLLLXLHHHXXHLXHigh ZHigh ZDOUTDINICCSB, ICCSB1ICCICCICCABSOLUTE MAXIMUM RATINGS(1)SYMBOLVTERMTBIASTSTGPTIOUTPARAMETERTerminal Voltage withRespect to GNDTemperature Under BiasStorage TemperaturePower DissipationDC Output CurrentOPERATING RANGEUNITSVORATING-0.5 toVcc+0.5-40 to +125-60 to +1501.020RANGECommercialIndustrialAMBIENTTEMPERATURE0 O C to +70 O C-40 O C to +85 O CVcc4.5V~5.5V4.5V~5.5VCCOWmACAPACITANCE (1)(TA = 25oC, f = 1.0 MHz)SYMBOLPARAMETERCONDITIONSMAX.UNITInput1. Stresses greater than those listed under ABSOLUTE MAXIMUMCINVIN=0V6CapacitanceRATINGS may cause permanent damage to the device. This is aInput/OutputCDQstress rating only and functional operation of the device at theseVI/O=0V8Capacitanceor any other conditions above those indicated in the operational sections of this specification is not implied. Exposure toabsolute 1. This parameter is guaranteed and not tested.maximum rating conditions for extended periods may affectreliability.pFpFR0201-BS62LV20052Revision 2.4April 2002元器件交易网www.cecb2b.com
BSIDC ELECTRICAL CHARACTERISTICS ( TA = 0oC to + 70oC )PARAMETER NAME VIL VIH IIL IOL VOL VOH ICCBS62LV2005TEST CONDITIONS Vcc=5.0V PARAMETER MIN. TYP. (1) MAX. UNITSGuaranteed Input Low Voltage(2)Guaranteed Input High (2)VoltageInput Leakage CurrentVcc = Max, VIN = 0V to VccOutput Leakage Current Output Low Voltage Output High Voltage Vcc = Max, CE1= VIH, CE2= VIL, or OE = VIH, VI/O = 0V to VccVcc = Max, IOL = 2mAVcc = Min, IOH = -1mA-0.5 -- 0.8 V 2.2 -- Vcc+0.2-- -- 1 V uA Vcc=5.0V -- -- 1 uA Vcc=5.0V Vcc=5.0V -- -- 0.4 V 2.4 -- -- V -- -- 35 mA Operating Power Supply CE1 = VIL, or CE2 = VIH,Current IDQ = 0mA, F = Fmax(3)CE1 = VIH, or CE2 = VIL,(3)IDQ = 0mA, F = FmaxVcc=5.0V ICCSB Standby Current-TTL Vcc=5.0V -- -- 2 mA CE1ЊVcc-0.2V, CE2Љ0.2V, ICCSB1 Standby Current-CMOS VINЊVcc-0.2V or VINЉ0.2VVcc=5.0V -- 0.6 6 uA 1. Typical characteristics are at TA = 25oC.2. These are absolute values with respect to device ground and all overshoots due to system or tester notice are included.3. Fmax= 1/tRC.DATA RETENTION CHARACTERISTICS ( TA = 0oC to + 70oC )SYMBOLVDRICCDRtCDRtRPARAMETERVcc for Data RetentionData Retention CurrentChip Deselect to DataRetention TimeOperation Recovery TimeTEST CONDITIONSCE1 Њ Vcc - 0.2V, CE2 Љ 0.2V,VINЊ Vcc - 0.2V or VINЉ 0.2VCE1 Њ Vcc - 0.2V, CE2 Љ 0.2V,VINЊ Vcc - 0.2V or VINЉ 0.2VSee Retention WaveformMIN. TYP. (1) MAX.1.5--0TRC (2)--0.01------1----UNITSVuAnsns1. Vcc = 1.5V,TA= + 25OC2.tRC= Read Cycle TimeLOW VCCDATA RETENTION WAVEFORM (1) ( CE1 Controlled )Data Retention ModeVccVIHVccVDR≥1.5VVcctCDR≥CE1 Vcc -0.2VtRVIHCE1LOW VCCDATA RETENTION WAVEFORM (2) ( CE2 Controlled )Data Retention ModeVccVccVDRЊ1.5VVcctCDRtRCE2 Љ0.2VCE2R0201-BS62LV2005VILVIL3Revision 2.4April 2002元器件交易网www.cecb2b.com
BSIAC TEST CONDITIONSInput Pulse LevelsInput Rise and Fall TimesInput and OutputTiming Reference LevelVcc/0V5ns0.5VccWAVEFORMINPUTSBS62LV2005KEY TO SWITCHING WAVEFORMSOUTPUTSMUST BESTEADYWILL BECHANGEFROM H TO LWILL BECHANGEFROM L TO HCHANGE :STATEUNKNOWNCENTERLINE IS HIGHIMPEDANCE”OFF ”STATEMUST BESTEADYMAY CHANGEFROM H TO L1928ΩAC TEST LOADS AND WAVEFORMS5.0VOUTPUT100PFINCLUDINGJIG ANDSCOPE1928Ω5.0VOUTPUTMAY CHANGEFROM L TO HDON T CARE:ANY CHANGEPERMITTEDDOES NOTAPPLY,5PF1020ΩINCLUDINGJIG ANDSCOPE1020ΩFIGURE 1ATHEVENIN EQUIVALENT667ΩFIGURE 1BOUTPUT1.73VALL INPUT PULSESVccGND10%90%90%10%→←→←5nsFIGURE 2AC ELECTRICAL CHARACTERISTICS ( TA = 0oC to + 70oC, Vcc = 5.0V )READ CYCLEJEDECPARAMETERNAMEPARAMETERNAMEDESCRIPTIONRead Cycle TimeAddress Access TimeChip Select Access TimeChip Select Access TimeOutput Enable to Output ValidChip Select to Output Low ZChip Select to Output Low ZOutput Enable to Output in Low ZChip Deselect to Output in High ZChip Deselect to Output in High ZOutput Disable to Output in High ZOutput Disable to Output Address Change(CE1)(CE2)(CE1)(CE2)(CE1)(CE2)BS62LV2005-55MIN. TYP. MAX.BS62LV2005-70MIN. TYP. MAX.UNITtAVAXtAVQVtE1LQVtE2HOVtGLQVtE1LQXtE2HOXtGLQXtE1HQZtE2HQZtGHQZtAXOXtRCtAAtACS1tACS2tOEtCLZ1tCLZ2tOLZtCHZ1tCHZ2tOHZtOH55--------10101000010--------------------------55555530------303025--70--------10101000010--------------------------70707035------353530--nsnsnsnsnsnsnsnsnsnsnsnsR0201-BS62LV20054Revision 2.4April 2002元器件交易网www.cecb2b.com
BSISWITCHING WAVEFORMS (READ CYCLE)READ CYCLE1(1,2,4)BS62LV2005tRCADDRESStDOUTtOHAAtOHREAD CYCLE2(1,3,4)CE1tACS1CE2tt(5)CLZACS2tCHZ1, t(5)CHZ2DOUTREAD CYCLE3(1,4)tRCADDRESStOEAAtOECE1tOHtOLZt(5)CLZ1tACS1tOHZ(5)(1,5)tCHZ1CE2tACS2t(5)CLZ2tCHZ2(2,5)DOUTNOTES:1. WE is high for read Cycle.2. Device is continuously selected when CE1 =VILand CE2=VIH.3. Address valid prior to or coincident with CE1 transition low and/or CE2 transition high.4. OE =VIL.±5. Transition is measured 500mV from steady state withCL= 5pF as shown in Figure 1B.The parameter is guaranteed but not 100% tested.R0201-BS62LV20055Revision 2.4April 2002元器件交易网www.cecb2b.com
BSIAC ELECTRICAL CHARACTERISTICS ( TA = 0oC to + 70oC,Vcc= 5.0V )WRITE CYCLEJEDECPARAMETERNAMEPARAMETERNAMEDESCRIPTIONWrite Cycle TimeChip Select to End of WriteAddress Set up TimeAddress Valid to End of WriteWrite Pulse WidthWrite Recovery TimeWrite Recovery TimeWrite to Output in High ZData to Write Time OverlapData Hold from Write TimeOutput Disable to Output in High ZEnd of Write to Output Active(CE1 , WE)(CE2)BS62LV2005-55MIN. TYP. MAX.BS62LV2005BS62LV2005-70MIN. TYP. MAX.UNITtAVAXtE1LWHtAVWLtAVWHtWLWHtWHAXtE2LAXtWLOZtDVWHtWHDXtGHOZtWHQXtWCtCWtAStAWtWPtWR1tWR2tWHZtDWtDHtOHZtOW55550553000025005--------------------------------------25----25--70700703500030005--------------------------------------30----30--nsnsnsnsnsnsnsnsnsnsnsnsSWITCHING WAVEFORMS (WRITE CYCLE)WRITE CYCLE1(1)ADDRESStWCtWR1OE(3)tCW(5)(11)CE1CE2(5)tWEtCWAW(11)tWR2(2)(3)tAS(4,10)tWPtOHZDOUTttDWDHDINRevision 2.4April 2002R0201-BS62LV20056元器件交易网www.cecb2b.com
BSIWRITE CYCLE2(1,6)BS62LV2005tWCADDRESStCW(5)(11)CE1CE2(5)(11)tWEtCWAWtWR2(2)tWP(3)tAS(4,10)tDHtWHZDOUT(7)(8)tDWtDH(8,9)DINNOTES:1. WE must be high during address transitions.2. The internal write time of the memory is defined by the overlap of CE1 and CE2 active and WE low. All signals must be active to initiate a write and any one signal can terminate a write by goinginactive. The data input setup and hold timing should be referenced to the second transition edgeof the signal that terminates the write.3. TWRis measured from the earlier of CE1 or WE going high or CE2 going low at the end of writecycle.4. During this period, DQ pins are in the output state so that the input signals of opposite phase to theoutputs must not be applied.5. If the CE1 low transition or the CE2 high transition occurs simultaneously with the WE low transitions or after the WE transition, output remain in a high impedance state.6. OE is continuously low (OE =VIL).7.DOUTis the same phase of write data of this write cycle.8.DOUTis the read data of next address.9. If CE1 is low and CE2 is high during this period, DQ pins arein the output state. Then the data inputsignals of opposite phase to the outputs must not be appliedto them.10. Transition is measured 500mV from steady state withCL= 5pF as shown in Figure 1B. The±parameter is guaranteed but not 100% tested.11.TCW is measured from the later of CE1 going low or CE2 going high tothe end of write.R0201-BS62LV20057Revision 2.4April 2002元器件交易网www.cecb2b.com
BSIORDERING INFORMATIONBS62LV2005BS62LV2005X XˀˀY YSPEED70: 70ns55: 55nsGRADEC: +0oC ~ +70oCI: -40oC ~ +85oCPACKAGET: TSOP (8mm x 20mm)ST: Small TSOP (8mm x 13.4mm)S: SOPPACKAGE DIMENSIONSSTSOP -32R0201-BS62LV20058Revision 2.4April 2002元器件交易网www.cecb2b.com
BSIPACKAGE DIMENSIONS (continued)BS62LV2005TSOP -32WITH PLATINGbcc1BASE METALb1SECTION A-ASOP -32R0201-BS62LV20059Revision 2.4April 2002元器件交易网www.cecb2b.com
BSIREVISION HISTORY Revision Description 2.2 2.3 2.4 2001 Data Sheet release Modify Standby Current (Typ. and Max.) Modify some AC parameters. Modify 5V ICCSB1_Max(I-grade) from 10uA to 25uA. BS62LV2005Date Apr. 15, 2001 Note Jun. 29, 2001 April,11,2002 R0201-BS62LV200510Revision 2.4April 2002
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