COMMUNICATION DMA DEVICE

专利名称：COMMUNICATION DMA DEVICE发明人：ISHIBASHI, HIDEKI申请号：EP98919587申请日：19980514公开号：EP1016973A4公开日：20011219

摘要：When the data bus is cut off from the CPU (1) and the transmission ready signal(TXRDY) is activated, the DMA control circuit (10) reads 32 bits of data at once accordingto the lead address of the destined area for storage in the DRAM (2) and the addresswidth that are set by the CPU (1), and stores the data in the transmission buffer (16). Theselector (17) selects 8 bits of data at a time from the transmission buffer (16), the data iswritten to the communication circuit (14) and thus output, the bus release request iscancelled, 8 bits of data is read at a time from transmission buffer (16), and the data iswritten into the communication circuit (14). When the transmission ready signal isprovided once again, the above-described processing is repeated.

申请人：SANYO ELECTRIC CO., LTD.

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