GigaDevice Semiconductor Inc.
GD32F105xx ®™
ARM Cortex-M3 32-bit MCU
Datasheet
GD32F105xx
Table of Contents
List of Figures ............................................................................................................................. 3 List of Tables ............................................................................................................................... 4 1 2
General description ......................................................................................................... 5 Device overview ............................................................................................................... 6 2.1 Device information .............................................................................................................................. 6 2.2 Block diagram ...................................................................................................................................... 8 2.3 Pinouts and pin assignment .............................................................................................................. 9 2.4 Memory map ...................................................................................................................................... 12 2.5 Clock tree ........................................................................................................................................... 13 2.6 Pin definitions .................................................................................................................................... 14 Functional description .................................................................................................. 22
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3.1 ARM Cortex™-M3 core .................................................................................................................. 22 3.2 On-chip memory ................................................................................................................................ 22 3.3 Clock, reset and supply management ........................................................................................... 23 3.4 Boot modes ........................................................................................................................................ 23 3.5 Power saving modes ........................................................................................................................ 24 3.6 Analog to digital converter (ADC) ................................................................................................... 24 3.7 Digital to analog converter (DAC) ................................................................................................... 25 3.8 DMA .................................................................................................................................................... 25 3.9 General-purpose inputs/outputs (GPIOs) ...................................................................................... 25 3.10 Timers and PWM generation ........................................................................................................... 26 3.11 Real time clock (RTC) ...................................................................................................................... 27 3.12 Inter-integrated circuit (I2C) ............................................................................................................. 27 3.13 Serial peripheral interface (SPI) ...................................................................................................... 28 3.14 Universal synchronous asynchronous receiver transmitter (USART) ....................................... 28 3.15 Inter-IC sound (I2S) .......................................................................................................................... 28 3.16 Universal serial bus on-the-go full-speed (USB OTG FS) .......................................................... 29 3.17 Controller area network (CAN) ........................................................................................................ 29 3.18 External memory controller (EXMC) .............................................................................................. 29 3.19 Debug mode ...................................................................................................................................... 30 3.20 Package and operation temperature .............................................................................................. 30 Electrical characteristics .............................................................................................. 31 4.1 Absolute maximum ratings .............................................................................................................. 31 4.2 Recommended DC characteristics ................................................................................................. 31 4.3 Power consumption .......................................................................................................................... 32 4.4 EMC characteristics .......................................................................................................................... 33 4.5 Power supply supervisor characteristics ....................................................................................... 33 4.6 Electrical sensitivity........................................................................................................................... 34 4.7 External clock characteristics .......................................................................................................... 34
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GD32F105xx
4.8 4.9
Internal clock characteristics ........................................................................................................... 35 PLL characteristics ........................................................................................................................... 36
4.10 Memory characteristics .................................................................................................................... 36 4.11 GPIO characteristics ......................................................................................................................... 36 4.12 ADC characteristics .......................................................................................................................... 37 4.13 DAC characteristics .......................................................................................................................... 37 4.14 I2C characteristics ............................................................................................................................ 37 4.15 SPI characteristics ............................................................................................................................ 38
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Package information ..................................................................................................... 39 Ordering Information ..................................................................................................... 41 Revision History ............................................................................................................. 42
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GD32F105xx
List of Figures
Figure 1. GD32F105xx block diagram ...................................................................................................................... 8 Figure 2. GD32F105Zx LQFP144 pinouts ............................................................................................................... 9 Figure 3. GD32F105Vx LQFP100 pinouts ............................................................................................................. 10 Figure 4. GD32F105Rx LQFP64 pinouts ............................................................................................................... 11 Figure 6. GD32F105xx memory map ..................................................................................................................... 12 Figure 7. GD32F105xx clock tree ............................................................................................................................ 13 Figure 8. LQFP package outline .............................................................................................................................. 39
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GD32F105xx
List of Tables
Table 1. GD32F105xx devices features and peripheral list................................................................................... 6 Table 2. GD32F105xx pin definitions ...................................................................................................................... 14 Table 3. Absolute maximum ratings ........................................................................................................................ 31 Table 4. DC operating conditions ............................................................................................................................ 31 Table 5. Power consumption characteristics ......................................................................................................... 32 Table 6. EMS characteristics ................................................................................................................................... 33 Table 7. EMI characteristics ..................................................................................................................................... 33 Table 8. Power supply supervisor characteristics ................................................................................................. 33 Table 9. ESD characteristics .................................................................................................................................... 34 Table 10. Static latch-up characteristics ................................................................................................................ 34 Table 11. High speed external clock (HSE) generated from a crystal/ceramic characteristics ...................... 34 Table 12. Low speed external clock (LSE) generated from a crystal/ceramic characteristics ....................... 35 Table 13. High speed internal clock (HSI) characteristics ................................................................................... 35 Table 14. Low speed internal clock (LSI) characteristics ..................................................................................... 35 Table 15. PLL characteristics ................................................................................................................................... 36 Table 16. Flash memory characteristics ................................................................................................................. 36 Table 17. I/O port characteristics ............................................................................................................................. 36 Table 18. ADC characteristics .................................................................................................................................. 37 Table 19. DAC characteristics ................................................................................................................................. 37 Table 20. I2C characteristics .................................................................................................................................... 37 Table 21. SPI characteristics .................................................................................................................................... 38 Table 22. LQFP package dimensions ..................................................................................................................... 40 Table 23. Part ordering code for GD32F105xx devices ....................................................................................... 41 Table 24. Revision history......................................................................................................................................... 42
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GD32F105xx
1 General description
The GD32F105xx device belongs to the connectivity line of GD32 MCU Family. It is a 32-bit general-purpose microcontroller based on the ARM Cortex™-M3 RISC core with enhanced connectivity performance and best ratio in terms of processing power, reduced power consumption and peripheral set. The Cortex™-M3 is a next generation processor core which is tightly coupled with a Nested Vectored Interrupt Controller (NVIC), SysTick timer and advanced debug support.
The GD32F105xx device incorporates the ARM Cortex™-M3 32-bit processor core operating at 108 MHz frequency with Flash accesses zero wait states to obtain maximum efficiency. It provides up to 1 MB on-chip Flash memory and up to 96 KB SRAM memory. An extensive range of enhanced I/Os and peripherals connected to two APB buses. The devices offer up to three 12-bit ADCs, up to two 12-bit DACs, up to ten general-purpose 16-bit timers, two basic timers plus two PWM advanced-control timer, as well as standard and advanced communication interfaces: up to three SPIs, two ICs, three USARTs, two UARTs, two ISs, two CANs, an USB OTG FS.
The device operates from a 2.6 to 3.6 V power supply and available in –40 to +85 °C temperature range. Several power saving modes provide the flexibility for maximum optimization between wakeup latency and power consumption, an especially important consideration in low power applications.
The above features make the GD32F105xx devices suitable for a wide range of applications, especially in areas such as industrial control, motor drives, power monitor and alarm systems, consumer and handheld equipment, POS, vehicle GPS, LED display and so on.
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GD32F105xx
2
2.1
Device overview
Device information
Table 1. GD32F105xx devices features and peripheral list GD32F105xx Part Number Flash (KB) SRAM (KB) GPTM Advanced TM R8 64 64 4 1 1 2 2 1 5 2 3 2 2 1 51 0 16 3 16 2 RB 128 64 4 1 1 2 2 1 5 2 3 2 2 1 51 0 16 3 16 2 RC 256 96 4 1 1 2 2 1 5 2 3 2 2 1 51 0 16 3 16 2 RD 384 96 4 2 1 2 2 1 5 2 3 2 2 1 51 0 16 3 16 2 LQFP64 RE 512 96 4 2 1 2 2 1 5 2 3 2 2 1 51 0 16 3 16 2 RF 768 96 10 2 1 2 2 1 5 2 3 2 2 1 51 0 16 3 16 2 RG 1024 96 10 2 1 2 2 1 5 2 3 2 2 1 51 0 16 3 16 2 V8 64 64 4 1 1 2 2 1 5 2 3 2 2 1 80 1 16 3 16 2 VB 128 64 4 1 1 2 2 1 5 2 3 2 2 1 80 1 16 3 16 2 Timers SysTick Basic TM Watchdog RTC U(S)ART Connectivity I2C SPI I2S CAN 2.0B USB OTG FS GPIO EXMC EXTI ADC Units Channels DAC Package LQFP100
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GD32F105xx
Table 1. GD32F105xx devices features and peripheral list (continued) GD32F105xx Part Number Flash (KB) SRAM (KB) GPTM Advanced TM VC 256 96 4 1 1 2 2 1 5 2 3 2 2 1 80 1 16 3 16 2 VD 384 96 4 2 1 2 2 1 5 2 3 2 2 1 80 1 16 3 16 2 VE 512 96 4 2 1 2 2 1 5 2 3 2 2 1 80 1 16 3 16 2 LQFP100 VF 768 96 10 2 1 2 2 1 5 2 3 2 2 1 80 1 16 3 16 2 VG 1024 96 10 2 1 2 2 1 5 2 3 2 2 1 80 1 16 3 16 2 ZC 256 96 4 2 1 2 2 1 5 2 3 2 2 1 112 1 16 3 21 2 ZD 384 96 4 2 1 2 2 1 5 2 3 2 2 1 112 1 16 3 21 2 ZE 512 96 4 2 1 2 2 1 5 2 3 2 2 1 112 1 16 3 21 2 LQFP144 ZF ZG 768 1024 96 10 2 1 2 2 1 5 2 3 2 2 1 112 1 16 3 21 2 96 10 2 1 2 2 1 5 2 3 2 2 1 112 1 16 3 21 2 Timers SysTick Basic TM Watchdog RTC U(S)ART Connectivity I2C SPI I2S CAN 2.0B USB OTG FS GPIO EXMC EXTI ADC Units Channels DAC Package
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GD32F105xx
Block diagram
Figure 1. GD32F105xx block diagram
POR/PDRTPIUSW/JTAGPLLICodeFmax: 144MHzFlash Memory FlashARM Cortex-M3 IbusController 1MemoryProcessorDCodeFlash Memory FlashLDOFmax: 108MHz1.2VDbusController 2MemoryHSISystemFMC ControlRST/CLK ControlRegistersRegisters8MHzNVICMasterAHB MatrixSlaveAHB PeripheralsHSE4-16MHzEXMCSlaveLVDGP DMA 1SRAMSRAM7chsSlaveControllerMasterPowered By VDDAGP DMA 25chsAHB to APB AHB to APB USB OTGMasterSlaveBridge 2Bridge 1FSInterrput requestUSART1CAN1SPI1SlaveSlaveWDGADC1GP TM212-bitGP TM3SAR ADCADC2ADC3GP TM4Powered By VDDAGPIOAAPB2: FGP TM5max APB1: FGP TM12GPIOB= 108MHzmax = 54MHzGP TM13GPIOCGP TM14GPIODSPI2/I2S2GPIOESPI3/I2S3GPIOFUSART2GPIOGUSART3ADV TM1UART4ADV TM8UART5GP TM9I2C1GP TM10BSC TM6I2C2GP TM11BSC TM7DAC1EXTIDAC2CAN2
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2.2
GD32F105xx
2.3 Pinouts and pin assignment
Figure 2. GD32F105Zx LQFP144 pinouts
BOOT0VSS_10VDD_10VDD_11VSS_11VDD_3VSS_3PG13PG10PG15PG14PG12PC10PA15PG11PC12PC11PA14PG9PD7PD0PD6PD5PD4PD3PD2PD1PB3PE1PE0PB9PB8PB7PB6PB5PB4PE2PE3PE4PE5PE6VBATPC13-TAMPER-RTCPC14-OSC32_INPC15-OSC32_OUTPF0PF1PF2PF3PF4PF5VSS_5VDD_5PF6PF7PF8PF9PF10OSC_INOSC_OUTNRSTPC0PC1PC2PC3VSSAVREF-VREF+VDDAPA0_WKUPPA1PA212345678914414314214114013913813713613513413313213113012912812712612512412312212112011911811711611511411311211111010910810710610510410310210110099989796959493VDD_2VSS_2NCPA13PA12PA11PA10PA9PA8PC9PC8PC7PC6VDD_9VSS_9PG8PG7PG6PG5PG4PG3PG2PD15PD14VDD_8VSS_8PD13PD12PD11PD10PD9PD8PB15PB14PB13PB12101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172PE11PE14PE12PE15PB10PF11PF12PE9PE10PE13VSS_1PB11PF14PF15PG0PG1PB1PB0PB2PC4PE7PE8PF13PA3PA4PA5PA6PA7PC5VSS_4VSS_7VDD_4VDD_1VDD_7VSS_6VDD_6GigaDevice GD32F105ZxLQFP1449291908988878685848382818079787776757473
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GD32F105xx
Figure 3. GD32F105Vx LQFP100 pinouts
VDD_3VSS_3PE1PE0PB9PB8BOOT0PB7PB6PB5PB4PB3PD7PD6PD5PD4PD3PD2PD1PD0PC12PC11PC10PA15PA14100999897969594939291908988878685848382818079787776PE2175VDD_2PE3274VSS_2PE4373NCPE5472PA13PE6571PA12VBAT670PA11PC13-TAMPER-RTC769PA10PC14-OSC32_IN868PA9PC15-OSC32_OUT967PA8VSS_51066PC9VDD_51165PC8OSC_IN12GigaDevice GD32F105Vx64PC7OSC_OUT13LQFP10063PC6NRST1462PD15PC01561PD14PC11660PD13PC21759PD12PC31858PD11VSSA1957PD10VREF-2056PD9VREF+2155PD8VDDA2254PB15PA0-WKUP2353PB14PA12452PB13PA22551PB1226272829303132333435363738394041424344454647484950PA3VSS_4VDD_4PA4PA5PA6PA7PC4PC5PB0PB1PB2PE7PE8PE9PE10PE11PE12PE13PE14PE15PB10PB11VVSS_1DD_1
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GD32F105xx
Figure 4. GD32F105Rx LQFP64 pinouts
VVDD_3SS_3PB9PB8BOOT0PB7PB6PB5PB4PB3PD2PC12PC11PC10PA15PA1464636261605958575655545352515049VBAT148VDD_2PC13-TAMPER-RTC247VSS_2PC14-OSC32_IN346PA13PC15-OSC32_OUT445PA12PD0-OSC_IN544PA11PD1 OSC_OUT643PA10NRST742PA9PC08GigaDevice GD32F105Rx41PA8PC19LQFP6440PC9PC21039PC8PC31138PC7VSSA1237PC6VDDA1336PB15PA0-WKUP1435PB14PA11534PB13PA21633PB1217181920212223242526272829303132PA3VVSS_4DD_4PA4PA5PA6PA7PC4PC5PB0PB1PB2PB10PB11VVSS_1DD_1
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GD32F105xx
Memory map
Figure 5. GD32F105xx memory map
0x 5FFF FFFF0x 5000 0400reserved0x 5000 0000USB OTG FS0x 4002 3400reserved0x 4002 3000CRC0x 4002 2400reserved0x 4002 2000Flash Interface0x 4002 1400reserved0x 4002 1000RCC0x 4002 0800reserved0x 4002 0400DMA20x 4002 0000DMA10x 4001 5800reserved0x 4001 5400TM110x 4001 5000TM100x 4001 4C00TM90x 4001 4000reserved0x 4001 3C00ADC30x 4001 3800USART10x 4001 3400TM80x 4001 3000SPI10x 4001 2C00TM10x 4001 2800ADC20x 4001 2400ADC10x 4001 2000Port G0x 4001 1C00Port F0x 4001 1800Port E0xFFFF FFFF0x 4001 1400Port D7Cortex-M3 Internal 0x 4001 1000Port CPeripherals0x 4001 0C00Port BPort A0x1FFF FFFF0xE010 00000x 4001 0800reservedEXTI0x1FFF F80F0xE000 00000x 4001 0400Option 0x 4001 0000AFIOBytes6reserved0x 4000 7800reserved0x1FFF F8000x 4000 7400DAC0xC000 00000x 4000 7000PWRSystem 0x 4000 6C00BKPmemory5EXMC register0x 4000 6800bxCAN2bxCAN10x1FFF F0000xA000 10000x 4000 64000xA000 00000x 4000 5C00reserved0x 4000 5800I2C24I2C1reserved0x 4000 54000x 4000 5000UART5UART40x8000 00000x 4000 4C00reservedEXMC bank0x 4000 4800USART30x 4000 4400USART23reserved0x 4000 4000reserved0x 4000 3C00SPI3/I2S30x6000 00000x 4000 3800SPI2/I2S2reserved2reserved0x 4000 34000x 4000 3000IWDG0x 4000 2C00WWDGRTC0x0810 00000x4000 0000Peripherals0x 4000 2800reservedFlash memory0x 4000 2400TM140x0808 0000 bank 2 (512KB)1reserved0x 4000 20000x 4000 1C00TM13Flash memory0x2001 80000x 4000 1800TM120x0800 0000 bank 1 (512KB)0x2000 0000SRAM (96KB)0x 4000 1400TM7TM60x0010 0000reserved0x 4000 1000Aliased to Flash or 0x 4000 0C00TM5system memory 0reserved0x 4000 0800TM4according to BOOT 0x 4000 0400TM30x0000 0000pins configuration0x0000 00000x 4000 0000TM212 / 43
2.4
GD32F105xx
2.5 Clock tree
Figure 6. GD32F105xx clock tree
USB÷PrescalerCK_USB(1,1.5,2)(to USB)I2S2CLKenable(to I2S2)I2S3CLKenable(to I2S3)SCS[1:0]CK_FMCUFMCU enable(by hardware)(to FMCU)CK_HSICK_EXMC00EXMC enable(to EXMC)8 MHzHSI RC/20PLLCK_PLLCK_SYSAHB× 2...3210HCLK1108 MHz max÷PrescalerCK_AHB(1,2...512)108 MHz maxAHB enable(to AHB bus,Cortex-M3,SRAM,DMA)PLLPREDVPLLSELPLLEN01÷8CK_CST(to Cortex-M3 SysTick)/214-16 MHzClockFCLKHSE XTAL0Monitor(free running clock)CK_HSETM2,3,4× 1 or × 2CK_TMXTMX enableto TM2,3,4/1281132.768 KHzLSE OSC01CK_RTCAPB1÷PrescalerCK_APB1PCLK1(to RTC)(1,2,4,8,16)54 MHz maxto APB1 10Peripheral enableperipheralsTM140 KHzRTCSRC[1:0]CK_IWDG× 1 or × 2CK_TM1LSI RCTM1 enable(to IWDG)to TM1APB2CK_SYS÷PrescalerCK_APB2PCLK2(1,2,4,8,16)108 MHz maxto APB2 CK_OUTCK_HSIPeripheral enableperipheralsCK_HSEADCCK_PLL/2÷PrescalerCK_ADCX to ADC1,ADC2(2,4,8,12,16)14 MHz maxLegend:
HSE = High speed external clock HSI = High speed internal clock LSE = Low speed external clock LSI = Low speed internal clock
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GD32F105xx
2.6 Pin definitions
Table 2. GD32F105xx pin definitions LQFP144 LQFP100 I/O Level Pin Type(1) Pins Pin Name LQFP64 (2)Functions description PE2 PE3 PE4 1 2 3 1 2 3 - - - I/O 5VT I/O 5VT I/O 5VT Default: PE2 Alternate: TRACECK, EXMC_A23 Default: PE3 Alternate: TRACED0, EXMC_A19 Default: PE4 Alternate:TRACED1, EXMC_A20 Default: PE5 PE5 4 4 - I/O 5VT Alternate:TRACED2, EXMC_A21 Remap: TM9_CH1 Default: PE6 (4)PE6 VBAT PC13-TAMPER-RTC PC14-OSC32_IN PC15- OSC32_OUT PF0 PF1 PF2 PF3 PF4 PF5 VSS_5 VDD_5 PF6 5 6 7 8 9 10 11 12 13 14 15 5 6 7 8 9 - - - - - - - 1 2 3 4 - - - - - - - - - I/O 5VT Alternate:TRACED3, EXMC_A22 Remap: TM9_CH2 P I/O I/O I/O Default: VBAT Default: PC13 Alternate: TAMPER-RTC Default: PC14 Alternate: OSC32_IN Default: PC15 Alternate: OSC32_OUT Default: PF0 Alternate: EXMC_A0 Default: PF1 Alternate: EXMC_A1 Default: PF2 Alternate: EXMC_A2 Default: PF3 Alternate: EXMC_A3 Default: PF4 Alternate: EXMC_A4 Default: PF5 Alternate: EXMC_A5 Default: VSS_5 Default: VDD_5 Default: PF6 Alternate: ADC3_IN4, EXMC_NIORDRemap: TM10_CH1 Default: PF7 Alternate: ADC3_IN5, EXMC_NREG(3)(3) (3)(4)(3)(3) (3)(3)(3)(3)(3)(3)(3)(3)(3)(3)(3)(3)(3)(4)I/O 5VT I/O 5VT I/O 5VT I/O 5VT I/O 5VT I/O 5VT P P I/O 16 10 17 11 18 - PF7 19 - - I/O 14 / 43
I/O Level (1)
Pins LQFP144 LQFP100 GD32F105xx
Functions description (2)Pin Name LQFP64 Pin TypeRemap: TM11_CH1 Default: PF8 PF8 20 - - I/O Alternate: ADC3_IN6, EXMC_NIOWRRemap: TM13_CH1 Default: PF9 PF9 21 - - I/O Alternate: ADC3_IN7, EXMC_CDRemap: TM14_CH1 Default: PF10 Alternate: ADC3_IN8, EXMC_INTR Default: OSC_IN Remap: PD0 Default: OSC_OUT Remap: PD1 Default: NRST Default: PC0 Alternate: ADC_IN10 Default: PC1 Alternate: ADC_IN11 Default: PC2 Alternate: ADC_IN12 Default: PC3 Alternate: ADC_IN13 Default: VSSA Default: VREF- Default: VREF+ Default: VDDA Default: PA0 Alternate: WKUP, USART2_CTS, ADC_IN0, TM2_CH1_ETR, TM5_CH1, TM8_ETR Default: PA1 Alternate: USART2_RTS, ADC_IN1, TM2_CH2, TM5_CH2 Default: PA2 Alternate: USART2_TX, ADC_IN2, TM2_CH3, TM5_CH3 , TM9_CH1 Default: PA3 Alternate: USART2_RX, ADC_IN3, TM2_CH4, TM5_CH4 , TM9_CH2 Default: VSS_4 Default: VDD_4 Default: PA4 Alternate: SPI1_NSS, USART2_CK, ADC12_IN4; DAC_OUT1Remap: SPI3_NSS, I2S3_WS Default: PA5 Alternate: SPI1_SCK, ADC12_IN5, DAC_OUT2 15 / 43
(3)(3)(3)(3) (3)(4)(3)(4)(3)(3)(3)(4)(4)(3)(3)(3)(4)(3)(3) (3)(4)(3)(3) (3)(4)PF10 OSC_IN OSC_OUT NRST PC0 PC1 PC2 PC3 VSSA VREF- VREF+ VDDA PA0-WKUP 22 - - 5 6 7 8 9 I/O I O I/O I/O I/O 23 12 24 13 25 14 26 15 27 16 28 17 10 I/O 29 18 11 I/O 30 19 12 31 20 32 21 - - P P P P 33 22 13 34 23 14 I/O PA1 PA2 PA3 VSS_4 VDD_4 PA4 35 24 15 I/O 36 25 16 I/O 37 26 17 I/O 38 27 18 39 28 19 P P 40 29 20 I/O PA5 41 30 21 I/O I/O Level (1)
Pins LQFP144 LQFP100 GD32F105xx
Functions description (2)Pin Name LQFP64 Pin TypeDefault: PA6 PA6 42 31 22 I/O Alternate: SPI1_MISO, ADC12_IN6, TM3_CH1, TM8_BKIN, TM13_CH1 Remap: TM1_BKINDefault: PA7 PA7 43 32 23 I/O Alternate: SPI1_MOSI, ADC12_IN7, TM3_CH2, TM8_CH1N, TM14_CH1 Remap: TM1_CH1N PC4 PC5 44 33 24 I/O 45 34 25 I/O Default: PC4 Alternate: ADC12_IN14 Default: PC5 Alternate: ADC12_IN15 Default: PB0 PB0 46 35 26 I/O Alternate: ADC12_IN8, TM3_CH3, TM8_CH2N Remap: TM1_CH2N Default: PB1 PB1 PB2 PF11 PF12 VSS_6 VDD_6 PF13 PF14 PF15 PG0 PG1 47 36 27 I/O Alternate: ADC12_IN9, TM3_CH4, TM8_CH3N Remap: TM1_CH3N Default: PF11 Alternate: EXMC_NIOS16 Default: PF12 Alternate: EXMC_A6 Default: VSS_6 Default: VDD_6 Default: PF13 Alternate: EXMC_A7 Default: PF14 Alternate: EXMC_A8 Default: PF15 Alternate: EXMC_A9 Default: PG0 Alternate: EXMC_A10 Default: PG1 Alternate: EXMC_A11 Default: PE7 PE7 58 38 - I/O 5VT Alternate: EXMC_D4 Remap: TM1_ETR Default: PE8 PE8 59 39 - I/O 5VT Alternate: EXMC_D5 Remap: TM1_CH1N PE9 60 40 - I/O 5VT Default: PE9 Alternate: EXMC_D6 16 / 43
(3)(3)(3)(3)(3)(3)(3)(3)(3)(3)(3)(3)(3)(3)(3)(3)(4)(3) (4)(3)48 37 28 I/O 5VT Default: PB2/BOOT1 49 50 51 52 53 54 55 56 57 - - - - - - - - - - - - - - - - - - I/O 5VT I/O 5VT P P I/O 5VT I/O 5VT I/O 5VT I/O 5VT I/O 5VT I/O Level (1)
Pins LQFP144 LQFP100 GD32F105xx
Functions description (2)Pin Name LQFP64 Pin TypeRemap: TM1_CH1 VSS_7 VDD_7 PE10 61 62 - - - - - P P Default: VSS_7 Default: VDD_7 Default: PE10 Remap: TM1_CH2N Default: PE11 PE11 64 42 - I/O 5VT Alternate: EXMC_D8 Remap: TM1_CH2 Default: PE12 PE12 65 43 - I/O 5VT Alternate: EXMC_D9 Remap: TM1_CH3N Default: PE13 PE13 66 44 - I/O 5VT Alternate: EXMC_D10 Remap: TM1_CH3 Default: PE14 PE14 67 45 - I/O 5VT Alternate: EXMC_D11 Remap: TM1_CH4 Default: PE15 PE15 68 46 - I/O 5VT Alternate: EXMC_D12 Remap: TM1_BKIN Default: PB10 PB10 69 47 29 I/O 5VT Alternate: I2C2_SCL, USART3_TX Remap: TM2_CH3 Default: PB11 PB11 VSS_1 VDD_1 PB12 70 48 30 I/O 5VT Alternate: I2C2_SDA, USART3_RX Remap: TM2_CH4 71 49 31 72 50 32 P P Default: VSS_1 Default: VDD_1 Default: PB12 I2S2_WS, CAN2_RX PB13 PB14 PB15 74 52 34 I/O 5VT 75 53 35 I/O 5VT 76 54 36 I/O 5VT Default: PB13 Alternate: SPI2_SCK, USART3_CTS, TM1_CH1N, I2S2_CK, CAN2_TX Default: PB14 Alternate: SPI2_MISO, USART3_RTS, TM1_CH2N, TM12_CH1 Default: PB15 Alternate: SPI2_MOSI, TM1_CH3N, I2S2_SD, TM12_CH2 Default: PD8 PD8 77 55 - I/O 5VT Alternate: EXMC_D13 Remap: USART3_TX PD9 78 56 - I/O 5VT Default: PD9 Alternate: EXMC_D14 17 / 43
(3)(4)(4)(3)(3)63 41 I/O 5VT Alternate: EXMC_D7 73 51 33 I/O 5VT Alternate: SPI2_NSS, I2C2_SMBAI, USART3_CK, TM1_BKIN, I/O Level (1)
Pins LQFP144 LQFP100 GD32F105xx
Functions description (2)Pin Name LQFP64 Pin TypeRemap: USART3_RX Default: PD10 PD10 79 57 - I/O 5VT Alternate: EXMC_D15 Remap: USART3_CK Default: PD11 PD11 80 58 - I/O 5VT Alternate: EXMC_A16 Remap: USART3_CTS Default: PD12 PD12 81 59 - I/O 5VT Alternate: EXMC_A17 Remap: TM4_CH1, USART3_RTS Default: PD13 PD13 VSS_8 VDD_8 PD14 82 60 83 84 - - - - - - I/O 5VT Alternate: EXMC_A18 Remap: TM4_CH2 P P Default: VSS_8 Default: VDD_8 Default: PD14 Remap: TM4_CH3 Default: PD15 PD15 86 62 - I/O 5VT Alternate: EXMC_D1 Remap: TM4_CH4 PG2 PG3 PG4 PG5 PG6 PG7 PG8 VSS_9 VDD_9 PC6 87 88 89 90 91 92 93 94 95 - - - - - - - - - - - - - - - - - - I/O 5VT I/O 5VT I/O 5VT I/O 5VT I/O 5VT I/O 5VT Default: PG2 Alternate: EXMC_A12 Default: PG3 Alternate: EXMC_A13 Default: PG4 Alternate: EXMC_A14 Default: PG5 Alternate: EXMC_A15 Default: PG6 Alternate: EXMC_INT2 Default: PG7 Alternate: EXMC_INT3 (3)(3)(3)(3)(3)(3)(3)(3)(3)(3)(3)(3)(3)85 61 I/O 5VT Alternate: EXMC_D0 I/O 5VT Default: PG8 P P Default: VSS_9 Default: VDD_9 Default: PC6 (3)(3)96 63 37 I/O 5VT Alternate: I2S2_MCK; TM8_CH1 Remap: TM3_CH1 Default: PC7 PC7 PC8
97 64 38 I/O 5VT Alternate: I2S3_MCK; TM8_CH2 Remap: TM3_CH2 98 65 39 I/O 5VT Default: PC8 18 / 43 (3)(3) I/O Level (1)
Pins LQFP144 LQFP100 GD32F105xx
Functions description (2)Pin Name LQFP64 Pin TypeAlternate: TM8_CH3 Remap: TM3_CH3 Default: PC9 PC9 99 66 40 I/O 5VT Alternate: TM8_CH4 Remap: TM3_CH4 PA8 PA9 PA10 PA11 PA12 PA13 NC VSS_2 VDD_2 PA14 100 67 41 I/O 5VT 101 68 42 I/O 5VT 102 69 43 I/O 5VT 103 70 44 I/O 5VT 104 71 45 I/O 5VT 105 72 46 I/O 5VT 106 73 - P P Default: PA8 Alternate: USART1_CK, TM1_CH1, MCO Default: PA9 Alternate: USART1_TX, TM1_CH2, OTG_FS_VBUS Default: PA10 Alternate: USART1_RX, TM1_CH3, OTG_FS_ID Default: PA11 Alternate: USART1_CTS, CANRX, OTG_FS_DM, TM1_CH4 Default: PA12 Alternate: USART1_RTS, OTG_FS_DP, CAN1_TXTM1_ETR Default: JTMS, SWDIO Remap: PA13 - Default: VSS_2 Default: VDD_2 Default: JTCK, SWCLK Remap: PA14 Default: JTDI PA15 110 77 50 I/O 5VT Alternate: SPI3_NSS, I2S3_WS Remap: TM2_CH1_ETR, PA15, SPI1_NSS Default: PC10 PC10 111 78 51 I/O 5VT Alternate: UART4_TX Remap: USART3_TX, SPI3_SCK, I2S3_CK Default: PC11 PC11 112 79 52 I/O 5VT Alternate: UART4_RX Remap: USART3_RX, SPI3_MISO Default: PC12 PC12 113 80 53 I/O 5VT Alternate: UART5_TX Remap: USART3_CK, SPI3_MOSII2S3_SD Default: PD0 PD0 114 81 5 I/O 5VT Alternate: EXMC_D2 Remap: CAN1_RX, OSC_IN Default: PD1 PD1 115 82 6 I/O 5VT Alternate: EXMC_D3 Remap: CAN1_TX, OSC_OUT PD2 PD3
116 83 54 I/O 5VT 117 84 - Default: PD2 Alternate: TM3_ETR, UART5_RX 19 / 43
(3)(3, (3)(3)(3)(3)(3)(3)(3)(3)(3), (3)(3)107 74 47 108 75 48 109 76 49 I/O 5VT I/O 5VT Default: PD3 I/O Level (1)
Pins LQFP144 LQFP100 GD32F105xx
Functions description (2)Pin Name LQFP64 Pin TypeAlternate: EXMC_CLK Remap: USART2_CTS Default: PD4 PD4 118 85 - I/O 5VT Alternate: EXMC_NOE Remap: USART2_RTS Default: PD5 PD5 VSS_10 VDD_10 PD6 119 86 120 121 - - - - - - I/O 5VT Alternate: EXMC_NWE Remap: USART2_TX Default: VSS_10 Default: VDD_10 Default: PD6 Remap: USART2_RX Default: PD7 PD7 123 88 - I/O 5VT Alternate: EXMC_NE1/EXMC_NCE2 Remap: USART2_CK PG9 PG10 PG11 PG12 PG13 PG14 VSS_11 VDD_11 PG15 PB3 124 125 126 127 128 129 130 131 132 - - - - - - - - - - - - - - - - - - I/O 5VT I/O 5VT I/O 5VT I/O 5VT I/O 5VT I/O 5VT P P Default: PG9 Alternate: EXMC_NE2, EXMC_NCE3 Default: PG10 Alternate: EXMC_NCE4_1, EXMC_NE3 Default: PG11 Alternate: EXMC_NCE4_2 Default: PG12 Alternate: EXMC_NE4 Default: PG13 Alternate: EXMC_A24 Default: PG14 Alternate: EXMC_A25 Default: VSS_10 (3)(3)(3)(3)(3)(3)(3)(3)(3)(3)(3)(3)(3)(3)122 87 I/O 5VT Alternate: EXMC_NWAIT Default: VDD_10 I/O 5VT Default: PG15 Default: JTDO (3)(3)133 89 55 I/O 5VT Alternate:SPI3_SCK, I2S3_CK Remap: PB3, TRACESWO, TM2_CH2, SPI1_SCK Default: NJTRST PB4 134 90 56 I/O 5VT Alternate: SPI3_MISO Remap: TM3_CH1, PB4, SPI1_MISO Default: PB5 (3)PB5 135 91 57 I/O Alternate: I2C1_SMBAI, SPI3_MOSI, I2S3_SD Remap: TM3_CH2, SPI1_MOSI, CAN2_RX Default: PB6 (3)(3)PB6 136 92 58 I/O 5VT Alternate: I2C1_SCL, TM4_CH1, Remap: USART1_TX, CAN2_TX 20 / 43
I/O Level (1)
Pins LQFP144 LQFP100 GD32F105xx
Functions description (2)Pin Name LQFP64 Pin TypeDefault: PB7 PB7 BOOT0 PB8 137 93 59 I/O 5VT Alternate: I2C1_SDA, TM4_CH2, EXMC_NADV Remap: USART1_RX 138 94 60 I Default: BOOT0 Default: PB8 (4) (3)139 95 61 I/O 5VT Alternate: TM4_CH3, TM10_CH1 Remap: I2C1_SCL, CAN1_RX Default: PB9 PB9 140 96 62 I/O 5VT Alternate: TM4_CH4, TM11_CH1 Remap: I2C1_SDA, CAN1_TX Default: PE0 Alternate: TM4_ETR, EXMC_NBL0 Default: PE1 Alternate: EXMC_NBL1 Default: VSS_3 Default: VDD_3 (4)PE0 PE1 VSS_3 VDD_3 141 97 142 98 - - I/O 5VT I/O 5VT P P 143 99 63 144 100 64
Notes:
1. Type: I = input, O = output, P = power. 2. I/O Level: 5VT = 5 V tolerant.
3. Functions are available in GD32F105xC, GD32F105xD, GD32F105xE, GD32F105xF, GD32F105xG
devices.
4. Functions are available in GD32F105xF, GD32F105xG devices.
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3
3.1
Functional description
ARM® Cortex™-M3 core
The Cortex™-M3 processor is the latest generation of ARM processors for embedded systems. It has been developed to provide a low-cost platform that meets the needs of MCU implementation, with a reduced pin count and low-power consumption, while delivering outstanding computational performance and an advanced system response to interrupts.
32-bit ARM Cortex™-M3 processor core Up to 108 MHz operation frequency
Single-cycle multiplication and hardware divider Integrated Nested Vectored Interrupt Controller (NVIC) 24-bit SysTick timer
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The Cortex™-M3 processor is based on the ARMv7 architecture and supports both Thumb and Thumb-2 instruction sets. Some system peripherals listed below are also provided by Cortex™-M3:
Internal Bus Matrix connected with ICode bus, DCode bus, system bus, Private Peripheral Bus (PPB) and debug accesses (AHB-AP) Nested Vectored Interrupt Controller (NVIC) Flash Patch and Breakpoint (FPB) Data Watchpoint and Trace (DWT) Instrument Trace Macrocell (ITM) Memory Protection Unit (MPU)
Serial Wire JTAG Debug Port (SWJ-DP) Trace Port Interface Unit (TPIU)
3.2 On-chip memory
Up to 1024 Kbytes of Flash memory Up to 96 Kbytes of SRAM
The ARM Cortex-M3 processor is structured in Harvard architecture which can use separate buses to fetch instructions and load/store data. 1024 Kbytes of inner Flash and 96 Kbytes of inner SRAM at most is available for storing programs and data, both accessed (R/W) at CPU clock speed with zero wait states. The Figure 6. GD32F105xx memory map shows the memory map of the GD32F105xx series of devices, including code, SRAM, peripheral, and other pre-defined regions.
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3.3 Clock, reset and supply management
Internal 8 MHz factory-trimmed RC and external 4 to 16 MHz crystal oscillator Internal 40 KHz RC calibrated oscillator and external 32.768 KHz crystal oscillator Integrated system clock PLL
2.6 to 3.6 V application supply and I/Os
Supply Supervisor: POR (Power On Reset), PDR (Power Down Reset), and low voltage
detector (LVD)
The Clock Control Unit (CCU) provides a range of oscillator and clock functions. These include speed internal RC oscillator and external crystal oscillator, high speed and low speed two types. Several prescalers allow the configuration of the AHB frequency, the high-speed APB (APB2) and the low-speed APB (APB1) domains. The maximum frequency of the AHB and the high-speed APB domains is 108 MHz. The maximum allowed frequency of the low-speed APB domain is 54 MHz. See Figure 7 for details on the clock tree.
The Reset Control Unit (RCU) controls three kinds of reset: system reset resets the processor core and peripheral IP components. Power-on reset (POR) and power-down reset (PDR) are always active, and ensures proper operation starting from/down to 2.6 V. The device remains in reset mode when VDD is below a specified threshold. The embedded low voltage detector (LVD) monitors the power supply, compares it to the voltage threshold and generates an interrupt as a warning message for leading the MCU into security. Power supply schemes:
VDD range: 2.6 to 3.6 V, external power supply for I/Os and the internal regulator. Provided externally through VDD pins.
VSSA, VDDA range: 2.6 to 3.6 V, external analog power supplies for ADC, reset blocks, RCs and PLL. VDDA and VSSA must be connected to VDD and VSS, respectively.
VBAT range: 1.8 to 3.6 V, power supply for RTC, external clock 32 kHz oscillator and backup registers (through power switch) when VDD is not present.
3.4 Boot modes
At startup, boot pins are used to select one of three boot options:
Boot from main flash memory (default) Boot from system memory Boot from on-chip SRAM
The boot loader is located in the internal boot ROM memory (system memory). It is used to reprogram the Flash memory by using USART1, USART2, CAN2, USB OTG FS in device mode. It also can be used to transfer and update the Flash memory code, the data and the vector table sections. In default condition, boot from bank 1 of Flash memory is selected. It also supports to boot from bank 2 of Flash memory by setting a bit in option bytes.
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3.5 Power saving modes
The MCU supports three kinds of power saving modes to achieve even lower power consumption. They are Sleep mode, Deep-sleep mode, and Standby mode. These operating modes reduce the power consumption and allow the application to achieve the best balance between the CPU operating time, speed and power consumption.
Sleep mode
In sleep mode, only the clock of CPU core is off. All peripherals continue to operate and any interrupt/event can wake up the system.
Deep-sleep mode
In Deep-sleep mode, all clocks in the 1.2V domain are off, and all of the high speed crystal oscillator (HSI, HSE) and PLL are disabled. Only the contents of SRAM and registers are retained. Any interrupt or wakeup event from EXTI lines can wake up the system from the Deep-sleep mode including the 16 external lines, the RTC alarm, the LVD output, and USB wakeup. When exiting the Deep-sleep mode, the HSI is selected as the system clock.
Standby mode
In Standby mode, the whole 1.2V domain is power off, the LDO is shut down, and all of HSI, HSE and PLL are disabled. The contents of SRAM and registers (except Backup Registers) are lost. There are four wakeup sources for the Standby mode, including the external reset from NRST pin, the RTC alarm, the IWDG reset, and the rising edge on WKUP pin.
3.6 Analog to digital converter (ADC)
12-bit SAR ADC engine Up to 1 MSPS conversion rate
Conversion range: VSSA to VDDA (2.6 to 3.6 V) Temperature sensor
Up to three 12-bit 1 μs multi-channel ADCs are integrated in the device. Each is a total of up to 21 multiplexed external channels. An analog watchdog block can be used to detect the channels, which are required to remain within a specific threshold window. A configurable channel management block of analog inputs also can be used to perform conversions in single, continuous, scan or discontinuous mode to support more advanced usages.
The ADCs can be triggered from the events generated by the general-purpose timers (TMx) and the advanced-control timers (TM1 and TM8) with internal connection. The temperature sensor has to generate a voltage that varies linearly with temperature. The conversion range is between 2.6 V < VDDA < 3.6 V. The temperature sensor is internally connected to the ADC_IN16 input channel which is used to convert the sensor output voltage into a digital value.
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3.7 Digital to analog converter (DAC)
Two 12-bit DAC converters of independent output channel 8-bit or 12-bit mode in conjunction with the DMA controller
The two 12-bit buffered DAC channels are used to generate variable analog outputs. The DACs are designed with integrated resistor strings structure. The DAC channels can be triggered by the timer update outputs or EXTI with DMA support. In dual DAC channel operation, conversions could be done independently or simultaneously. The maximum output value of the DAC is VREF+.
3.8 DMA
7 channel DMA 1 controller and 5 channel DMA 2 controller Peripherals supported: Timers, ADC, SPIs, ICs, USARTs, DAC, IS
The flexible general-purpose DMA controllers provide a hardware method of transferring data between peripherals and/or memory without intervention from the CPU, thereby freeing up bandwidth for other system functions. Four types of access method are supported: peripheral to peripheral, peripheral to memory, memory to peripheral, memory to memory Each channel is connected to fixed hardware DMA requests. The priorities of DMA channel requests are determined by software configuration and hardware channel number. Transfer size of source and destination are independent and configurable.
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3.9 General-purpose inputs/outputs (GPIOs)
Up to 112 fast GPIOs, all mappable on 16 external interrupt vectors (EXTI) Analog input/output configurable
Alternate function input/output configurable
There are up to 112 general purpose I/O pins (GPIO) in GD32F105xx, named PA0 ~ PA15 and PB0 ~ PB15, PC0 ~ PC15, PD0 ~ PD15, PE0 ~ PE15, PF0-PF15, PG0-PG15 to implement logic input/output functions. Each of the GPIO ports has related control and configuration registers to satisfy the requirements of specific applications. The external interrupts on the GPIO pins of the device have related control and configuration registers in the External Interrupt Control Unit (EXTI). The GPIO ports are pin-shared with other alternative functions (AFs) to obtain maximum flexibility on the package pins. Each of the GPIO pins can be configured by software as output (push-pull or open-drain), as input (with or without pull-up or pull-down) or as peripheral alternate function. Most of the GPIO pins are shared with digital or analog alternate functions. All GPIOs are high-current capable except for analog inputs.
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3.10 Timers and PWM generation
Up to two 16-bit advanced-control timer (TM1 & TM8), ten 16-bit general-purpose timers
(GPTM), and two 16-bit basic timer (TM6 & TM7)
Up to 4 independent channels of PWM, output compare or input capture for each GPTM
and external trigger input
16-bit, motor control PWM advanced-control timer with programmable dead-time
generation for output match
Encoder interface controller with two inputs using quadrature decoder 24-bit SysTick timer down counter
2 watchdog timers (Independent watchdog and window watchdog)
The advanced-control timer (TM1 & TM8) can be seen as a three-phase PWM multiplexed on 6 channels. It has complementary PWM outputs with programmable dead-time generation. It can also be used as a complete general-purpose timer. The 4 independent channels can be used for
Input capture Output compare
PWM generation (edge- or center-aligned counting modes) Single pulse mode output
If configured as a general-purpose 16-bit timer, it has the same functions as the TMx timer. It can be synchronized with external signals or to interconnect with other GPTMs together which have the same architecture and features.
The general-purpose timer (GPTM), known as TM2 ~ TM5, TM9 ~ TM11, TM12 ~ TM14 can be used for a variety of purposes including general time, input signal pulse width measurement or output waveform generation such as a single pulse generation or PWM output, up to 4 independent channels for input capture/output compare. The GPTM also supports an encoder interface with two inputs using quadrature decoder.
The basic timer, known as TM6 and TM7 are mainly used for DAC trigger generation. They can also be used as a simple 16-bit time base.
The GD32F105xx have two watchdog peripherals, Independent watchdog and window watchdog. They offer a combination of high safety level, flexibility of use and timing accuracy. The independent watchdog timer includes a 12-bit down-counting counter and a 8-bit prescaler, It is clocked from an independent 40 kHz internal RC and as it operates independently of the main clock, it can operate in stop and standby modes. It can be used either as a watchdog to reset the device when a problem occurs, or as a free-running timer for application timeout management.
The window watchdog is based on a 7-bit down counter that can be set as free-running. It can be used as a watchdog to reset the device when a problem occurs. It is clocked from the main clock. It has an early warning interrupt capability and the counter can be frozen in
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debug mode.
The SysTick timer is dedicated for OS, but could also be used as a standard down counter. It features:
A 24-bit down counter Auto reload capability
Maskable system interrupt generation when the counter reaches 0 Programmable clock source
3.11 Real time clock (RTC)
32-bit up-counter with a programmable 20-bit prescaler Alarm function
Interrupt and wake-up event
The real time clock is an independent timer which provides a set of continuously running counters which can be used with suitable software to provide a clock calendar function, and provides an alarm interrupt and an expected interrupt. The RTC features a 32-bit programmable counter for long-term measurement using the compare register to generate an alarm. A 20-bit prescaler is used for the time base clock and is by default configured to generate a time base of 1 second from a clock at 32.768 kHz from external crystal oscillator.
3.12 Inter-integrated circuit (I2C)
Up to two I2C bus interfaces can support both master and slave mode with a frequency up to 400 kHz
Provide arbitration function, optional PEC (packet error checking) generation and checking
Supports 7-bit and 10-bit addressing mode and general call addressing mode
The I2C interface is an internal circuit allowing communication with an external I2C interface which is an industry standard two line serial interface used for connection to external hardware. These two serial lines are known as a serial data line (SDA) and a serial clock line (SCL). The I2C module provides two data transfer rates: 100 kHz of standard mode or 400 kHz of the fast mode. The I2C module also has an arbitration detect function to prevent the situation where more than one master attempts to transmit data to the I2C bus at the same time. A CRC-8 calculator is also provided in I2C interface to perform packet error checking for I2C data.
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3.13 Serial peripheral interface (SPI)
Up to two SPI interfaces with a frequency of up to 18 MHz Support both master and slave mode
Hardware CRC calculation and transmit automatic CRC error checking
The SPI interface uses 4 pins, among which are the serial data input and output lines (MISO & MOSI), the clock line (SCK) and the slave select line (NSS). Both SPIs can be served by the DMA controller. The SPI interface may be used for a variety of purposes, including simplex synchronous transfers on two lines with a possible bidirectional data line or reliable communication using CRC checking.
3.14
Universal synchronous asynchronous receiver transmitter (USART)
Up to three USARTs with operating frequency up to 4.5 MHz
Supports both asynchronous and clocked synchronous serial communication modes IrDA SIR encoder and decoder support LIN break generation and detection
USARTs support ISO 7816-3 compliant smart card interface
The USART (USART1, USART2 and USART3) are used to translate data between parallel and serial interfaces, provides a flexible full duplex data exchange using synchronous or asynchronous transfer. It is also commonly used for RS-232 standard communication. The USART includes a programmable baud rate generator which is capable of dividing the system clock to produce a dedicated clock for the USART transmitter and receiver. The USART also supports DMA function for high speed data communication except UART5.
3.15 Inter-IC sound (I2S)
Two I2S bus Interfaces with sampling frequency from 8 kHz to 192 kHz Support either master or slave mode
The Inter-IC sound (I2S) bus provides a standard communication interface for digital audio applications by 3-wire serial lines. GD32F105xx contain two I2S-bus interfaces that can be operated with 16/32 bit resolution in master or slave mode, pin multiplexed with SPI2 and SPI3. The audio sampling frequency from 8 kHz to 192 kHz is supported with less than 0.5% accuracy error.
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3.16 Universal serial bus on-the-go full-speed (USB OTG FS)
One USB device/host/OTG full-speed Interface with frequency up to 12 Mbit/s Internal main PLL for USB CLK compliantly
The Universal Serial Bus (USB) is a 4-wire bus with 4 bidirectional endpoints. The device controller enables 12 Mbit/s data exchange with integrated transceivers in device/host/OTG mode. Full-speed peripheral is compliant with the USB 2.0 specification. Transaction formatting is performed by the hardware, including CRC generation and checking. The status of a completed USB transfer or error condition is indicated by status registers. An interrupt is also generated if enabled. The dedicated 48 MHz clock is generated from the internal main PLL (the clock source must use a HSE crystal oscillator) and the operating frequency divided from APB1 should be 12 MHz above.
3.17 Controller area network (CAN)
Two CAN2.0B interface with communication frequency up to 1 Mbit/s Internal main PLL for USB CLK compliantly
Controller area network (CAN) is a method for enabling serial communication in field bus. The CAN protocol has been used extensively in industrial automation and automotive applications. It can receive and transmit standard frames with 11-bit identifiers as well as extended frames with 29-bit identifiers. Each CAN has three mailboxes for transmission and two FIFOs of three message deep for reception. It also provides 14 scalable/configurable identifier filter banks for selecting the incoming messages needed and discarding the others.
3.18 External memory controller (EXMC)
Supported external memory: SRAM, PSRAM, ROM and NOR-Flash, NAND Flash and CF card
Up to 16-bit data bus
Support to interface with Motorola 6800 and Intel 8080 type LCD directly
External memory controller (EXMC) is an abbreviation of external memory controller. It is divided in to several sub-banks for external device support, each sub-bank has its own chip selection signal but at one time, only one bank can be accessed. The EXMC support code execution from external memory except NAND Flash and CF card. The EXMC also can be configured to interface with the most common LCD module of Motorola 6800 and Intel 8080 series and reduce the system cost and complexity.
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3.19 Debug mode
Serial wire JTAG debug port (SWJ-DP)
The ARM SWJ-DP Interface is embedded and is a combined JTAG and serial wire debug port that enables either a serial wire debug or a JTAG probe to be connected to the target.
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3.20 Package and operation temperature
LQFP144 (GD32F105Zx), LQFP100 (GD32F105Vx), LQFP64 (GD32F105Rx)
Operation temperature range: -40°C to +85°C (industrial level)
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4
4.1
Electrical characteristics
Absolute maximum ratings
The maximum ratings are the limits to which the device can be subjected without permanently damaging the device. Note that the device is not guaranteed to operate properly at the maximum ratings. Exposure to the absolute maximum rating conditions for extended periods may affect device reliability. Table 3. Absolute maximum ratings Symbol VDD VDDA VBAT VIN IIO TA TSTG TJ Parameter External voltage range External analog supply voltage External battery supply voltage Input voltage on 5V tolerant pin Input voltage on other I/O Maximum current for GPIO pins Operating temperature range Storage temperature range Maximum junction temperature Min VSS - 0.3 VSSA - 0.3 VSS - 0.3 VSS - 0.3 VSS - 0.3 — -40 -55 — Max VSS + 3.6 VSSA + 3.6 VSS + 3.6 VDD + 4.0 4.0 25 +85 +150 125 Unit V V V V V mA °C °C °C 4.2 Recommended DC characteristics
Table 4. DC operating conditions Symbol VDD VDDA VBAT Parameter Supply voltage Analog supply voltage Battery supply voltage Conditions — Same as VDD — Min 2.6 2.6 1.8 Typ 3.3 3.3 — Max Unit 3.6 3.6 3.6 V V V
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4.3 Power consumption
The power measurements specified in the tables represent that code with data executing from on-chip Flash with the following specifications. Table 5. Power consumption characteristics Symbol Parameter Conditions VDD=VBAT=3.3V, HSE=8MHz, System clock=108 MHz, All peripherals enabled VDD=VBAT=3.3V, HSE=8MHz, System clock Supply current (Run mode) =108 MHz, All peripherals disabled VDD=VBAT=3.3V, HSE=8MHz, System clock =72MHz, All peripherals enabled VDD=VBAT=3.3V, HSE=8MHz, System Clock =72 MHz, All peripherals disabled IDD Supply current (Sleep mode) Supply current (Deep-Sleep mode) Supply current VDD=VBAT=3.3V, HSE=8MHz, CPU clock off, All peripherals enabled VDD=VBAT=3.3V, HSE=8MHz, CPU clock off, All peripherals disabled VDD=VBAT=3.3V, All clock off, LSI on, RTC on, All GPIOs analog mode VDD=VBAT=3.3V, LDO off, LSE off, LSI on, Min — — -— — — — Typ 45.2 36.0 32.4 26.1 23.2 13.9 Max Unit — — — — — — mA mA mA mA mA mA — 0.65 1.4 mA (Standby mode) RTC on Battery supply IBAT current (Standby mode) VDD not available, VBAT=3.3V, LDO off, LSE on, LSI off, RTC on VDD not available, VBAT=3.3 V, LDO off, LSE off, LSI on, RTC on — 20.5 — μA μA μA — — 10.1 6.8 — —
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4.4 EMC characteristics
EMS (electromagnetic susceptibility) includes ESD (Electrostatic discharge, positive and negative) and FTB (Burst of Fast Transient voltage, positive and negative) testing result is given in the following table, based on the EMS levels and classes compliant with IEC 61000 series standard.
Table 6. EMS characteristics Symbol VESD Parameter induce a functional disturbance Fast transient voltage burst applied to VFTB induce a functional disturbance through 100 pF on VDD and VSS pins Conditions conforms to IEC 61000-4-2 VDD = 3.3 V, TA = +25 °C conforms to IEC 61000-4-4 Level/Class 3A Voltage applied to all device pins to VDD = 3.3 V, TA = +25 °C 4A EMI (Electromagnetic Interference) emission testing result is given in the following table, compliant with IEC 61967-2 standard which specifies the test board and the pin loading. Table 7. EMI characteristics Symbol Parameter Conditions Tested frequency band 0.1 to 2 MHz 2 to 30 MHz 30 to 130 MHz 130 MHz to 1GHz Conditions 56M 72M <0 2.29 -4.7 -4.7 <0 1.9 -2.1 -2.1 108M <0 0.12 -3.7 -3.7 dBμV Unit VDD = 3.3 V, SEMI Peak level TA = +25 °C, compliant with IEC 61967-2 4.5 Power supply supervisor characteristics
Table 8. Power supply supervisor characteristics Symbol VPOR VPDR VHYST TRSTTEMP Parameter Power on reset threshold power down reset threshold PDR hysteresis Reset temporization Conditions Min Typ Max 2.48 2.43 — — Unit V V V s 2.32 2.40 2.27 2.35 — — 0.05 2
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4.6 Electrical sensitivity
The device is strained in order to determine its performance in terms of electrical sensitivity. Electrostatic discharges (ESD) are applied directly to the pins of the sample. Static latch-up (LU) test is based on the two measurement methods. Table 9. ESD characteristics Symbol VESD(HBM) VESD(CDM) Parameter Electrostatic discharge voltage (human body model) Electrostatic discharge voltage (charge device model) Conditions TA=25 °C; JESD22-A114 TA=25 °C; JESD22-C101 Min — — Typ — — Max 3000 500 Unit V V Table 10. Static latch-up characteristics Symbol I-test LU Vsupply over voltage TA=25 °C; JESD78 — — 5.4 V Parameter Conditions Min — Typ — Max ±100 Unit mA 4.7 External clock characteristics
Table 11. High speed external clock (HSE) generated from a crystal/ceramic characteristics Symbol fHSE CHSE Parameter High Speed External oscillator (HSE) frequency Recommended load capacitance on OSC_IN and OSC_OUT Recommended external feedback RFHSE DHSE IDDHSE tSUHSE resistor between XTALIN and XTALOUT HSE oscillator duty cycle HSE oscillator operating current HSE oscillator startup time — VDD=3.3V, TA=25°C VDD=3.3V, TA=25°C — 48 — — 1 50 1.4 2 52 — — MΩ % Conditions VDD=3.3V — Min 3 — Typ 8 20 Max Unit 32 30 MHz pF μA ms
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Conditions VDD=VBAT=3.3V Min — Typ 32.768 Max 1000 Unit KHz Table 12. Low speed external clock (LSE) generated from a crystal/ceramic characteristics Symbol fLSE Parameter Low Speed External oscillator (LSE) frequency Recommended load CLSE capacitance on OSC32_IN and — OSC32_OUT Recommended external RFLSE DLSE IDDLSE tSULSE feedback resistor between XTAL32IN and XTAL32OUT LSE oscillator duty cycle LSE oscillator operating current LSE oscillator startup time — VDD=VBAT=3.3V VDD=VBAT=3.3V 48 — — 50 1.4 3 52 — — % — — 5 — MΩ — — 15 pF μA s 4.8 Internal clock characteristics
Table 13. High speed internal clock (HSI) characteristics Symbol fHSI Parameter High Speed Internal Oscillator (HSI) frequency HSI oscillator Frequency accuracy, Factory-trimmed HSI oscillator duty cycle HSI oscillator operating current HSI oscillator startup time Conditions VDD=3.3V VDD=3.3V, TA=-40°C ~+105°C VDD=3.3V, TA=0°C ~ +85°C VDD=3.3V, TA=25°C VDD=3.3V, fHSI=8MHz VDD=3.3V, fHSI=8MHz VDD=3.3V, fHSI=8MHz Min — -2.5 -1.2 -1 48 — 1 Typ 8 — — — 50 80 — Max Unit — +1.5 +1.2 +1 52 100 2 MHz % % % % ACCHSI DHSI IDDHSI tSUHSI μA us Table 14. Low speed internal clock (LSI) characteristics Symbol fLSI IDDLSI tSULSI Parameter Low Speed Internal oscillator (LSI) frequency LSI oscillator operating current LSI oscillator startup time Conditions VDD=VBAT=3.3V, TA=-40°C ~ +85°C VDD=VBAT=3.3V, TA=25°C VDD=VBAT=3.3V, TA=25°C Min 30 — — Typ 40 1 — Max Unit 60 2 80 KHz μA μs
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4.9 PLL characteristics
Table 15. PLL characteristics Symbol fPLLIN fPLL tLOCK Parameter PLL input clock frequency PLL output clock frequency PLL lock time Conditions Min 1 16 — Typ 8 — Max Unit 25 108 100 MHz MHz μs 4.10 Memory characteristics
Table 16. Flash memory characteristics Symbol PECYC tRET tPROG tERASE tMERASE Parameter Number of guaranteed program /erase cycles before failure (Endurance) Data retention time Word programming time Page erase time Mass erase time TA=125°C TA=-40°C ~ +85°C TA=-40°C ~ +85°C TA=-40°C ~ +85°C 20 200 60 3.2 — — 100 — — 400 450 9.6 years us ms s TA=-40°C ~ +85°C 100 — — kcycles Conditions Min Typ Max Unit 4.11 GPIO characteristics
Table 17. I/O port characteristics Symbol Parameter Standard IO Low level VIL input voltage 5V-tolerant IO Low level input voltage Standard IO High level VIH input voltage 5V-tolerant IO High level input voltage VOL VOH RPU RPD Low level output voltage High level output voltage Internal pull-up resistor Internal pull-down resistor Conditions VDD=2.6V VDD=2.6V VDD=2.6V VDD=2.6V VDD=2.6V VDD=2.6V VIN=VSS VIN=VDD Min -0.3 -0.3 1.2 1.5 — 2.3 30 30 Typ — — — — — — 40 40 Max Unit 0.95 0.9 4.0 5.5 0.2 — 50 50 V V V V V V kΩ kΩ 36 / 43
GD32F105xx
4.12 ADC characteristics
Table 18. ADC characteristics Symbol VDDA VADCIN fADC fS fADCCONV RADC CADC tSU Parameter Operating voltage ADC input voltage range ADC clock Sampling rate ADC conversion time Input sampling switch resistance Input sampling capacitance Startup time fADC=14MHz No pin/pad capacitance included Conditions Min 2.6 0 0.6 — 1 — — — Typ 3.3 — — — — — 32 — Max Unit 3.6 VREF+ 14 1 18 0.5 — 1 V V MHz MHz μs kΩ pF μs 4.13 DAC characteristics
Table 19. DAC characteristics Symbol VDDA VDACIN RLOAD CLOAD DNE INL Offset GE Parameter Operating voltage DAC input voltage range Load resistance Load capacitance Differential non-linearity error Integral non-linearity Offset error Gain error Resistive load vs. VSSA with buffer ON No pin/pad capacitance included DAC in 12-bit DAC in 12-bit DAC in 12-bit, VREF+ = 3.6 V DAC in 12-bit Conditions Min 2.6 0 5 — — — — — Typ 3.3 — — — — — — — Max Unit 3.6 VREF+ — 50 ±3 ±4 V V kΩ pF LSB LSB % ±12 LSB ±0.5 4.14 I2C characteristics
Table 20. I2C characteristics Symbol fSCL tSCL(H) tSCL(L) Parameter SCL clock frequency SCL clock high time SCL clock low time Conditions Standard mode Min 0 4.0 4.7 Max 100 — — Fast mode Min 0 0.6 1.3 Max 400 — — Unit KHz ns ns 37 / 43
GD32F105xx
4.15 SPI characteristics
Table 21. SPI characteristics Symbol fSCK tSCK(H) tSCK(L) tV(MO) tH(MO) tSU(MI) tH(MI) tSU(NSS) tH(NSS) tA(SO) tDIS(SO) tV(SO) tH(SO) tSU(SI) tH(SI) Parameter SCK clock frequency SCK clock high time SCK clock low time Conditions Min — 19 19 Typ — — — Max Unit 18 — — MHz ns ns SPI master mode Data output valid time Data output hold time Data input setup time Data input hold time — 2 5 5 — — — — 25 — — — ns ns ns ns SPI slave mode NSS enable setup time NSS enable hold time Data output access time Data output disable time Data output valid time Data output hold time Data input setup time Data input hold time fPCLK=54MHz fPCLK=54MHz fPCLK=54MHz 74 37 0 3 — 15 5 4 — — — — — — — — — — 55 10 25 — — — ns ns ns ns ns ns ns ns
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GD32F105xx
5 Package information
Figure 7. LQFP package outline
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GD32F105xx
LQFP100 LQFP144 Max 1.60 0.15 1.45 - - - - - 0.20 7° - 13° 13° 0.20 0.75 - - 0.27 - - - Min - 0.05 1.35 - - - - 0.08 0.08 0° 0° 11° 11° 0.09 0.45 - 0.20 0.17 - - - Typ - - 1.40 22.00 20.00 22.00 20.00 - - 3.5° - 12° 12° - 0.60 1.00 - 0.20 0.50 17.50 17.50 0.20 0.20 0.08 Max 1.60 0.15 1.45 - - - - - 0.20 7° - 13° 13° 0.20 0.75 - - 0.27 - - -
Table 22. LQFP package dimensions Symbol A A1 A2 D D1 E E1 R1 R2 θ θ1 θ2 θ3 c L L1 S b e D2 E2 aaa bbb ccc LQFP64 Min - 0.05 1.35 - - - - 0.08 0.08 0° 0° 11° 11° 0.09 0.45 - 0.20 0.17 - - - Typ - - 1.40 12.00 10.00 12.00 10.00 - - 3.5° - 12° 12° - 0.60 1.00 - 0.20 0.50 7.50 7.50 0.20 0.20 0.08 Max 1.60 0.15 1.45 - - - - - 0.20 7° - 13° 13° 0.20 0.75 - - 0.27 - - - Min - 0.05 1.35 - - - - 0.08 0.08 0° 0° 11° 11° 0.09 0.45 - 0.20 0.17 - - - Typ - - 1.40 16.00 14.00 16.00 14.00 - - 3.5° - 12° 12° - 0.60 1.00 - 0.20 0.50 12.00 12.00 0.20 0.20 0.08 (Original dimensions are in millmeters)
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GD32F105xx
6 Ordering Information
Temperature operating range Table 23. Part ordering code for GD32F105xx devices Ordering code GD32F105R8T6 GD32F105RBT6 GD32F105RCT6 GD32F105RDT6 GD32F105RET6 GD32F105RFT6 GD32F105RGT6 GD32F105V8T6 GD32F105VBT6 GD32F105VCT6 GD32F105VDT6 GD32F105VET6 GD32F105VFT6 GD32F105VGT6 GD32F105ZCT6 GD32F105ZDT6 GD32F105ZET6 GD32F105ZFT6 GD32F105ZGT6 Flash (KB) 64 128 256 384 512 768 1024 64 128 256 384 512 768 1024 256 384 512 768 1024 Package LQFP64 LQFP64 LQFP64 LQFP64 LQFP64 LQFP64 LQFP64 LQFP100 LQFP100 LQFP100 LQFP100 LQFP100 LQFP100 LQFP100 LQFP144 LQFP144 LQFP144 LQFP144 LQFP144 Package type Green Green Green Green Green Green Green Green Green Green Green Green Green Green Green Green Green Green Green Industrial -40°C to +85°C Industrial -40°C to +85°C Industrial -40°C to +85°C Industrial -40°C to +85°C Industrial -40°C to +85°C Industrial -40°C to +85°C Industrial -40°C to +85°C Industrial -40°C to +85°C Industrial -40°C to +85°C Industrial -40°C to +85°C Industrial -40°C to +85°C Industrial -40°C to +85°C Industrial -40°C to +85°C Industrial -40°C to +85°C Industrial -40°C to +85°C Industrial -40°C to +85°C Industrial -40°C to +85°C Industrial -40°C to +85°C Industrial -40°C to +85°C
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GD32F105xx
7 Revision History
Revision No. 1.0 1.1 Description Initial Release Characteristics values modified Date Oct.8, 2013 Nov.10, 2013 Table 24. Revision history
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