BurrĆBrown Productsfrom Texas Instruments
ADS8370
SLAS450–JUNE2005
16-BIT,600-kHz,PSEUDO-DIFFERENTIALINPUT,MICROPOWERSAMPLINGANALOG-TO-DIGITALCONVERTERWITHSERIALINTERFACEANDREFERENCE
FEATURES
••••••••••••••
600-kHzSampleRate
±0.5LSBTyp,±1.25LSBMaxINL±0.4LSBTyp,±0.75LSBMaxDNL16-BitNMC
SINAD89.5dB,SFDR119dBatfi=1kHzHigh-SpeedSerialInterfaceupto40MHzOnboardReferenceBufferOnboard4.096-VReference
Pseudo-DifferentialInput,0Vto4.2VOnboardConversionClock
SelectableOutputFormat,2'sComplementorStraightBinaryZeroLatency
WideDigitalSupplyLowPower:
–110mWat600kHz
–15mWDuringNapMode–10µWDuringPowerDown28-Pin6x6QFNPackage
•
PincompatibleWith18-BitADS8380
APPLICATIONS
•••••
MedicalInstrumentsOpticalNetworkingTransducerInterface
HighAccuracyDataAcquisitionSystemsMagnetometers
DESCRIPTION
TheADS8370isahighperformance16-bit,600-kHzA/Dconverterwithsingle-ended(pseudo-differential)input.Thedeviceincludesan16-bitcapacitor-basedSARA/Dconverterwithinherentsampleandhold.TheADS8370offersahigh-speedCMOSserialinterfacewithclockspeedsupto40MHz.
TheADS8370isavailableina28lead6×6QFNpackageandischaracterizedovertheindustrial–40°Cto85°Ctemperaturerange.
•
HighSpeedSARConverterFamily
Type/Speed
18-BitPseudo-Diff
18-BitPseudo-Bipolar,FullyDiff16-BitPseudo-Diff
16-BitPseudo-Bipolar,FullyDiff14-BitPseudo-Diff12-BitPseudo-Diff
ADS7886
500kHzADS8383
~600kHzADS8381ADS8380(S)ADS8382(S)ADS8370(S)ADS8372(S)
ADS8371
ADS8401/05ADS8402/06ADS7890(S)
ADS8411ADS8412
ADS7891
ADS7881
750kHZ
1MHz
1.25MHz
2MHz
3MHz
4MHz
SAR+IN−INREFIN4.096-VInternalReference+_CDACComparatorOutputLatchesand3-StateDriversFSSCLKSB/2CSDOREFOUT
ClockConversionandControl LogicCSCONVSTBUSYPDPleasebeawarethatanimportantnoticeconcerningavailability,standardwarranty,anduseincriticalapplicationsofTexasInstrumentssemiconductorproductsanddisclaimerstheretoappearsattheendofthisdatasheet.
PRODUCTIONDATAinformationiscurrentasofpublicationdate.ProductsconformtospecificationsperthetermsoftheTexasInstrumentsstandardwarranty.Productionprocessingdoesnotnecessarilyincludetestingofallparameters.
Copyright©2005,TexasInstrumentsIncorporated
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Thesedeviceshavelimitedbuilt-inESDprotection.TheleadsshouldbeshortedtogetherorthedeviceplacedinconductivefoamduringstorageorhandlingtopreventelectrostaticdamagetotheMOSgates.
ORDERINGINFORMATION(1)
MODEL
MAXIMUMINTEGRALLINEARITY(LSB)
MAXIMUMDIFFERENTIALLINEARITY(LSB)
NOMISSINGCODESRESOLUTION
(BIT)
PACKAGETYPE
PACKAGEDESIGNATOR
TEMPERATURE
RANGE
ORDERINGINFORMATIONADS8370IRHPT
RHP
–40°Cto85°C
ADS8370IRHPRADS8370IBRHPT
RHP
–40°Cto85°C
ADS8370IBRHPR
TRANSPORTMEDIAQUANTITYSmallTapeand
reel250Tapeandreel
2500SmallTapeand
reel250Tapeandreel
2500
ADS8370I±2–1/1.516
28Pin6×6QFN
ADS8370IB±1.25±0.7516
28Pin6×6QFN
(1)
Forthemostcurrentpackageandorderinginformation,seethePackageOptionAddendumattheendofthisdocument,orseetheTIwebsiteatwww.ti.com.
ABSOLUTEMAXIMUMRATINGS
overoperatingfree-airtemperaturerangeunlessotherwisenoted(1)
UNIT
+INtoAGND
Voltage
–INtoAGND+VAtoAGND+VBDtoBDGND
DigitalinputvoltagetoBDGNDDigitalinputvoltageto+VA
Operatingfree-airtemperaturerange,TAStoragetemperaturerange,TstgJunctiontemperature(TJmax)QFNpackage
Leadtemperature,soldering(1)
PowerdissipationθJAthermalimpedanceVaporphase(60sec)Infrared(15sec)
–0.3Vto+VA+0.3V–0.3Vto+VA+0.3V
–0.3Vto6V–0.3Vto6V–0.3Vto+VBD+0.3V
+0.3V–40°Cto85°C–65°Cto150°C
150°C(TJmax–TA)/θJA
86°C/W215°C220°C
Stressesbeyondthoselistedunder\"absolutemaximumratings\"maycausepermanentdamagetothedevice.Thesearestressratingsonly,andfunctionaloperationofthedeviceattheseoranyotherconditionsbeyondthoseindicatedunder\"recommendedoperatingconditions\"isnotimplied.Exposuretoabsolute-maximum-ratedconditionsforextendedperiodsmayaffectdevicereliability.
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SPECIFICATIONS
At–40°Cto85°C,+VA=+5V,+VBD=+5Vor+VBD=+2.7V,usinginternalorexternalreference,fSAMPLE=600kHz,
unlessotherwisenoted.(Allperformanceparametersarevalidonlyafterdevicehasproperlyresumedfrompowerdown,seeTable2.)PARAMETER
ANALOGINPUT
Full-scale
inputvoltage(1)
AbsoluteinputvoltageSamplingcapacitance(measuredfrom±INtoAGND)
Inputleakagecurrent
SYSTEMPERFORMANCE
ResolutionNomissingcodes
INLDNLEOEG
Integrallinearity(2)(3)(4)Differentiallinearity(3)Offseterror
(3)
TESTCONDITIONS
ADS8370IBMIN
TYP
MAX
MIN
ADS8370I
TYP
MAX
UNIT
+IN–(–IN)+IN–IN
0–0.2–0.2
40116
16
Vref
Vref+0.2
0.2
0–0.2–0.2
40116
16
Vref
Vref+0.2
0.2
VV
pFnABitsBits21.51.5
LSB(16bit)LSB(16bit)mVppm/°C
0.15
%FSppm/°C
QuietzonesobservedQuietzonesnotobservedQuietzonesobservedQuietzonesnotobserved
–1.25–0.75–0.75–0.075
±0.5±0.8±0.4±0.75±0.4±0.4
1.250.750.750.075
–2–1–1.5
±0.4
–0.15
±1.2580554055
Offsettemperaturedrift(3)Gainerror(3)(5)Gaintemperature
drift(3)(5)
AtDC
CMRR
Common-moderejectionratio
[+IN–(–IN)]=Vref/2with50mVp-pcommonmodesignalat1MHzAt0VanaloginputAtfullscaleanaloginput
±1.2580554055
dB
Noise
PSRR
DCPowersupplyrejectionratio
ConversiontimeAcquisitiontimeThroughputrateAperturedelayAperturejitterStepresponseOvervoltagerecovery
µVRMSdB
SAMPLINGDYNAMICS
1.00.50
600
1012
(6)
1.161.00.50
1.16600
1012400400
µsµskHznspsRMSnsns
400400
(1)(2)(3)(4)(5)(6)
Idealinputspan;doesnotincludegainoroffseterror.LSBmeansleastsignificantbit.
MeasuredusinganaloginputcircuitinFigure51anddigitalstimulusinFigure56andFigure57andreferencevoltageof4.096V.ThisisendpointINL,notbestfit.
Measuredusingexternalreferencesourcesodoesnotincludeinternalreferencevoltageerrorordrift.
DefinedassamplingtimenecessarytosettleaninitialerrorofVrefonthesamplingcapacitortoafinalerrorof1LSBat16-bitlevel.MeasuredusingtheinputcircuitinFigure51.3
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SPECIFICATIONS(continued)
At–40°Cto85°C,+VA=+5V,+VBD=+5Vor+VBD=+2.7V,usinginternalorexternalreference,fSAMPLE=600kHz,
unlessotherwisenoted.(Allperformanceparametersarevalidonlyafterdevicehasproperlyresumedfrompowerdown,seeTable2.)PARAMETER
DYNAMICCHARACTERISTICSTHD
Totalharmonicdistortion(7)(8)
VIN=4Vp-pat1kHzVIN=4Vp-pat10kHzVIN=4Vp-pat100kHzVIN=4Vp-pat1kHz
SNR
Signal-to-noise
ratio(7)
VIN=4Vp-pat10kHzVIN=4Vp-pat100kHz
SINAD
Signal-to-noise+distortion(7)(8)
VIN=4Vp-pat1kHzVIN=4Vp-pat10kHzVIN=4Vp-pat100kHz
SFDR
Spuriousfreedynamicrange(7)
–3dBSmallsignalbandwidth
REFERENCEINPUTVref
ReferencevoltageinputrangeResistance(9)
INTERNALREFERENCEOUTPUTVref
ReferencevoltagerangeSourcecurrentLineregulationDrift
DIGITALINPUT/OUTPUT
LogicfamilyCMOS
VIHVILVOHVOL
HighlevelinputvoltageLowlevelinputvoltageHighleveloutputvoltageLowleveloutputvoltage
IOH=2TTLloadsIOL=2TTLloads
+VBD–1
–0.3+VBD–0.6
0.4
+VBD+0.3
0.8
+VBD–1
–0.3+VBD–0.6
0.4
+VBD+0.3
0.8
VVVV
IOUT=0A,TA=30°CStaticload
+VA=4.75Vto5.25VIOUT=0A
2.525
4.088
4.096
4.10410
2.525
4.088
4.096
4.10410
VµAmVppm/°C
2.5
4.09610
4.2
2.5
4.09610
4.2
VMΩ
VIN=4Vp-pat1kHzVIN=4Vp-pat10kHzVIN=4Vp-pat100kHz
–112–111–9289.589.589.589.589.587.51191179275
–111–111–9289.58988.589.589871191179275
MHzdBdBdBdB
TESTCONDITIONS
ADS8370IBMIN
TYP
MAX
MIN
ADS8370I
TYP
MAX
UNIT
Dataformat:MSBfirst,2'scomplementorstraightbinary(selectableviatheSB/2Cpin)
POWERSUPPLYREQUIREMENTS
Powersupplyvoltage
ICC
+VA+VBD
+VA=5V
4.752.7
53.322
5.255.2525
4.752.7
53.322
5.255.2525
VVmA
Supplycurrent,600-kHzsamplerate(10)
Supplycurrent,powerdownSupplycurrent,napmodePower-uptimefromnap
POWERDOWNICC(PD)ICC(NAP)
23
300
–40
85
–40
23
30085
µAmAns°C
NAPMODE
TEMPERATURERANGE
Specifiedperformance
(7)(8)(9)(10)
MeasuredusinganaloginputcircuitinFigure51anddigitalstimulusinFigure56andFigure57andreferencevoltageof4.096V.Calculatedonthefirstnineharmonicsoftheinputfrequency.Canvary+/-30%.
Thisincludesonly+VAcurrent.With+VBD=5V,+VBDcurrentistypically1mAwitha10-pFloadcapacitanceonthedigitaloutputpins.
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TIMINGREQUIREMENTS(1)(2)(3)(4)(5)(6)
PARAMETER
tconvtacq1tacq2
Conversiontime
Acquisitiontimeinnormalmode
Acquisitiontimeinnapmode(tacq2=tacq1+td18)
Quitesamplingtime(lasttoggleofinterfacesignalstoconvertstartcommand)(6)
Quitesamplingtime(convertstartcommandtofirsttoggleofinterfacesignals)(6)
Quiteconversiontime(lasttoggleofinterfacesignalstofallofBUSY)(6)Setuptime,CONVSTbeforeBUSYfall
Setuptime,CSbeforeBUSYfall(onlyforconversion/samplingcontrol)Setuptime,CONVSTbeforeCSrise(soCONVSTcanberecognized)Holdtime,CSafterBUSYfall(onlyforconversion/samplingcontrol)Holdtime,CONVSTafterCSrise
Holdtime,CONVSTafterCSfall(toensurewidthofCONVST_QUAL)(4)CONVSTpulsedurationCSpulseduration
Pulseduration,timebetweenconversionstartcommandandconversionabortcommandtosuccessfullyaborttheongoingconversionSCLKperiodSCLKdutycycle
tsu5tsu6tsu7th5th6tsu2tsu3th2th8tw2tw3tw4(1)(2)(3)(4)(5)(6)
Setuptime,CSfallbeforefirstSCLKfallSetuptime,CSfallbeforeFSriseSetuptime,FSfallbeforefirstSCLKfallHoldtime,CSfallafterSCLKfallHoldtime,FSfallafterSCLKfall
Setuptime,CSfallbeforeBUSYfall(onlyforreadcontrol)Setuptime,FSfallbeforeBUSYfall(onlyforreadcontrol)Holdtime,CSfallafterBUSYfall(onlyforreadcontrol)Holdtime,FSfallafterBUSYfall(onlyforreadcontrol)CSpulsedurationFSpulseduration
PDpulsedurationforresetandpowerdownAllunspecifiedpulsedurations
2540%1077372020151510106010
60%
nsnsnsnsnsnsnsnsnsnsnsnsns
4546,4746,474546,4740,4540,4740,4540,474546,4753,54
ADS8370I/ADS8370IBMIN10000.50.8
TYP
MAX1160
UNITnsµsµs
REFFIGURE41–4441,42,444340–43,45–4740–43,45–4740–43,45,474140,4141,43,444143424341,4244
CONVERSIONANDSAMPLINGtquiet1tquiet2tquiet3tsu1tsu2tsu4th1th3th4tw1tw2tw5
30106001520507202010
1000
nsnsnsnsnsnsnsnsnsnsnsns
DATAREADOPERATIONtcyc
ns
45–47
MISCELLANEOUS
Allinputsignalsarespecifiedwithtr=tf=5ns(10%to90%ofVDD)andtimedfromavoltagelevelof(VIL+VIH)/2.Allspecificationstypicalat–40°Cto85°C,+VA=+4.75Vto+5.25V,+VBD=+2.7Vto+5.25V.Alldigitaloutputsignalsloadedwith10-pFcapacitors.
CONVST_QUALisCONVSTlatchedbyalowvalueonCS(seeFigure39).Referencefigureindicatedisonlyarepresentativeofwherethetimingisapplicableandisnotexhaustive.Quiettimezonesareformeetingperformanceandnotfunctionality.
5
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TIMINGCHARACTERISTICS(1)(2)(3)(4)
PARAMETER
CONVERSIONANDSAMPLINGtd1td2td4td3td5td6
Delaytime,conversionstartcommandtoconversionstart(aperturedelay)Delaytime,conversionendtoBUSYfall
Delaytime,conversionstartcommandtoBUSYriseDelaytime,CONVSTrisetosamplestartDelaytime,CSfalltosamplestart
Delaytime,conversionabortcommandtoBUSYfall
362
105205101015181810655300
td11+2xconversions
25(4)
1
20010
4
msmsnsµsmsnsnsnsnsnsnsnsnsnsnsnsnsns
41,4341–43414343444546,474745–474553,5455545353,545553,5453
ADS8370I/ADS8370IBMIN
TYP
MAX
UNIT
REFFIGURE
DATAREADOPERATION
td12Delaytime,CSfalltoMSBvalidtd15Delaytime,FSrisetoMSBvalidtd7
Delaytime,BUSYfalltoMSBvalid(ifFSishighwhenBUSYfalls)td13Delaytime,SCLKrisetobitvalidtd14Delaytime,CSrisetoSDO3-stateMISCELLANEOUS
td10Delaytime,PDrisetoSDO3-state
Napmode
Delaytime,totaltd18deviceresume
time
Fullpowerdown(externalreferenceusedwithorwithout1-µF||0.1-µFcapacitoronREFOUT)
Fullpowerdown(internalreferenceusedwithorwithout1-µF||0.1-µFcapacitoronREFOUT)Nap
Fullpowerdown(internal/externalreferenceused)
td11Delaytime,untrimmedcircuitfullpower-downresumetimeDelaytime,devicetd16power-downtimetd17
Delaytime,trimmedinternalreferencesettling(eitherbyturningonsupplyorresumingfromfullpower-downmode),with1-µF||0.1-µFcapacitoronREFOUT
(1)(2)(3)(4)
Allinputsignalsarespecifiedwithtr=tf=5ns(10%to90%ofVDD)andtimedfromavoltagelevelof(VIL+VIH)/2.Allspecificationstypicalat–40°Cto85°C,+VA=+4.75Vto+5.25V,+VBD=+2.7Vto+5.25V.Alldigitaloutputsignalsloadedwith10-pFcapacitors.
Includingtd11,twoconversions(timetocycleCONVSTtwice),andtd17.
6
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PINASSIGNMENTS
TOPVIEW
282726252423SDO22BUSYBDGND+VBDAGND1234567CONVSTSCLKPDFSCSSB/2CAGND+VAAGNDAGND+VAREFMREFOUTREFIN21201918171615ADS8370AGND+VA+VAAGND+IN1213Note:Thepackagethermalpadmustbesolderedtotheprintedcircuitboardforthermalandmechanicalperformance.
TERMINALFUNCTIONS
PINNAMEAGNDBDGNDBUSYCONVSTCSFS+IN–INNCPDREFINREFMREFOUTSB/2CSCLKSDO+VA+VBDNO.2,4,5,15,18,192122252627111210,1328879124233,6,14,16,1720I/O––OIIIII–IIIOIIO––DESCRIPTIONAnaloggroundpins.AGNDmustbeshortedtoanaloggroundplanebelowthedevice.Digitalgroundforalldigitalinputsandoutputs.BDGNDmustbeshortedtotheanaloggroundplanebelowthedevice.Statusoutput.Thispinishighwhenconversionisinprogress.Convertstart.ThissignalisqualifiedwithCSinternally.ChipselectFramesync.ThissignalisqualifiedwithCSinternally.NoninvertinganaloginputchannelInvertinganaloginputchannelNoconnectionPowerdown.Deviceresetsandpowersdownwhenthissignalishigh.Reference(positive)input.REFINmustbedecoupledwithREFMpinusing0.1-µFbypasscapacitorand1-µFstoragecapacitor.Referenceground.Tobeconnectedtoanaloggroundplane.Internalreferenceoutput.ShortedtoREFINpinonlywheninternalreferenceisused.Straightbinaryor2'scomplementoutputdataformat.Whenlowthedeviceoutputisstraightbinaryformat;whenhighthedeviceoutputis2'scomplementformat.SeeTable1.Serialclock.DataisshiftedontoSDOwiththerisingedgeofthisclock.ThissignalisqualifiedwithCSinternally.Serialdataout.AllbitsexceptMSBareshiftedoutattherisingedgeofSCLK.AnalogpowersuppliesDigitalpowersupplyforalldigitalinputsandoutputs.10111489+VANCNC−IN7
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TYPICALCHARACTERISTICS
SIGNAL-TO-NOISERATIO
vs
REFERENCEVOLTAGE
SINAD − Signal-to-Noise and Distortion − dB91SNR − Signal-to-Noise Ratio − dB9089888786852.5+VA = 5 V,+VBD = 5 V,fi = 1 kHz,TA = 25°C919089888786852.5
3
3.5
4
Vref − Reference Voltage − V
SIGNAL-TO-NOISEANDDISTORTION
vs
REFERENCEVOLTAGE
+VA = 5 V,+VBD = 5 V,fi = 1 kHz,TA = 25°C33.54Vref − Reference Voltage − V
Figure1.
SPURIOUSFREEDYNAMICRANGE
vs
REFERENCEVOLTAGE
SFDR − Spurious Free Dynamic Range − dB1201191181171161151141131121112.533.54THD − Total Harmonic Distortion − dB+VA = 5 V,+VBD = 5 V,fi = 1 kHz,TA = 25°CFigure2.
TOTALHARMONICDISTORTION
vs
REFERENCEVOLTAGE
−106−107−108−109−110−111−112+VA = 5 V,+VBD = 5 V,fi = 1 kHz,TA = 25°C2.533.54Vref − Reference Voltage − VVref − Reference Voltage − V
Figure3.
EFFECTIVENUMBEROFBITS
vs
REFERENCEVOLTAGE
14.6ENOB − Effective Number of Bits − Bits14.514.414.314.214.11413.9
2.5
33.5
Vref − Reference Voltage − V
4
ENOB − Effective Number of Bits − Bits+VA = 5 V,+VBD = 5 V,fi = 1 kHz,TA = 25°C14.7
Figure4.
EFFECTIVENUMBEROFBITS
vs
FREE-AIRTEMPERATURE
14.6
14.5
14.4
+VA = 5 V,+VBD = 5 V,REFIN = 4.096 V,fi = 1 kHz,14.3
14.2
−40−25−105
20
35
50
65
80
TA − Free-Air-Temperature − 5C
Figure5.Figure6.
8
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TYPICALCHARACTERISTICS(continued)
SIGNAL-TO-NOISERATIO
vs
FREE-AIRTEMPERATURE
SINAD − Signal-to-Noise and Distortion − dB90SNR − Signal-to-Noise Ratio − dB89.58988.58887.587−40−25−10520355065
TA − Free-Air-Temperature − 5C
80
9089.58988.58887.5
SIGNAL-TO-NOISEANDDISTORTION
vs
FREE-AIRTEMPERATURE
+VA = 5 V,+VBD = 5 V,REFIN = 4.096 V,fi = 1 kHz,+VA = 5 V,+VBD = 5 V,REFIN = 4.096 V,fi = 1 kHz,5
20
35
50
65
80
87
−40−25−10
TA − Free-Air-Temperature − 5C
Figure7.
SPURIOUSFREEDYNAMICRANGE
vs
FREE-AIRTEMPERATURE
SFDR − Spurious Free Dynamic Range − dB120119118117116115114113112111−40−25−10
5
20
35
50
65
80
TA − Free-Air-Temperature − 5C
+VA = 5 V,+VBD = 5 V,REFIN = 4.096 V,fi = 1 kHz,THD − Total Harmonic Distortion − dBFigure8.
TOTALHARMONICDISTORTION
vs
FREE-AIRTEMPERATURE
−100−102−104−106−108−110
−112
−40−25−10+VA = 5 V,+VBD = 5 V,REFIN = 4.096 V,fi = 1 kHz,52035506580TA − Free-Air-Temperature − 5C
Figure9.
EFFECTIVENUMBEROFBITS
vs
INPUTFREQUENCY
SINAD − Signal-to-Noise and Distortion − dB14.6ENOB − Effective Number of Bits − Bits89.689.489.28988.888.688.4
1
Figure10.SIGNAL-TO-NOISEANDDISTORTION
vs
INPUTFREQUENCY
14.55
14.5
14.45
+VA = 5 V,+VBD = 5 V,REFIN = 4.096 V,TA = 25°C+VA = 5 V,+VBD = 5 V,REFIN = 4.096 V,TA = 25°C10
fi − Input Frequency − kHz
100
14.4
110fi − Input Frequency − kHz
100Figure11.Figure12.
9
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TYPICALCHARACTERISTICS(continued)
SIGNAL-TO-NOISERATIO
vs
INPUTFREQUENCY
SFDR − Spurious Free Dynamic Range − dB89.6SNR − Signal-to-Noise Ratio − dB89.489.28988.888.688.4
1
10
fi − Input Frequency − kHz
100
+VA = 5 V,+VBD = 5 V,REFIN = 4.096 V,TA = 25°CSPURIOUSFREEDYNAMICRANGE
vs
INPUTFREQUENCY
1401201008060402001
10
fi − Input Frequency − kHz
100
+VA = 5 V,+VBD = 5 V,REFIN = 4.096 V,TA = 25°CFigure13.
TOTALHARMONICDISTORTION
vs
INPUTFREQUENCY
0THD − Total Harmonic Distortion − dB−20+VA = 5 V,+VBD = 5 V,REFIN = 4.096 V,TA = 25°CFigure14.
−40−60−80−100−1201
10fi − Input Frequency − kHz
100Figure15.
HISTOGRAM
65536CONVERSIONS
WITHADCINPUTATZEROSCALE(0V)
40000350003000025000HitsHits200001500010000
10000
5000
6542065421654226542365424654256542665427654286542965430495051525354555657585960Code Out
(Straight Binary Code in Decimal)
654310
03000020000
+VA = 5 V,+VBD = 5 V,REFIN = 4.096 V,TA = 25°CHISTOGRAM
100000CONVERSIONS
WITHADCINPUTCLOSETOFULLSCALE(4V)
600005000040000
+VA = 5 V,+VBD = 5 V,REFIN = 4.096 V,TA = 25°CCode Out
(Straight Binary Code in Decimal)
Figure16.Figure17.
10
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TYPICALCHARACTERISTICS(continued)
GAINERROR
vs
REFERENCEVOLTAGE
10.80.6EG− Gain Error − mV0.40.20−0.2−0.4−0.6−0.8−12.5
33.5
Vref − Reference Voltage − V
4
−64.755+VA − Analog Supply Voltage − V
5.25+VA = 5 V,+VBD = 5 V,TA = 25°CEG− Gain Error − mV6420−2−4
GAINERROR
vs
ANALOGSUPPLYVOLTAGE
+VBD = 5 V,REFIN = 4.096 V,TA = 25°CFigure18.
GAINERROR
vs
FREE-AIRTEMPERATURE
2
+VA = 5 V,+VBD = 5 V,REFIN = 4.096 VEO− Offset Error − mVEG− Gain Error − mV1
10.750.50.250
+VA = 5 V,+VBD = 5 V,TA = 25°CFigure19.
OFFSETERROR
vs
REFERENCEVOLTAGE
0
−0.25−0.5
−1
−0.75
−2
−1
−40−25−10
5
20
35
50
65
80
2.533.54TA − Free-Air-Temperature − 5C
Vref − Reference Voltage − V
Figure20.
OFFSETERROR
vs
FREE-AIRTEMPERATURE
10.75EO− Offset Error − mV0.50.250+VA = 5 V,+VBD = 5 V,REFIN = 4.096 VEO− Offset Error − mV0.20.10−0.1−0.2−0.3−0.4−0.5−0.6
520355065804.75
Figure21.OFFSETERROR
vs
SUPPLYVOLTAGE
+VBD = 5 V,REFIN = 4.096 V,TA = 25°C−0.25−0.5−0.75−1−40−25−10TA − Free-Air-Temperature − 5C
5
+VA − Analog Supply Voltage − V
5.25
Figure22.Figure23.
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TYPICALCHARACTERISTICS(continued)
POWERDISSIPATION
vs
SUPPLYVOLTAGE
116
PD− Power Dissipation − mW114PD− Power Dissipation − mW112110108106104102100
4.75
5
+VA − Analog Supply Voltage − V
5.25
+VBD = 5 V,fs = 600 KSPSTA = 25°C1401201008060NAP Mode Current402000100200300400500600fs − Sample Rate − KSPS
+VA = 5 .25 V,+VBD = 5.25 V,TA = 25°CNormal Mode CurrentPOWERDISSIPATION
vs
SAMPLERATE
Figure24.
POWERDISSIPATION
vs
FREE-AIRTEMPERATURE
120
DNL − Diffreential Nonlinearity − LSB+VA = 5 V,+VBD = 5 V,fs = 600 KSPS115
10.80.60.40.20−0.2−0.4−0.6−0.8−12.5
Figure25.
DIFFERENTIALNONLINEARITY
vs
REFERENCEVOLTAGE
PD− Power Dissipation − mWMAX110
MIN105
+VA = 5 V,+VBD = 5 V,TA = 25°C33.5
Vref − Reference Voltage − V
4
100
−40−25−105
20
35
50
65
80
TA − Free-Air Temperature − °C
Figure26.
INTEGRALNONLINEARITY
vs
REFERENCEVOLTAGE
1
INL − Integral Nonlinearity − LSB0.80.60.40.20−0.2−0.4−0.6−0.8−12.533.54Vref − Reference Voltage − V
MIN+VA = 5 V,+VBD = 5 V,TA = 25°CDNL − Diffreential Nonlinearity − LSBMAX10.80.60.40.20−0.2−0.4−0.6−0.8
Figure27.
DIFFERENTIALNONLINEARITY
vs
FREE-AIRTEMPERATURE
MAXMIN+VA = 5 V,+VBD = 5 V,REFIN = 4.096 V20
35
50
65
80
−1
−40−25−105
TA − Free-Air-Temperature − 5C
Figure28.Figure29.
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TYPICALCHARACTERISTICS(continued)
INTEGRALNONLINEARITY
vs
FREE-AIRTEMPERATURE
1
Internal Reference Output Voltage − VINL − Integral Nonlinearity − LSB0.80.60.40.20−0.2−0.4−0.6−0.8
−1
−40−25−1052035506580MIN+VA = 5 V,+VBD = 5 V,REFIN = 4.096 VMAXINTERNALVOLTAGEREFERENCE
vs
FREE-AIRTEMPERATURE
4.1264.1164.106
+VA = 5 V,+VBD = 5 V,4.0964.0864.0764.066
−40−25−105
20
35
50
65
80
TA − Free-Air Temperature − °C
TA − Free-Air-Temperature − 5C
Figure30.
INTERNALVOLTAGEREFERENCE
vs
SUPPLYVOLTAGE
4.126Internal Reference Output Voltage − V4.1164.1064.0964.0864.0764.066
4.75
5
+VA − Analog Supply Voltage − V
5.25
SCLK to SDO Delay Time (td13) − ns+VBD = 5 V,TA = 25°C9.598.587.576.565.554.55
Figure31.
DELAYTIME
vs
LOADCAPACITANCE
+VA = 5 V,TA = 85°C+VBD = 2.7 V+VBD = 5 V101520CL − Load Capacitance − pF
Figure32.
DIFFERENTIALNONLINEARITY10.80.6DNL − LSBs0.40.20−0.2−0.4−0.6−0.8−10
+VA = 5 V, +VBD = 5 V,REFIN = 4.096 V,fS = 600 KSPS,TA = 25°C1638432768Code
(Straight Binary Code in Decimal)
49152Figure33.
65536Figure34.
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TYPICALCHARACTERISTICS(continued)
10.80.6INL − LSB0.40.20−0.2−0.4−0.6−0.8−10
+VA = 5 V, +VBD = 5 V,REFIN = 4.096 V,fS = 600 KSPS,TA = 25°C16384
32768Code
(Straight Binary Code in Decimal)
49152
65536
INTEGRALNONLINEARITY
Figure35.
FFT(100kHzInput)+VA = 5 V, +VBD = 5 V,REFIN = 4.096 V,fS = 600 KSPS,TA = 25°C0−20−40Amplitude − dB−60−80−100−120−140−160−180−2000
50000
100000
150000
f − Frequency − Hz
200000250000300000
Figure36.
FFT(10kHzInput)
200−20−40Amplitude − dB−60−80−100−120−140−160−180−2000
50000
100000
150000f − Frequency − Hz
200000
250000
300000
+VA = 5 V, +VBD = 5 V,REFIN = 4.096 V,fS = 600 KSPS,TA = 25°CFigure37.
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PowerOnBUSY=0+VA and +VBD Reach Operation Rangeand PD = 0SampleBUSY=0CS = 0 and CONVST = 1Falling Edge of CONVST_QUALCS = 0 and CONVST = 1SOCBUSY=0 −> 1CS = 0 and CONVST = 1Back to Back CycleCONVERSIONFalling Edge ofCONVST_QUALand BUSY = 1AbortEOCCONVST_QUAL = 0BUSY= 1−>0CONVST_QUAL = 1and CS = 1NAPBUSY=0WaitBUSY=0A.
EOC=Endofconversion,SOC=Startofconversion,CONVST_QUALisCONVSTlatchedbyCS=0,seeFigure39.Figure38.DeviceStatesandIdealTransitions
CONVSTDLATCHQCONVST_QUALCSLATCHFigure39.RelationshipBetweenCONVST_QUAL,CS,andCONVSTTIMINGDIAGRAMS
Inthefollowingdescriptions,thesignalCONVST_QUALrepresentsCONVSTlatchedbyalowvalueonCS(seeFigure39).Toavoidperformancedegradation,therearethreequietzonestobeobserved(tquiet1andtquiet2arezonesbeforeandafterthefallingedgeofCONVST_QUALwhiletquiet3isatimezonebeforethefallingedgeofBUSY)wherethereshouldbenoI/Oactivities.Interfacecontrolsignals,includingtheserialclockshouldremainsteady.Typicaldegradationinperformanceifthesequietzonesarenotobservedisdepictedinthespecificationssection.ToavoiddatalossareadoperationshouldnotstartaroundtheBUSYfallingedge.Thisisconstrainedbytsu2,tsu3,th2,andth8.
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CONVST_QUALtquiet1BUSYtquiet3Quiet Zones
CSFSCStsu2th2BUSYNo Read Zone (CS Initiated)BUSYNo Read Zone (FS Initiated)
tsu3th8tquiet2Figure40.QuietZonesandNo-ReadZones
CONVERSIONANDSAMPLING1.Convertstartcommand:
ThedeviceenterstheconversionphasefromthesamplingphasewhenafallingedgeisdetectedonCONVST_QUAL.ThisisshowninFigure41,Figure42,andFigure43.2.Sample(acquisition)startcommand:
ThedevicestartssamplingfromthewaitstateorattheendofaconversionifCONVST_QUALisdetectedashighandCSaslow.ThisisshowninFigure41,Figure42,andFigure43.Maintainingthisconditionwhenthedevicehasjustfinishedaconversion(asshowninFigure41)takesthedeviceimmediatelyintothesamplingphaseaftertheconversionphase(back-to-backconversion)andhenceachievesmaximumthroughput.Otherwise,thedeviceentersthewaitstate.
tw2CStsu4CONVSTCONVST_QUAL(Device Internal)tquiet1SAMPLEDEVICE STATEtd4BUSYtquiet3CONVERTtCONVtd2td1tquiet2tquiet1SAMPLEtacq1tsu1tquiet2tsu2th1Figure41.Back-To-BackConversionandSample
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3.Wait/Napentrystimulus:
Thedeviceentersthewaitphaseattheendoftheconversionifthesamplestartcommandisnotgiven.ThisisshowninFigure42.CStsu4tw2th4CONVSTCONVST_QUAL(Device Internal)tquiet2tquiet1DEVICE STATESAMPLECONVERTtCONVtd2BUSYtquiet3WAITSAMPLEtacq1tquiet1tquiet2Figure42.ConvertandSamplewithWait
Iflowerpowerdissipationisdesiredandthroughputcanbecompromised,anapstatecanbeinsertedinbetweencycles(asshowninFigure43).Thedeviceentersalowpower(3mA)statecallednapiftheendoftheconversionhappenswhenCONVST_QUALislow.Thecostforusingthisspecialwaitstateisalongersamplingtime(tacq2)plusthenaptime.
CSth3td5CONVSTtw1CONVST_QUAL(Device Internal)tquiet1td1tquiet2td3tquiet2tquiet1DEVICE STATENAPSAMPLEtCONVtd2BUSYtquiet3td4CONVERTNAPSAMPLEtacq2tquiet3CONVERTNAPSAMPLEFigure43.ConvertandSamplewithNap
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4.Conversionabortcommand
Anongoingconversioncanbeabortedbyusingtheconversionabortcommand.Thisisdonebyforcinganotherstartofconversion(avalidCONVST_QUALfallingedge)ontoanongoingconversionasshowninFigure44.Thedeviceentersthewaitstateafteranabortedconversion.Ifthepreviousconversionwassuccessfullyaborted,thedeviceoutputreads0xFF00onSDO.
tw5CStw5CONVSTtsu4CONVST_QUAL(Device Internal)DEVICE STATESAMPLECONVERTIncompleteConversionWAITSAMPLEtacq1CONVERTIncompleteConversionWAITtCONVBUSYtd6tCONVtd6Figure44.ConversionAbort
DATAREADOPERATION
Datareadcontrolisindependentofconversioncontrol.Datacanbereadeitherduringconversionorduringsampling.Datathatisreadduringaconversioninvolveslatencyofonesample.ThestartofanewdataframearoundthefallofBUSYisconstrainedbytsu2,tsu3,th2,andth8.1.SPIInterface:
AdatareadoperationinSPIinterfacemodeisshowninFigure45.FSmustbetiedhighforoperatinginthismode.TheMSBoftheoutputdataisavailableatthefallingedgeofCS.MSB–1isshiftedoutatthefirstrisingedgeafterthefirstfallingedgeofSCLKafterCSfallingedge.SubsequentbitsareshiftedatthesubsequentrisingedgesofSCLK.Ifanotherdataframeisattempted(bypullingCShighandsubsequentlylow)duringanactivedataframe,thentheongoingframeisabortedandanewframeisstarted.
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SCLK12tsu53416 17 18 19tcyctd14th5CStw2CONVSTSDOtquiet2tquiet1MSBD15tquiet3td12td13D14D13D12D1D0D0LSBD0D15 RepeatedIf There is 19th SCLKDon’t Care(D0 Repeated)Conversion N+1BUSYConversion Ntsu2CS Fall Before ThisPoint Reads DataFrom ConversionN−1No CSFallZoneth2CS Fall After ThisPoint Reads DataFrom ConversionNFigure45.ReadFrameControlledviaCS(FS=1)
Ifanotherdataframeisattempted(bypullingCShighandthenlow)duringanactivedataframe,thentheongoingframeisabortedandanewframeisstarted.2.SerialinterfaceusingFS:
AdatareadoperationinthismodeisshowninFigure46andFigure47.TheMSBoftheoutputdataisavailableattherisingedgeofFS.MSB–1isshiftedoutatthefirstrisingedgeafterthefirstfallingedgeofSCLKaftertheFSfallingedge.SubsequentbitsareshiftedatthesubsequentrisingedgesofSCLK.
SCLK 1 2 3 4 16 17 18 19th6CStsu6FStw3tcyctsu7CONVSTtd15SDOtd13MSB of Conversion Ntquiet1D14D13D12D1D0D0LSBD0tquiet2D15D15 RepeatedIf There is 19th SCLKBUSYConversion NDon’t Care(D0 Repeated)Conversion N+1Figure46.ReadFrameControlledviaFS(FSisLowWhenBUSYFalls)
IfFSishighwhenBUSYfalls,theSDOisupdatedagainwiththenewMSBwhenBUSYfalls.ThisisshowninFigure47.19
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1 16 17 18 19www.ti.com
SCLK234th6CStsu6FStw3tcyctsu7CONVSTtd15SDOMSB of Conversion N−1MSB of Conversion Ntquiet1D12D1D0D0LSBD0tquiet2td13D15D14D13D15 Repeatedtd7BUSYtquiet3Conversion NIf There is 19th SCLKDon’t Care(D0 Repeated)Conversion N+1tsu3FS Fall Before ThisPoint Reads DataFrom ConversionN−1No FSFallZoneth8FS Fall After ThisPoint Reads DataFrom ConversionNFigure47.ReadFrameControlledviaFS(FSisHighWhenBUSYFalls)
IfanotherdataframeisattemptedbypullingupFSduringanactivedataframe,thentheongoingframeisabortedandanewframeisstarted.
PRINCIPLESOFOPERATION
TheADS8370isahigh-speedsuccessiveapproximationregister(SAR)analog-to-digitalconverter(ADC).Thearchitectureisbasedonchargeredistribution,whichinherentlyincludesasample/holdfunction.
Thedeviceincludesabuilt-inconversionclock,internalreference,and40-MHzSPIcompatibleserialinterface.Themaximumconversiontimeis1.16µswhichiscapableofsustaininga600-kHzthroughput.
Theanaloginputisprovidedtothetwoinputpins:+INand–IN.Whenaconversionisinitiated,thedifferentialinputonthesepinsissampledontheinternalcapacitorarray.Whileaconversionisinprogress,bothinputsaredisconnectedfromanyinternalfunction.
REFERENCE
TheADS8370hasabuilt-in4.096-V(nominalvalue)referencebutcanoperatewithanexternalreferencealso.Whentheinternalreferenceisused,pin9(REFOUT)shouldbeshortedtopin8(REFIN)anda0.1-µFdecouplingcapacitoranda1-µFstoragecapacitormustbeconnectedbetweenpin8(REFIN)andpin7(REFM)(seeFigure48).Theinternalreferenceoftheconverterisbuffered.
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PRINCIPLESOFOPERATION(continued)
ADS8370REFOUT1 mF0.1 mFREFMAGNDREFINFigure48.ADS8370UsingInternalReference
TheREFINpinisalsointernallybuffered.ThiseliminatestheneedtoputahighbandwidthbufferontheboardtodrivetheADCreferenceandsavessystemareaandpower.Whenanexternalreferenceisused,thereferencemustbeoflownoise,whichmaybeachievedbytheadditionofbypasscapacitorsfromtheREFINpintotheREFMpin.SeeFigure49foroperationoftheADS8370withanexternalreference.REFMmustbeconnectedtotheanaloggroundplane.ADS8370REFOUT50 WREF324022 mFAGND0.1 mF1 mFAGNDREFMREFINFigure49.ADS8370UsingExternalReference
+VAADS8370+IN−IN53 W+_40 pF53 W40 pFAGNDAGNDFigure50.SimplifiedAnalogInput
ANALOGINPUT
Whentheconverterentersholdmode,thevoltagedifferencebetweenthe+INand–INinputsiscapturedontheinternalcapacitorarray.The+INinputhasarangeof–0.2Vto(+VREF+0.2V),whereasthe–INinputhasarangeof–0.2Vto+0.2V.Theinputspan[+IN–(–IN)]islimitedfrom0VtoVREF.
Theinputcurrentontheanaloginputsdependsuponthroughputandthefrequencycontentoftheanaloginput
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PRINCIPLESOFOPERATION(continued)
signals.Essentially,thecurrentintotheADS8370chargestheinternalcapacitorarrayduringthesampling(acquisition)time.Afterthiscapacitancehasbeenfullycharged,thereisnofurtherinputcurrent.Thesourceoftheanaloginputvoltagemustbeabletochargethedevicesamplingcapacitance(40pFeachfrom+IN/–INtoAGND)toan16-bitsettlinglevelwithinthesampling(acquisition)timeofthedevice.Whentheconvertergoesintoholdmode,theinputresistanceisgreaterthan1GΩ.
Caremustbetakenregardingtheabsoluteanaloginputvoltage.Tomaintainthelinearityoftheconverter,the+IN,–INinputsandthespan[+IN–(–IN)]shouldbewithinthelimitsspecified.Outsideoftheseranges,theconverter'slinearitymaynotmeetspecifications.
Careshouldbetakentoensurethattheoutputimpedanceofthesourcesdriving+INand–INinputsarematched.Ifthisisnotobserved,thetwoinputscanhavedifferentsettlingtimes.Thiscanresultinoffseterror,gainerror,andlinearityerrorwhichvarywithtemperatureandinputvoltage.
AtypicalinputcircuitusingTI'sTHS4031isshowninFigure52.Inthefigure,inputfromabipolarsourceisconvertedtoaunipolarsignalfortheADS8370.InthecasewherethesourcesignalisinrangefortheADS8370,thecircuitinFigure51maybeused.MostofthespecifiedperformancefigureweremeasuredusingthecircuitinFigure51.InputSignal(0 V to 4 V)THS403120 W1.5 nF50 W−IN20 W+INADS8370Figure51.UnipolarInputDriveConfiguration
ADS83701 V DCTHS403120 W1.5 nFInputSignal(−2V to 2 V)600 W−IN20 W+IN600 WFigure52.BipolarInputDriveConfiguration
DIGITALINTERFACE
TIMINGANDCONTROL
ConversionandsamplingarecontrolledbytheCONVSTandCSpins.Seethetimingdiagramsfordetailedinformationontimingsignalsandtheirrequirements.TheADS8370usesaninternallygeneratedclocktocontroltheconversionrateandinturnthethroughputoftheconverter.SCLKisusedforreadingconverteddataonly.Acleanandlowjitterconversionstartcommandisimportantfortheperformanceoftheconverter.Thereisaminimalquietzonerequirementaroundtheconversionstartcommandasmentionedinthetimingrequirementstable.
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DIGITALINTERFACE(continued)READINGDATA
TheADS8370offersahighspeedserialinterfacethatiscompatiblewiththeSPIprotocol.Thedeviceoutputsdataineither2'scomplementformatorstraightbinaryformatdependingonthestateoftheSB/2Cpin.RefertoTable1fortheidealoutputcodes.
Table1.InputVoltagesandIdealOutputCodes
DESCRIPTIONFull-scalerangeLeastsignificantbit(LSB)FullscaleMidscaleMidscale–1LSB0
ANALOGVALUE+IN–(–IN)(+VREF)(+VREF)/216VREF–1LSB(+VREF)/2(+VREF)/2–1LSB0
SB/2CPin=0
FFFF80007FFF0000
SB/2CPin=1
7FFF0000FFFF8000
DIGITALOUTPUT(HEXADECIMAL)
Toavoidperformancedegradationduetothetogglingofdevicebuffers,readoperationmustnotbeperformedinthespecifiedquietzones(tquiet1,tquiet2,andtquiet3).Internaltothedevice,thepreviouslyconverteddataisupdatedwiththenewdatanearthefallofBUSY.Hence,thefallofCSandthefallofFSaroundthefallofBUSYisconstrained.Thisisspecifiedbytsu2,tsu3,th2,andth8inthetimingrequirementstable.
POWERSAVING
Theconverterprovidestwopowersavingmodes,fullpowerdownandnap.RefertoTable2forinformationonactivation/deactivationandresumptiontimeforbothmodes.
Table2.PowerSave
TYPEOFPOWERDOWN
Normaloperation
Fullpowerdown
(IntRef,1-µFcapacitoronREFOUTpin)
SDONot3stated3Stated(td10timing)
POWERCONSUMPTION22mA2µA2µA3mA
ACTIVATEDBYNAPD=1PD=1
AtEOCand
CONVST_QUAL=0
ACTIVATIONTIME(td16)NA10µs10µs200ns
RESUMEPOWERBYNAPD=0PD=0
SampleStartcommand
Fullpowerdown3Stated(td10(ExtRef,1-µFcapacitoronREFOUTpin)timing)Nappowerdown
Not3stated
FULLPOWER-DOWNMODE
Fullpower-downmodeisactivatedbyturningoffthesupplyorbyassertingPDto1.SeeFigure53andFigure54.Thedevicecanberesumedfromfullpowerdownbyeitherturningonthepowersupplyorbyde-assertingthePDpin.Thefirsttwoconversionsproduceinaccurateresultsbecauseduringthisperiodthedeviceloadsitstrimvaluestoensurethespecifiedaccuracy.
Ifaninternalreferenceisused(witha1-µFcapacitorinstalledbetweentheREFOUTandREFMpins),thetotalresumetime(td18)is25ms.Afterthefirsttwoconversions,td17(4ms)isrequiredforthetrimmedinternalreferencevoltagetosettletothespecifiedaccuracy.Onlythentheconvertedresultsmatchthespecifiedaccuracy.
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PDtw4SDOtd10Invalid DataValid DataBUSYREFOUTtd16ICC PDtd111td1823td17Full ICCFull ICCICCFigure53.DeviceFullPowerDown/Resume(InternalRefernceUsed)
PDtw4SDOtd10Invalid DataValid Datatd11BUSYtd16ICCFull ICCICC PDtd18123tacq1Full ICCFigure54.DeviceFullPowerDown/Resume(ExternalReferenceUsed)
NAPMODE
NapmodeisautomaticallyinsertedattheendofaconversionifCONVST_QUALisheldlowatEOC.Thedevicecanbeoperatedinnapmodeattheendofeveryconversionforsavingpoweratlowerthroughputs.Anotherwaytousethismodeistoconvertmultipletimesandthenenternapmode.Theminimumsamplingtimeafteranapstateistacq1+td18=tacq2.
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PD = 0CONVSTCSCONVST_QUALDEVICESTATESAMPLELSBtCONVBUSYREFIN(or REFOUT)td16ICC
Full ICCICC NAPCONVERTNAPHi−ZSAMPLEMSBMSB−1SDOLSB+1td18Full ICCFigure55.DeviceNapPowerDown/Resume
LAYOUT
Foroptimumperformance,careshouldbetakenwiththephysicallayoutoftheADS8370circuitry.
SincetheADS8370offerssingle-supplyoperation,itisoftenusedincloseproximitywithdigitallogic,microcontrollers,microprocessors,anddigitalsignalprocessors.Themorethedigitallogicinthedesignandthehighertheswitchingspeed,thegreatertheneedforbetterlayoutandisolationofthecriticalanalogsignalsfromtheseswitchingdigitalsignals.
ThebasicSARarchitectureissensitivetoglitchesorsuddenchangesonthepowersupply,reference,groundconnectionsanddigitalinputsthatoccurjustpriortotheendofsamplingandjustpriortothelatchingoftheanalogcomparator.Suchglitchesmightoriginatefromswitchingpowersupplies,nearbydigitallogic,orhighpowerdevices.Noiseduringtheendofsamplingandthelatterhalfoftheconversionmustbekepttoaminimum(theformerhalfoftheconversionisnotverysensitivesincethedeviceusesaproprietaryerrorcorrectionalgorithmtocorrectforthetransienterrorsmadehere).
Thedegreeoferrorinthedigitaloutputdependsonthereferencevoltage,layout,andtheexacttiminganddegreeoftheexternalevent.
Onaverage,theADS8370drawsverylittlecurrentfromanexternalreferenceasthereferencevoltageisinternallybuffered.Ifthereferencevoltageisexternal,itmustbeensuredthatthereferencesourcecandrivethebypasscapacitorwithoutoscillation.A0.1-µFbypasscapacitorisrecommendedfrompin8directlytopin7(REFM).
TheAGNDandBDGNDpinsshouldbeconnectedtoacleangroundpoint.Inallcases,thisshouldbetheanalogground.Avoidconnectionsthataretooclosetothegroundingpointofamicrocontrollerordigitalsignalprocessor.Ifrequired,runagroundtracedirectlyfromtheconvertertothepowersupplyentrypoint.Theideallayoutconsistsofananaloggroundplanededicatedtotheconverterandassociatedanalogcircuitry.
AswiththeAGNDconnections,+VAshouldbeconnectedtoa+5-Vpower-supplyplaneortracethatisseparatefromtheconnectionfordigitallogicuntiltheyareconnectedatthepowerentrypoint.PowertotheADS8370shouldbecleanandwellbypassed.A0.1-µFceramicbypasscapacitorshouldbeplacedasclosetothedeviceaspossible.SeeTable3fortheplacementofthesecapacitors.Inaddition,a1-µFcapacitorisrecommended.Insomesituations,additionalbypassingmayberequired,suchasa100-µFelectrolyticcapacitororevenaPifiltermadeupofinductorsandcapacitors—alldesignedtoessentiallylow-passfilterthe+5-Vsupply,removingthehighfrequencynoise.
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Table3.PowerSupplyDecouplingCapacitorPlacement
SUPPLYPINS
PairofpinsrequiringashortestpathtodecouplingcapacitorsPinsrequiringnodecoupling
CONVERTERANALOGSIDE(2,3);(5,6);(15,16);(17,18)
4,14,19
CONVERTERDIGITAL
SIDE
(20,21)
Whenusingtheinternalreference,ensureashortestpathfromREFOUT(pin9)toREFIN(pin8)withthebypasscapacitordirectlybetweenpins8and7.
APPLICATIONINFORMATION
EXAMPLEDIGITALSTIMULUS
TheuseoftheADS8370isverystraightforward.Thefollowingtimingdiagramshowsoneexampleofhowtoachievea600-KSPSthroughputusingaSPIcompatibleserialinterface.
BUSYDEVICE STATECONVERTSAMPLECONVERTCONVSTFrequency = 600 kHz15 nsCS15 ns485 ns80 ns50 ns25 ns 2 3 15 16SCLK12.5 nsSDOMSBD15D14D13D2D1LSBD0Figure56.ExampleStimulusinSPIMode(FS=1),Back-To-BackConversionthatAchieves600KSPS
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APPLICATIONINFORMATION(continued)
Itisalsopossibletousetheframesyncsignal,FS.Thefollowingtimingdiagramshowshowtoachievea600-KSPSthroughputusingamodifiedserialinterfacewithFSactive.
BUSYDEVICE STATECONVERTSAMPLECONVERTFrequency = 600 kHzCONVSTCS = 015 nsFS15 ns485 ns50 ns80 ns25 ns 1 2 3 15 16SCLK12.5 nsSDOLSBn−1D0MSBnD15D14D13D2D1LSBnD0Figure57.ExampleStimulusinSerialInterfaceWithFSActive,Back-To-BackConversionthatAchieves
600KSPS
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PACKAGINGINFORMATION
OrderableDeviceADS8370IBRHPRADS8370IBRHPTADS8370IBRHPTG4ADS8370IRHPRADS8370IRHPT
(1)
Status(1)ACTIVEACTIVEACTIVEACTIVEACTIVE
PackageTypeQFNQFNQFNQFNQFN
PackageDrawingRHPRHPRHPRHPRHP
PinsPackageEcoPlan(2)
Qty2828282828
25002502502500250
TBDGreen(RoHS&noSb/Br)Green(RoHS&noSb/Br)
TBDTBD
Lead/BallFinish
CallTICUNIPDAUCUNIPDAUCallTICallTI
MSLPeakTemp(3)CallTI
Level-2-260C-1YEARLevel-2-260C-1YEARCallTI
Level-2-260C-1YEAR
Themarketingstatusvaluesaredefinedasfollows:ACTIVE:Productdevicerecommendedfornewdesigns.
LIFEBUY:TIhasannouncedthatthedevicewillbediscontinued,andalifetime-buyperiodisineffect.
NRND:Notrecommendedfornewdesigns.Deviceisinproductiontosupportexistingcustomers,butTIdoesnotrecommendusingthispartinanewdesign.
PREVIEW:Devicehasbeenannouncedbutisnotinproduction.Samplesmayormaynotbeavailable.OBSOLETE:TIhasdiscontinuedtheproductionofthedevice.
(2)
EcoPlan-Theplannedeco-friendlyclassification:Pb-Free(RoHS)orGreen(RoHS&noSb/Br)-pleasecheckhttp://www.ti.com/productcontentforthelatestavailabilityinformationandadditionalproductcontentdetails.TBD:ThePb-Free/Greenconversionplanhasnotbeendefined.
Pb-Free(RoHS):TI'sterms\"Lead-Free\"or\"Pb-Free\"meansemiconductorproductsthatarecompatiblewiththecurrentRoHSrequirementsforall6substances,includingtherequirementthatleadnotexceed0.1%byweightinhomogeneousmaterials.Wheredesignedtobesolderedathightemperatures,TIPb-Freeproductsaresuitableforuseinspecifiedlead-freeprocesses.
Green(RoHS&noSb/Br):TIdefines\"Green\"tomeanPb-Free(RoHScompatible),andfreeofBromine(Br)andAntimony(Sb)basedflameretardants(BrorSbdonotexceed0.1%byweightinhomogeneousmaterial)
(3)
MSL,PeakTemp.--TheMoistureSensitivityLevelratingaccordingtotheJEDECindustrystandardclassifications,andpeaksoldertemperature.
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