IP1726 + IP108 layout Guide Jun 30

IP1726+IP108 PCB Layout Guide

1. Introduction

This guide will help one to make good PCB for IP1726+IP108 circuit board.

The goals for this document are to reduce noise and other interference to the chip, and also to prevent the EMI effect of the chip. There are following sections will be covered: 󰁺 General layout guideline 󰁺 Ground

󰁺 Power Supply 󰁺 Signal Trace

2. General Layout Guideline

The following recommended steps would help the customer to gain the maximum performance.

The high speed signal trace should be kept away from the board border at least 100mil width.

high speed signal

IP1726+IP108 system boardPoor

board borderat least 100milIP1726+IP108 system boardFair

high speed signal

Figure 2.1 Keep the high speed signal away from the border

Utilize the source termination scheme to improve the impendence match and the signal integrity. The termination resistor should be close to the signal output end.

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IP1726+IP108 PCB layout guide IP1726TX signalsR value=22-33Source terminationSignal traceSource termination Ver. 1.5 R value=22-33RX signalsIP108Figure 2.2 Source termination scheme

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IP1726+IP108 PCB layout guide

3. Ground

3.1 Signal Ground

To reduce the electromagnetic radiation and noise coupling, the signal ground plane should be made as an unbroken layer to provide a low impedance for the signal return path. The following figure shows the incorrect & correct ground plane layout.

Good Poor Signal Signal GND GND IP1726IP1726 IP108IP108IP108IP108IP108IP108

TransformeTransformeTransformeTransformeTransformeTransforme

RJ45 Phone Jack RJ45 Phone Jack Chassis GND Chassis GND

Figure 3.1 The correct & incorrect ground plane

The digital GND and analogue GND should be connected as one large GND plane.

3.2 Chassis Ground

The designer can place a 1nF/2KV capacitor and a large impedance resistor between the Chassis ground and the signal ground. This design can improve the ESD immunity.

1nF/2KV

1M ohm

Figure 3.2 Improve the ESD immunity by the extra components

The chassis ground and the signal should be separated by at least 80mils wide.

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IP1726+IP108 PCB layout guide

4. Power

A 0.01£gF ~ 0.1£gF capacitor should be placed as close to the power pins as possible(L<0.3 inch ) for each VDD and GND pair.

Good Poor

IP1726 VDD or IP108 GND

LCapIP1726 VDDor IP108 GNDLCap Figure 4.1 Place a decoupling capacitor for each VDD, GND pair

Do not connect the analog power to I/O power directly. Various power sources should be separated by a ferrite BEAD as shown below. The ferrite BEAD should behave like a high

impedance at the frequency higher than 100MHz and behave like a very low impedance at the DC.

Good AVDD1.8VDVDD;IOVDD1.8VPoorDVDD; AVDD1.8VIOVDD1.8VFerrite beadReg. controlDVDD; AVDD1.8VIOVDD3.3VReg. controlDVDD; AVDD1.8VIOVDD3.3VFerrite beadDVDD: Digital VDD; AVDD: AnalogVDD; IOVDD:I/OVDD

Figure 4.2 Power sources separation

Use as many as vias as possible in power connection to keep low impedance when power trace changes layer.

Good Poor

Power trace Via ViaPower trace Power tracePower trace

Figure 4.3 Change the player of the power plane

If a bipolar transistor is used to generate the IP108 1.8V power, the power consumption on the transistor may be as high as 1.45W in the full load case. A solder plate under the transistor for the heat ventilation is necessary. The ventilation area should be at least 70 mm X 70 mm.

5. Signal Trace

5.1 Generic signal trace

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IP1726+IP108 PCB layout guide oAvoid 90 signal tracing.

Good Poor IP1726 or IP108 IP1726 or IP108 Figure 5.1 Signal trace layout 5.2 SS-SMII

All SS-SMII signal trace should be kept as short as possible. The longer the SS-SMII trace is, the poorer the EMI performance.

Utilize the ground guard trace to reduce the EMI effect, IP1726GNDVIA

Guard traceSignal

IP108SS-SMII Interface

Figure 5.2 The SS-SMII layout

5.3 MDC and MDIO recommendation

The MDIO and MDC are routed across every IP108 and IP1726 and likely to be interfered by the high-speed clock, such as TXCLK and RXCLK. It’s recommended that the MDC and MDIO should not be parallel to any high-speed click signal to avoid the interference.

MDC/MDIORXCLK/TXCLK

MDC/MDIORXCLK/TXCLK

PoorGood

Figure 5.3 Avoid signal interference

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IP1726+IP108 PCB layout guide

In 16 and 24 ports Switch system, the MDC and the MDIO are routed to each PHY device. To achieve the best performance of signal quality, the width and the space for both signals should be routed as the figure shown below

MDC=8milMDIO=8mil

MDC &MDIO space=16mil

MDCMDIOIP1726MDCMDIOMDCMDIOMDCMDIOIP108IP108IP10824 ports Switch MDC & MDIO connection

Figure 5.4 MDC and MDIO trace layout

5.4 Transformer and RJ-45 phone jack

The termination resistors should be close to the output of the TD+/- pair of the IP108. It is

recommended that the twisted pair trace be routed so that the space between the + signal and the – signal is close to each other. The space between each pair (TX pair or RX pair) is at least 24 mils wide.

In order to keep the impedance match, the via between the secondary winding and the RJ-45 phone jack is not allowed.

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IP1726+IP108 PCB layout guide IP108TX or RX pairTX or RX pairWidth=8 milWidth=8 milTransformer...........

Figure 5.5 Differential pair layout recommendation

The central tap of primary winding of the transformer must be connected to analog 1.8V.

A decoupling capacitor(0.01£gF ~ 0.1£gF) should be placed close to the primary winding of the transformer.

Width=8 milS>24milWidth=8 mil...........

Analog1.8V powerCapacitorGND...........AVDDTransformer...........

Figure 5.6 The decoupling capacitor at the primary end of the transformer

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