专利名称：Memory with shared write bit line(s)发明人：Ravindraraj Ramaraju申请号：US11619808申请日：20070104公开号：US07649764B2公开日：20100119
专利附图：
摘要：A memory includes at least one write bit line and a plurality of memory cells.The at least one write bit line is configured to carry a write bit signal. The plurality ofmemory cells are arranged in a column and are configured to be selectively coupled tothe at least one write bit line. The plurality of memory cells are configured to be
selectively read or written in a first phase of a cycle and selectively read or written in asecond phase of the cycle using the at least one write bit line.
申请人：Ravindraraj Ramaraju
地址：Round Rock TX US
国籍：US
代理机构：Dillon & Yudell LLP
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