Circuit arrangement for accelerated carry formatio

专利名称：Circuit arrangement for accelerated carry

formation in an adder device

发明人：Hans K. Nussbaecher申请号：US06/595241申请日：19840330公开号：US04639888A公开日：19870127

摘要：A parallel combinational logic system has a shortened carry run for two binarily-coded numbers upon consideration of an input carry. In order to shorten the carrythroughput time, two alternative carries are respectively formed, group-wise, from thesums of the operands in first combinational logic units, the actual result carries beingselected therefrom and from a decision logic unit, upon consideration of other groupcarries. These result carries are supplied to second combinational logic units at whoseinputs the operands to be combined are applied. Under the control of the result carries,the operands are combined group- wise with one another or, respectively, the final resultis selected from two alternative intermediate results.

申请人：SIEMENS AKTIENGESELLSCHAFT

代理机构：Hill, Van Santen, Steadman & Simpson

更多信息请下载全文后查看