Si5319
ANY-RATE PRECISION CLOCK MULTIPLIER/JITTER ATTENUATOR
Description
The Si5319 is a jitter-attenuating precision M/N clockmultiplier for applications requiring sub 1ps jitterperformance. The Si5319 accepts one clock input rangingfrom 2kHz to 710MHz and generates one clock outputranging from 2kHz to 945MHz and select frequencies to1.4GHz. The Si5319 can also use its crystal oscillator as aclock source for frequency synthesis. The device providesvirtually any frequency translation combination across thisoperating range. The Si5319 input clock frequency and clockmultiplication ratio are programmable through an I2C or SPIinterface. The Si5319 is based on Silicon Laboratories' 3rd-generation DSPLL® technology, which provides any-ratefrequency synthesis and jitter attenuation in a highlyintegrated PLL solution that eliminates the need for externalVCXO and loop filter components. The DSPLL loopbandwidth is digitally programmable, providing jitterperformance optimization at the application level. Operatingfrom a single 1.8, 2.5, or 3.3V supply, the Si5319 is ideal forproviding clock multiplication and jitter attenuation in highperformance timing applications.
Features
Generates any frequency from 2kHz to 945MHz and select frequencies to 1.4GHz from an input frequency of 2kHz to 710MHz
Ultra-low jitter clock outputs with jitter generation as lowas0.3psrms(50kHz–80MHz)
Integrated loop filter with selectable loop bandwidth (60Hzto8.4kHz)
Meets OC-192 GR-253-CORE jitter specificationsClock or crystal input with manual clock selectionClock output selectable signal format (LVPECL, LVDS, CML, CMOS)
Support for ITU G.709 and custom FEC ratios (255/238, 255/237, 255/236)
Supports various frequency translations for Synchronous EthernetLOL, LOS alarm outputs
Applications
SONET/SDH OC-48/STM-16 and OC-192/STM-64line cards
GbE/10GbE, 1/2/4/8/10GFC line cardsITU G.709 and custom FEC line cardsOptical modules
Wireless basestationsData converter clockingxDSL
Synchronous EthernetTest and measurementDiscrete PLL replacementBroadcast video
Xtal or RefclockXOI2C or SPI programmable
On-chip voltage regulator for 1.8V ±5%, 2.5 or 3.3V ±10% operationSmall size: 6x6mm 36-lead QFNPb-free, ROHS compliant
÷ NC1_LS÷ N32CKIN÷ N31÷ N2CKOUTDSPLL®N1_HSLoss of SignalLoss of LockSignal DetectControlVDD (1.8, 2.5, or 3.3 V) GNDI2C/SPI PortDevice InterruptRate SelectXtal/Clock SelectPreliminary Rev. 0.3 1/08Copyright © 2008 by Silicon LaboratoriesSi5319
This information applies to a product under development. Its characteristics and specifications are subject to change without notice.
Si5319
Table 1. Performance Specifications1
(VDD=1.8 ±5%, 2.5 ±10%, or 3.3V ±10%, TA=–40 to 85 ºC)
ParameterTemperature RangeSupply VoltageSymbolTAVDD
Test ConditionSupply Current
IDD
Input Clock Frequency (CKIN)
Output Clock Frequency (CKOUT)
CKFCKOF
fOUT = 622.08 MHzCKOUT enabled LVPECL format outputfOUT = 19.44 MHzCKOUT enabledCMOS format outputTristate/Sleep Mode
Input frequency and clock multi-plication ratio determined by programming device PLL divid-ers. Consult Silicon Laboratories configuration software DSPLL-sim to determine PLL divider settings for a given input fre-quency/clock multiplication ratio
combination.
See Note 2.
Min–402.972.251.71—Typ253.32.51.8217Max853.632.751.89243UnitºCVVVmA
—194220mA—0.0020.0029701213
165——
TBD71094511341400
mAMHzMHz
3-Level Input PinsInput Mid CurrentInput Clock (CKIN)Differential Voltage Swing
Common Mode Voltage
IIMMCKNDPPCKNVCM
–20.25
———————————230—
21.91.41.71.951160—VDD–1.25
1.90.93
350±40
µAVPPVVVns%nsVVpsps
Rise/Fall TimeDuty Cycle
(Minimum Pulse Width)
CKNTRFCKNDC
1.8V ±5%2.5V ±10%3.3V ±10%20–80%
Whichever is smaller
0.91.01.1—402VDD–1.42
1.10.5
——
Output Clock (CKOUT)Common ModeVOCMDifferential Output SwingVODSingle Ended Output VSESwing
Rise/Fall TimeCKOTRFOutput Duty Cycle CKODCDifferential Uncertainty
LVPECL100Ω loadline-to-line20–80% 100Ω loadline-to-line
measured at 50% point
Notes:
1.For a more comprehensive listing of device specifications, consult the Silicon Laboratories Any-Rate Precision Clock
Family Reference Manual.
2. This is the amount of leakage that the 3-level input can tolerate from an external driver. See the Family Reference
Manual. In most designs an external resistor voltage divider is recommended.
2Preliminary Rev. 0.3
Si5319
Table 1. Performance Specifications1 (Continued)
(VDD=1.8 ±5%, 2.5 ±10%, or 3.3V ±10%, TA=–40 to 85 ºC)
ParameterPLL PerformanceJitter Generation
SymbolJGEN
Test ConditionfIN = fOUT = 622.08 MHz,LVPECL output format50kHz–80MHz12kHz–20MHz800Hz–80MHz
Min—
Typ0.3
MaxTBD
Unitps rms
Jitter TransferJPKExternal Reference Jitter JPKEXTNTransferPhase NoiseCKOPN
—
——————————
0.30.40.05TBDTBDTBDTBDTBDTBDTBDTBD
TBDTBD0.1TBDTBDTBDTBDTBDTBDTBDTBD
ps rmsps rmsdBdBdBc/HzdBc/HzdBc/HzdBc/HzdBc/HzdBcdBc
Subharmonic NoiseSpurious NoisePackage
Thermal Resistance Junction to Ambient
fIN = fOUT = 622.08 MHz
100 Hz offset1 kHz offset10 kHz offset100 kHz offset1 MHz offset
SPSUBHPhase Noise @ 100kHz OffsetSPSPURMax spur @ n x F3
(n > 1, n x F3 < 100MHz)
Still Air
Theta JA—38—ºC/W
Notes:1.For a more comprehensive listing of device specifications, consult the Silicon Laboratories Any-Rate Precision Clock
Family Reference Manual.
2. This is the amount of leakage that the 3-level input can tolerate from an external driver. See the Family Reference
Manual. In most designs an external resistor voltage divider is recommended.
Table 2. Absolute Maximum Ratings
ParameterDC Supply VoltageLVCMOS Input Voltage
Operating Junction TemperatureStorage Temperature Range
ESD HBM Tolerance (100 pF, 1.5kΩ), Except CKIN PinsESD HBM Tolerance (100 pF, 1.5kΩ), CKIN PinsESD MM Tolerance, Except CKIN PinsESD MM Tolernace, CKIN PinsLatch-Up Tolerance
SymbolVDDVDIGTJCTTSTG
Value–0.5 to 3.6–0.3 to (VDD + 0.3)
–55 to 150–55 to 150
2700200150
JESD78 Compliant
UnitVVºCºCkVVVV
Note:Permanent device damage may occur if the Absolute Maximum Ratings are exceeded. Functional operation should be
restricted to the conditions as specified in the operation sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods of time may affect device reliability.
Preliminary Rev. 0.33
Si5319
155.52 MHz in, 622.08 MHz out0-20Phase Noise (dBc/Hz)-40-60-80-100-120-140-160100100010000100000100000010000000100000000Offset Frequency (Hz)Figure1.Typical Phase Noise PlotJitter Band
Brick Wall, 100 Hz to 100 MHzSONET_OC48, 12 kHz to 20 MHzSONET_OC192_A, 20 kHz to 80 MHzSONET_OC192_B, 4 MHz to 80 MHzSONET_OC192_C, 50 kHz to 80 MHzBrick Wall, 800 Hz to 80 MHz
Jitter, RMS1,279 fs315 fs335 fs194 fs318 fs343 fs
4Preliminary Rev. 0.3
Si5319
C41 µFSystem Power SupplyC10.1 µFFerriteBeadC20.1 µFC30.1 µF0.1 µFCKOUT+100 ΩCKOUT–0.1 µF–+VDD= 3.3 V130 Ω130 ΩCKIN+CKIN–82 Ω82 ΩGNDVDDSi5319Option 1:CrystalXBCrystal/RefClk RateRATE[1:0]0.1 µFRefclk+Refclk–Control Mode (L)Reset0.1 µFXAXBCMODERSTXAINT_CBInterrupt/CKIN Invalid IndicatorLOLPLL Loss of Lock IndicatorA[2:0]SDASCLSerial Port AddressSerial DataSerial ClockI2C InterfaceOption 2:CSXtal/Clock Select*Note:Assumes differential LVPECL termination (3.3 V) on clock inputs.Figure2.Si5319 Typical Application Circuit (I2C Control Mode)
C41 µFSystem Power SupplyC10.1 µFFerriteBeadC20.1 µFC30.1 µF0.1 µFCKOUT+100 ΩCKOUT–0.1 µF–+VDD= 3.3 V130 Ω130 ΩCKIN+CKIN–82 Ω82 ΩGNDVDDINT_CBInterrupt/CLKIN Invalid IndicatorSi5319LOLPLL Loss of Lock IndicatorOption 1:CrystalXAXBCrystal/RefClk RateRATE[1:0]0.1 µFRefclk+0.1 µFRefclk–Control Mode (H)ResetXAXBCMODERSTSSSDOSDISCLKSlave SelectSerial Data OutSPI InterfaceSerial Data InSerial ClockOption 2:CSXtal/Clock Select*Note:Assumes differential LVPECL termination (3.3 V) on clock inputs.Figure3.Si5319 Typical Application Circuit (SPI Control Mode)
Preliminary Rev. 0.35
Si5319
1. Functional Description
The Si5319 is a jitter-attenuating precision clockmultiplier for applications requiring sub 1ps jitterperformance. The Si5319 accepts one clock inputranging from 2kHz to 710MHz and generates oneclock output ranging from 2kHz to 945MHz and selectfrequencies to 1.4GHz. The Si5319 can also use itscrystal oscillator as a clock source for frequencysynthesis. The device provides virtually any frequencytranslation combination across this operating range.The Si5319 input clock frequency and clockmultiplication ratio are programmable through an I2C orSPI interface. Silicon Laboratories offers a PC-basedsoftware utility, DSPLLsim, that can be used todetermine the optimum PLL divider settings for a giveninput frequency/clock multiplication ratio combinationthat minimizes phase noise and power consumption.This utility can be downloaded fromhttp://www.silabs.com/timing.
The Si5319 is based on Silicon Laboratories' 3rd-generation DSPLL® technology, which provides any-rate frequency synthesis and jitter attenuation in ahighly integrated PLL solution that eliminates the needfor external VCXO and loop filter components. TheSi5319 PLL loop bandwidth is digitally programmableand supports a range from 60Hz to 8.4kHz. TheDSPLLsim software utility can be used to calculate validloop bandwidth settings for a given input clockfrequency/clock multiplication ratio.
The Si5319 monitors the input clock for loss-of-signaland provides a LOS alarm when it detects missingpulses on the input clock. The device monitors the lockstatus of the PLL. The lock detect algorithm works bycontinuously monitoring the phase of the input clock inrelation to the phase of the feedback clock.
The Si5319 provides a digital hold capability that allowsthe device to continue generation of a stable outputclock when the selected input reference is lost. Duringdigital hold, the DSPLL freezes its VCO settings anduses its XO as its frequency reference.The Si5319 has one differential clock output. Theelectrical format of the clock output is programmable tosupport LVPECL, LVDS, CML, or CMOS loads. Forsystem-level debugging, a bypass mode is availablewhich drives the output clock directly from the inputclock, bypassing the internal DSPLL. The device ispowered by a single 1.8, 2.5, or 3.3V supply.
1.1. External Reference
A low-cost 114.285MHz 3rd overtone crystal or anexternal reference oscillator is used as part of a fixed-frequency oscillator within the DSPLL. This externalreference is required for the device to perform jitterattenuation. Silicon Laboratories recommends using ahigh quality crystal. Specific recommendations may befound in the Family Reference Manual. An externaloscillator as well as other crystal frequencies can alsobe used as a reference for the device.
In digital hold, the DSPLL remains locked to thisexternal reference. Any changes in the frequency of thisreference when the DSPLL is in digital hold will betracked by the output of the device. Note that crystalscan have temperature sensitivities.
1.2. Further Documentation
Consult the Silicon Laboratories Any-Rate PrecisionClock Family Reference Manual (FRM) for detailedinformation about the Si5319. Additional design supportis available from Silicon Laboratories through yourdistributor.
Silicon Laboratories has developed a PC-basedsoftware utility called DSPLLsim to simplify deviceconfiguration, including frequency planning and loopbandwidth selection. The FRM and this utility can bedownloaded from http://www.silabs.com/timing; click onDocumentation.
6Preliminary Rev. 0.3
Si5319
2. Pin Descriptions: Si5319
CKOUT+27SDI26A2_SS25A124A023SDA_SDO22SCL21CS20GND19GND101112131415161718RATE0NCRATE1CKIN1+CKIN1–VDDLOLNCNCCKOUT–CMODEGNDVDDNCNCNCNC363534333231302928RSTNCINT_CBNCVDDXAXBGNDNC123456789GND PadPin numbers are preliminary and subject to change.Pin #1
Pin NameRST
I/OI
Signal LevelLVCMOS
Description
External Reset.
Active low input that performs external hardware reset of device. Resets all internal logic to a known state and forces the device regis-ters to their default value. Clock outputs are disabled during reset. The part must be programmed after a reset or power-on to get a clock out-put. See Family Reference Manual for details.This pin has a weak pull-up.No Connect.This pin must be left unconnected for normal operation.
2, 4, 9, 12–14, 30, 33–353
NC——
INT_CBOLVCMOS
Interrupt/CKIN Invalid Indicator.This pin functions as a device interrupt output or an alarm output for CKIN. If used as an interrupt output, INT_PIN must be set to 1. The pin functions as a maskable interrupt output with active polarity controlled by the INT_POL register bit.
If used as an alarm output, the pin functions as a LOS alarm indicator for CKIN. Set CK_BAD_PIN=1 and INT_PIN=0.0 = CKIN present.1 = LOS on CKIN.
The active polarity is controlled by CK_BAD_POL. If no function is selected, the pin tristates.
Note:Internal register names are indicated by underlined italics (e.g., INT_PIN. See Si5319 Register Map).
Preliminary Rev. 0.37
Si5319
Pin #5, 10, 32
Pin NameVDD
I/OVDD
Signal LevelSupply
DescriptionSupply.The device operates from a 1.8, 2.5, or 3.3V supply. Bypass capaci-tors should be associated with the following VDD pins:50.1µF100.1µF320.1µF
A 1.0µF should also be placed as close to the device as is practical.External Crystal or Reference Clock.
External crystal should be connected to these pins to use internal oscillator based reference. Refer to the Family Reference Manual for interfacing to an external reference. The external reference must be from a high-quality clock source (TCXO, OCXO). Frequency of crystal or external clock is set by the RATE pins.Ground.
Must be connected to system ground. Minimize the ground path impedance for optimal performance of this device.External Crystal or Reference Clock Rate.Three level inputs that select the type and rate of external crystal or reference clock to be applied to the XA/XB port. Refer to the Family Reference Manual for settings. These pins have both a weak pull-up and a weak pull-down; they default to M. The \"HH\" setting is not sup-ported.
Some designs may require an external resistor voltage divider when driven by an active device that will tri-state.Clock Input.
Differential input clock. This input can also be driven with a single-ended signal. Input frequency range is 2kHz to 710MHz.PLL Loss of Lock Indicator.This pin functions as the active high PLL loss of lock indicator if the LOL_PIN register bit is set to 1.0 = PLL locked.1 = PLL unlocked.
If LOL_PIN=0, this pin will tristate. Active polarity is controlled by the LOL_POL bit. The PLL lock status will always be reflected in the LOL_INT read only register bit.Xtal/Input Clock Select.
This pin selects the active DSPLL input clock, which can be a clock input or a crystal input. See the FREE_EN register for free run settings.0 = Select clock input (CKIN).1 = Select crystal input.
This pin should not be left open.Serial Clock/Serial Clock.
This pin functions as the serial clock input for both SPI and I2C modes. This pin has a weak pull-down.
76XBXA
IAnalog
8, 31
GND
GNDSupply
1115RATE0RATE1
I3-Level
161718
CKIN+CKIN–LOL
IMulti
OLVCMOS
21CSILVCMOS
22SCLILVCMOS
Note:Internal register names are indicated by underlined italics (e.g., INT_PIN. See Si5319 Register Map).
8Preliminary Rev. 0.3
Si5319
Pin #23
Pin NameSDA_SDO
I/OI/O
Signal LevelLVCMOS
DescriptionSerial Data.In I2C control mode (CMODE=0), this pin functions as the bidirec-tional serial data port.
In SPI control mode (CMODE=1), this pin functions as the serial data output.
Serial Port Address.In I2C control mode (CMODE=0), these pins function as hardware controlled address bits. The I2C address is 1101 [A2] [A1] [A0].In SPI control mode (CMODE=1), these pins are ignored.These pins have a weak pull-down.Serial Port Address/Slave Select.In I2C control mode (CMODE=0), this pin functions as a hardware controlled address bit [A2].
In SPI control mode (CMODE=1), this pin functions as the slave select input.
This pin has a weak pull-down.Serial Data In.
In I2C control mode (CMODE=0), this pin is ignored.
In SPI control mode (CMODE=1), this pin functions as the serial data input.
This pin has a weak pull-down.Output Clock.
Differential output clock with a frequency range of 10MHz to
1.4175GHz. Output signal format is selected by SFOUT1_REG regis-ter bits. Output is differential for LVPECL, LVDS, and CML compatible modes. For CMOS format, both output pins drive identical single-ended clock outputs.Control Mode.Selects I2C or SPI control mode for the Si5319.0 = I2C Control Mode1 = SPI Control ModeGround Pad.The ground pad must provide a low thermal and electrical impedance to a ground plane.
2524A1A0
ILVCMOS
26A2_SSILVCMOS
27SDIILVCMOS
2928CKOUT–CKOUT+
OMulti
36CMODEILVCMOS
GND PAD
GNDGNDSupply
Note:Internal register names are indicated by underlined italics (e.g., INT_PIN. See Si5319 Register Map).
Preliminary Rev. 0.39
Si5319
3. Ordering Guide
Ordering Part NumberSi5319A-C-GM
Output Clock Frequency Range2kHz–945MHz970–1134MHz1.213–1.417GHz2kHz–808MHz2kHz–346MHz
Package
36-Lead 6x6mm QFN
ROHS6, Pb-FreeYes
Temperature Range
–40 to 85°C
Si5319B-C-GMSi5319C-C-GM
36-Lead 6x6mm QFN36-Lead 6x6mm QFN
YesYes
–40 to 85°C–40 to 85°C
10Preliminary Rev. 0.3
Si5319
4. Package Outline: 36-Pin QFN
Figure4 illustrates the package details for the Si5319. Table3 lists the values for the dimensions shown in theillustration.
Figure4.36-Pin Quad Flat No-lead (QFN)
Table 3. Package Dimensions
Symbol
MinAA1bDD2eEE2
3.953.950.800.000.18
Millimeters
Nom0.850.020.256.00 BSC4.100.50 BSC6.00 BSC4.10
4.254.25Max0.900.050.30
LθaaabbbcccdddeeeSymbol
Min0.50——————
Millimeters
Nom0.60——————
Max0.7012º0.100.100.080.100.05
Notes:
1.All dimensions shown are in millimeters (mm) unless otherwise noted.2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.
3. This drawing conforms to JEDEC outline MO-220, variation VJJD.
4. Recommended card reflow profile is per the JEDEC/IPC J-STD-020C specification for Small Body
Components.
Preliminary Rev. 0.311
Si5319
5. Recommended PCB Layout
Figure5.PCB Land Pattern Diagram12Preliminary Rev. 0.3
Si5319
Table 4. PCB Land Pattern Dimensions
DimensioneEDE2D2GEGDXYZEZD
——4.004.004.534.53—
0.89REF.
6.316.31
MIN0.50 BSC.5.42REF.5.42REF.
4.204.20——0.28MAXNotes (General):
1.All dimensions shown are in millimeters (mm) unless otherwise noted.2. Dimensioning and Tolerancing is per the ANSI Y14.5M-1994 specification.
3. This Land Pattern Design is based on IPC-SM-782 guidelines.
4. All dimensions shown are at Maximum Material Condition (MMC). Least Material
Condition (LMC) is calculated based on a Fabrication Allowance of 0.05mm.Notes (Solder Mask Design):
1.All metal pads are to be non-solder mask defined (NSMD). Clearance between the
solder mask and the metal pad is to be 60 µm minimum, all the way around the pad.
Notes (Stencil Design):
1.A stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should be
used to assure good solder paste release.
2. The stencil thickness should be 0.125mm (5 mils).
3. The ratio of stencil aperture to land pad size should be 1:1 for the perimeter pads. 4. A 4x4 array of 0.80mm square openings on 1.05mm pitch should be used for the
center ground pad.Notes (Card Assembly):
1.A No-Clean, Type-3 solder paste is recommended.
2. The recommended card reflow profile is per the JEDEC/IPC J-STD-020C specification
for Small Body Components.
Preliminary Rev. 0.313
Si5319
DOCUMENT CHANGE LIST
Revision 0.1 to Revision 0.2
Changed 1.8V operating range to ±5%.Updated Table1 on page2.Updated Table2 on page3.
Added table under Figure1 on page 4.
Updated \"1. Functional Description\" on page 6.Clarified \"2. Pin Descriptions: Si5319\" on page 7.
Revision 0.2 to Revision 0.3
Updated \"2. Pin Descriptions: Si5319\" on page 7.
Corrected Pins 11 and 15 description in table.
14Preliminary Rev. 0.3
Si5319
NOTES:
Preliminary Rev. 0.315
Si5319
CONTACT INFORMATION
Silicon Laboratories Inc.400 West Cesar ChavezAustin, TX 78701
Tel: 1+(512) 416-8500Fax: 1+(512) 416-9669
Toll Free: 1+(877) 444-3032Email: Clockinfo@silabs.comInternet: www.silabs.com
The information in this document is believed to be accurate in all respects at the time of publication but is subject to change without notice. Silicon Laboratories assumes no responsibility for errors and omissions, and disclaims responsibility for any consequences resulting from the use of information included herein. Additionally, Silicon Laboratories assumes no responsibility for the functioning of undescribed features or parameters. Silicon Laboratories reserves the right to make changes without further notice. Silicon Laboratories makes no warranty, rep-resentation or guarantee regarding the suitability of its products for any particular purpose, nor does Silicon Laboratories assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation conse-quential or incidental damages. Silicon Laboratories products are not designed, intended, or authorized for use in applications intended to support or sustain life, or for any other application in which the failure of the Silicon Laboratories product could create a situation where per-sonal injury or death may occur. Should Buyer purchase or use Silicon Laboratories products for any such unintended or unauthorized ap-plication, Buyer shall indemnify and hold Silicon Laboratories harmless against all claims and damages.
Silicon Laboratories, Silicon Labs, and DSPLL are trademarks of Silicon Laboratories Inc.
Other products or brandnames mentioned herein are trademarks or registered trademarks of their respective holders.
16Preliminary Rev. 0.3
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