函数信号发生器VHDL

1、按键防抖电路及各分频电路略

2、9位二进制计数器—ROM地址发生器—寻址512字节

library ieee;

use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity hh_cnt9b is port(clk,en:in std_logic;

q:out std_logic_vector(8 downto 0)); end hh_cnt9b;

architecture bav of hh_cnt9b is

signal cnt:std_logic_vector(8 downto 0); begin process(clk) begin

if clk'event and clk='1' then if cnt=\"000000000\" then cnt<=\"111111111\"; else

cnt<=cnt+1; end if; end process; end bav;

3、波形存储单元-ROM模块

4、6选1数据选择器 library ieee;

use ieee.std_logic_1164.all;

entity hh_mux6 is

port(a,b,c,d,e,f:in std_logic_vector(7 downto 0); sw0,sw1,sw2:in std_logic;

dataout:out std_logic_vector(7 downto 0); din:out std_logic_vector(3 downto 0)); end hh_mux6;

architecture bav of hh_mux6 is

signal sw:std_logic_vector(4 downto 0); begin

sw<=sw0&sw1&sw2; process(sw,a,b,c,d,e,f) begin

case sw is

when \"000\"=>dataout<=\"00000000\";din<=\"0000\"; when \"001\"=>dataout<=a;din<=\"0001\"; when \"010\"=>dataout<=b;din<=\"0010\"; when \"011\"=>dataout<=c;din<=\"0011\"; when \"100\"=>dataout<=d;din<=\"0100\"; when \"101\"=>dataout<=e;din<=\"0101\"; when \"110\"=>dataout<=f;din<=\"0110\";

when \"111\"=>dataout<=\"00000000\";din<=\"0000\"; when others=>dataout<=\"00000000\";din<=\"0000\"; end case; end process; end bav;

5、学号产生与移位模块

library ieee;

use ieee.std_logic_1164.all;

entity hh_xuehao is port(clk:in std_logic;

din2,din3,din4,din5,din6,din7:out std_logic_vector(4 downto 0)); end hh_xuehao;

architecture bav of hh_xuehao is

signal xh:std_logic_vector(23 downto 0):=\"000010000100100101001000\"; begin

din2<=xh(23 downto 20); din3<=xh(19 downto 16); din4<=xh(15 downto 12); din5<=xh(11 downto 8); din6<=xh(7 downto 4); din7<=xh(3 downto 0); process(clk,xh) begin

if clk'event and clk='1' then

xh(3 downto 0)<=xh(23 downto 20); xh(7 downto 4)<=xh(3 downto 0); xh(11 downto 8)<=xh(7 downto 4); xh(15 downto 12)<=xh(11 downto 8); xh(19 downto 16)<=xh(15 downto 12); xh(23 downto 20)<=xh(19 downto 16); end if; end process; end bav;