Clock modulating circuit

专利名称：Clock modulating circuit发明人：Hirofumi Ebihara申请号：US10303838申请日：20021126公开号：US06822499B2公开日：20041123

专利附图：

摘要：A clock modulating circuit includes a first to nth delay circuits, a selection signalgenerator and a selection circuit. The first delay circuit receives an original clock signaland outputs a delayed clock signal. The second to nth delay circuits receive the delayedsignal output from the preceding delay circuit and output delayed clock signals. The

selection signal generator outputs a selection signal in response to the original clocksignal. The selection signal has an instruction for selecting in ascending order from thefirst to nth delay circuits and then in descending order from the nth to first delay circuits.The selection circuit is connected to the first to nth delay circuits and the selection signalgenerator. The selection circuit receives the delayed signals from the first to nth delaycircuits and outputs one of the delayed clock signals in response to the selection signal.

申请人：OKI ELECTRIC INDUSTRY CO., LTD.

代理机构：Volentine Francos & Whitt, PLLC

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