Area efficient fractureable logic elements

专利名称：Area efficient fractureable logic elements发明人：Sinan Kaptanoglu,Bruce B. Pedersen,James

G. Schleicher,Jinyong Yuan,Michael D.Hutton,David Lewis

申请号：US11234538申请日：20050922公开号：US07330052B2公开日：20080212

专利附图：

摘要：A fracturable logic element includes a first, second, third, and fourth two-inputlookup tables (2-LUTs). Each 2-LUT includes four memory elements. Each memory

element is configured to hold one data bit. The fracturable logic element also includes aset of six inputs and a control circuit configured to operate in a first mode and a secondmode. When the control circuit operates in the first mode, a first combinatorial output isgenerated using four of the set of six inputs and the first, second, third, and fourth 2-LUTs. When the control circuit operates in the second mode, a second combinatorialoutput is generated using a first subset of three of the set of six inputs and the first andsecond 2-LUTs. Additionally, when the control circuit operates in the second mode, athird combinatorial output is generated using a second subset of three of the set of sixinputs and the third and fourth 2-LUTs, the first and second subsets being non-intersecting subsets of the set of six inputs.

申请人：Sinan Kaptanoglu,Bruce B. Pedersen,James G. Schleicher,Jinyong Yuan,MichaelD. Hutton,David Lewis

地址：Belmont CA US,Sunnyvale CA US,Los Gatos CA US,Cupertino CA US,MountainView CA US,Toronto CA

国籍：US,US,US,US,US,CA

代理机构：Beyer Weaver LLP

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