元器件交易网www.cecb2b.comMC14013BDualTypeDFlip-FlopThe MC14013B dual type D flip–flop is constructed with MOSP–channel and N–channel enhancement mode devices in a singlemonolithic structure. Each flip–flop has independent Data, (D), DirectSet, (S), Direct Reset, (R), and Clock (C) inputs and complementaryoutputs (Q and Q). These devices may be used as shift registerelements or as type T flip–flops for counter and toggle applications.http://onsemi.comMARKINGDIAGRAMS14PDIP–14P SUFFIXCASE 646114SOIC–14D SUFFIXCASE 751A11414013BAWLYWWMC14013BCPAWLYYWW••••••Static OperationDiode Protection on All InputsSupply Voltage Range = 3.0 Vdc to 18 VdcLogic Edge–Clocked Flip–Flop DesignLogic state is retained indefinitely with clock level either high or low;information is transferred to the output only on the positive–goingedge of the clock pulseCapable of Driving Two Low–power TTL Loads or One Low–powerSchottky TTL Load Over the Rated Temperature RangePin–for–Pin Replacement for CD4013BMAXIMUM RATINGS (Voltages Referenced to VSS) (Note 2.)SymbolVDDVin, VoutIin, IoutPDTATstgTLParameterDC Supply Voltage RangeInput or Output Voltage Range(DC or Transient)Input or Output Current(DC or Transient) per PinPower Dissipation,per Package (Note 3.)Ambient Temperature RangeStorage Temperature RangeLead Temperature(8–Second Soldering)Value–0.5 to +18.0–0.5 to VDD + 0.5±10500–55 to +125–65 to +150260UnitVVmAmW°C°C°CTSSOP–14DT SUFFIXCASE 948G114SOEIAJ–14F SUFFIXCASE 9651A= Assembly LocationWL or L= Wafer LotYY or Y= YearWW or W= Work Week14013BALYWMC14013BAWLYWW2.Maximum Ratings are those values beyond which damage to the devicemay occur.3.Temperature Derating:Plastic “P and D/DW” Packages: – 7.0 mW/_C From 65_C To 125_CThis device contains protection circuitry to guard against damage due to highstatic voltages or electric fields. However, precautions must be taken to avoidapplications of any voltage higher than maximum rated voltages to thishigh–impedance circuit. For proper operation, Vin and Vout should be constrainedto the range VSS v (Vin or Vout) v VDD.Unused inputs must always be tied to an appropriate logic voltage level (e.g.,either VSS or VDD). Unused outputs must be left open.ORDERING INFORMATIONDeviceMC14013BCPMC14013BDMC14013BDR2MC14013BDTMC14013BDTR2MC14013BFMC14013BFELPackagePDIP–14SOIC–14SOIC–14TSSOP–14Shipping2000/Box55/Rail2500/Tape & Reel96/RailTSSOP–142500/Tape & ReelSOEIAJ–14SOEIAJ–14See Note 1.See Note 1.1.For ordering information on the EIAJ version ofthe SOIC packages, please contact your localON Semiconductor representative.© Semiconductor Components Industries, LLC, 20001March, 2000 – Rev. 3Publication Order Number:MC14013B/D元器件交易网www.cecb2b.comMC14013BTRUTH TABLEInputsClock†Data01XXXXXXXReset000101Set000011OutputsQ01Q011Q10Q101NoChangeX = Don’t Care† = Level ChangePIN ASSIGNMENTQAQACARADASAVSS1234567141312111098VDDQBQBCBRBDBSBBLOCK DIAGRAM65DSQ13489CRQ2DSQ131110CRQ12VDD = PIN 14VSS = PIN 7http://onsemi.com2元器件交易网www.cecb2b.comMC14013BELECTRICAL CHARACTERISTICS (Voltages Referenced to VSS)CharacteristicSymbolVOLVDDVdc5.010155.010155.010155.010155.05.010155.0101515—– 55_CMin———25_C125_CMaxMin———Typ (4.)000MaxMin———MaxUnitVdcOutput VoltageVin = VDD or 0Vin = 0 or VDD“0” Level0.050.050.05———0.050.050.05———0.050.050.05———“1” LevelVOH4.959.9514.95———4.959.9514.95———5.010154.959.9514.95———VdcInput Voltage“0” Level(VO = 4.5 or 0.5 Vdc)(VO = 9.0 or 1.0 Vdc)(VO = 13.5 or 1.5 Vdc)VIL1.53.04.0——————————2.254.506.752.755.508.251.53.04.0——————————1.53.04.0——————————Vdc(VO = 0.5 or 4.5 Vdc)“1” Level(VO = 1.0 or 9.0 Vdc)(VO = 1.5 or 13.5 Vdc)VIH3.57.0113.57.0113.57.011VdcOutput Drive Current(VOH = 2.5 Vdc) (VOH = 4.6 Vdc)(VOH = 9.5 Vdc)(VOH = 13.5 Vdc)(VOL = 0.4 Vdc) (VOL = 0.5 Vdc)(VOL = 1.5 Vdc)SourceIOHmAdc– 3.0– 0.64– 1.6– 4.20.641.64.2—————– 2.4– 0.51– 1.3– 3.40.511.33.4—————– 4.2– 0.88– 2.25– 8.80.882.258.8– 1.7– 0.36– 0.9– 2.40.360.92.4—————SinkIOLmAdcInput CurrentIin± 0.1—±0.000015.0± 0.17.51.02.04.0± 1.0—µAdcpFInput Capacitance(Vin = 0)CinQuiescent Current(Per Package)IDD5.010155.010151.02.04.00.0020.0040.0063060120µAdcTotal Supply Current (5.) (6.)(Dynamic plus Quiescent,Per Package)(CL = 50 pF on all outputs, allbuffers switching)ITIT = (0.75 µA/kHz) f + IDDIT = (1.5 µA/kHz) f + IDDIT = (2.3 µA/kHz) f + IDDµAdc4.Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.5.The formulas given are for the typical characteristics only at 25_C.6.To calculate total supply current at loads other than 50 pF:IT(CL) = IT(50 pF) + (CL – 50) Vfkwhere: IT is in µA (per package), CL in pF, V = (VDD – VSS) in volts, f in kHz is input frequency, and k = 0.002.http://onsemi.com3元器件交易网www.cecb2b.comMC14013BSWITCHING CHARACTERISTICS (7.) (CL = 50 pF, TA = 25_C)CharacteristicOutput Rise and Fall TimetTLH, tTHL = (1.5 ns/pF) CL + 25 nstTLH, tTHL = (0.75 ns/pF) CL + 12.5 nstTLH, tTHL = (0.55 ns/pF) CL + 9.5 nsSymboltTLH,tTHLVDD5.01015Min———Typ (8.)1005040Max20010080UnitnsPropagation Delay TimeClock to Q, QtPLH, tPHL = (1.7 ns/pF) CL + 90 nstPLH, tPHL = (0.66 ns/pF) CL + 42 nstPLH, tPHL = (0.5 ns/pF) CL + 25 nsSet to Q, QtPLH, tPHL = (1.7 ns/pF) CL + 90 nstPLH, tPHL = (0.66 ns/pF) CL + 42 nstPLH, tPHL = (0.5 ns/pF) CL + 25 nstPLHtPHLns5.010155.010155.010155.010155.010155.010155.010155.010155.010155101551015—————————175755017575502251007520107.520107.5350150100350150100450200150—————————Reset to Q, QtPLH, tPHL = (1.7 ns/pF) CL + 265 nstPLH, tPHL = (0.66 ns/pF) CL + 67 nstPLH, tPHL = (0.5 ns/pF) CL + 50 nsSetup Times (9.)tsu402015402015nsHold Times (9.)thnsClock Pulse WidthtWL, tWH25010070——————12550354.01014——1255035055nsClock Pulse Frequencyfcl2.05.07.0MHzClock Pulse Rise and Fall TimetTLHtTHL—155.04.0—————————µsSet and Reset Pulse WidthtWL, tWH25010070804535503025nsRemoval TimesSettremnsReset– 35– 10– 57.The formulas given are for the typical characteristics only at 25_C.8.Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.9.Data must be valid for 250 ns with a 5 V supply, 100 ns with 10 V, and 70 ns with 15 V.LOGIC DIAGRAM (1/2 of Device Shown)SDCCCCRCCCCCQCCQhttp://onsemi.com4元器件交易网www.cecb2b.comMC14013B20 nsDtsu (H)CtWH1fcl90%50%10%tTLHInputs R and S low.tTHL90%50%10%20 nsVDDVSS20 nsVDDVSSCLOCKtPHLVOHVOLQ OR QtPLHtPHL50%VOL20 nsSET ORRESET90%tw50%20 ns20 nsVDD10%trem90%50%tw20 ns10%VSSVDDVSSVOHtsu (L)th90%50%10%tWLtPLHQFigure 1. Dynamic Signal Waveforms(Data, Clock, and Output)Figure 2. Dynamic Signal Waveforms(Set, Reset, Clock, and Output)TYPICAL APPLICATIONSn–STAGE SHIFT REGISTER1DDCCLOCKQQDC2QQDCnthQQQBINARY RIPPLE UP–COUNTER (Divide–by–2n)1DCLOCKCQQDC2QQDCnthQQQT FLIP–FLOPMODIFIED RING COUNTER (Divide–by–(n+1))1DCCLOCKQQDC2QQDCnthQQQhttp://onsemi.com5元器件交易网www.cecb2b.comMC14013BPACKAGE DIMENSIONSP SUFFIXPLASTIC DIP PACKAGECASE 646–06ISSUE M148B17NOTES:1.DIMENSIONING AND TOLERANCING PER ANSIY14.5M, 1982.2.CONTROLLING DIMENSION: INCH.3.DIMENSION L TO CENTER OF LEADS WHENFORMED PARALLEL.4.DIMENSION B DOES NOT INCLUDE MOLD FLASH.5.ROUNDED CORNERS OPTIONAL.INCHESMILLIMETERSMINMAXMINMAX0.7150.77018.1618.800.2400.2606.106.600.1450.1853.694.690.0150.0210.380.530.0400.0701.021.780.100 BSC2.54 BSC0.0520.0951.322.410.0080.0150.200.380.1150.1352.923.430.2900.3107.377.87–––10 –––10 __0.0150.0390.381.01AFN–T–SEATINGPLANELCHGD14 PLKMJMDIMABCDFGHJKLMN0.13 (0.005)D SUFFIXPLASTIC SOIC PACKAGECASE 751A–03ISSUE F–A–148NOTES:1.DIMENSIONING AND TOLERANCING PER ANSIY14.5M, 1982.2.CONTROLLING DIMENSION: MILLIMETER.3.DIMENSIONS A AND B DO NOT INCLUDEMOLD PROTRUSION.4.MAXIMUM MOLD PROTRUSION 0.15 (0.006)PER SIDE.5.DIMENSION D DOES NOT INCLUDE DAMBARPROTRUSION. ALLOWABLE DAMBARPROTRUSION SHALL BE 0.127 (0.005) TOTALIN EXCESS OF THE D DIMENSION ATMAXIMUM MATERIAL CONDITION.–B–17P7 PL0.25 (0.010)MBMGC–T–SEATINGPLANERX 45_FD14 PL0.25 (0.010)MKTBSMASJDIMABCDFGJKMPRMILLIMETERSINCHESMINMAXMINMAX8.558.750.3370.3443.804.000.1500.1571.351.750.0540.0680.350.490.0140.0190.401.250.0160.0491.27 BSC0.050 BSC0.190.250.0080.0090.100.250.0040.0090 7 0 7 ____5.806.200.2280.2440.250.500.0100.019http://onsemi.com6元器件交易网www.cecb2b.comMC14013BPACKAGE DIMENSIONSDT SUFFIXPLASTIC TSSOP PACKAGECASE 948G–01ISSUE O14X REFKNOTES:1.DIMENSIONING AND TOLERANCING PER ANSIY14.5M, 1982.2.CONTROLLING DIMENSION: MILLIMETER.3.DIMENSION A DOES NOT INCLUDE MOLDFLASH, PROTRUSIONS OR GATE BURRS. MOLDFLASH OR GATE BURRS SHALL NOT EXCEED0.15 (0.006) PER SIDE.4.DIMENSION B DOES NOT INCLUDEINTERLEAD FLASH OR PROTRUSION.INTERLEAD FLASH OR PROTRUSION SHALL NOTEXCEED0.25 (0.010) PER SIDE.5.DIMENSION K DOES NOT INCLUDE DAMBARPROTRUSION. ALLOWABLE DAMBARPROTRUSION SHALL BE 0.08 (0.003) TOTAL INEXCESS OF THE K DIMENSION AT MAXIMUMMATERIAL CONDITION.6.TERMINAL NUMBERS ARE SHOWN FORREFERENCE ONLY.7.DIMENSION A AND B ARE TO BEDETERMINED AT DATUM PLANE –W–.MILLIMETERSINCHESDIMMINMAXMINMAXA4.905.100.1930.200B4.304.500.1690.177C–––1.20–––0.047D0.050.150.0020.006F0.500.750.0200.030G0.65 BSC0.026 BSCH0.500.600.0200.024J0.090.200.0040.008J10.090.160.0040.006K0.190.300.0070.012K10.190.250.0070.010L6.40 BSC0.252 BSCM0 8 0 8 ____0.10 (0.004)0.15 (0.006)TUSMTUSVSN2XL/21480.25 (0.010)MLPIN 1IDENT.17B–U–NFDETAIL EKK1JJ10.15 (0.006)TUSA–V–SECTION N–N–W–C0.10 (0.004)–T–SEATINGPLANEDGHDETAIL EF SUFFIXPLASTIC EIAJ SOIC PACKAGECASE 965–01ISSUE O148LEQ1EHEM_LDETAIL P17ZDeAVIEW PNOTES:1.DIMENSIONING AND TOLERANCING PER ANSIY14.5M, 1982.2.CONTROLLING DIMENSION: MILLIMETER.3.DIMENSIONS D AND E DO NOT INCLUDEMOLD FLASH OR PROTRUSIONS AND AREMEASURED AT THE PARTING LINE. MOLD FLASHOR PROTRUSIONS SHALL NOT EXCEED 0.15(0.006) PER SIDE.4.TERMINAL NUMBERS ARE SHOWN FORREFERENCE ONLY.5.THE LEAD WIDTH DIMENSION (b) DOES NOTINCLUDE DAMBAR PROTRUSION. ALLOWABLEDAMBAR PROTRUSION SHALL BE 0.08 (0.003)TOTAL IN EXCESS OF THE LEAD WIDTHDIMENSION AT MAXIMUM MATERIAL CONDITION.DAMBAR CANNOT BE LOCATED ON THE LOWERRADIUS OR THE FOOT. MINIMUM SPACEBETWEEN PROTRUSIONS AND ADJACENT LEADTO BE 0.46 ( 0.018).DIMAA1bcDEeHE0.50LEMQ1ZMILLIMETERSMINMAX–––2.050.050.200.350.500.180.279.9010.505.105.451.27 BSC7.408.200.500.851.101.500 _10 _0.700.90–––1.42INCHESMINMAX–––0.0810.0020.0080.0140.0200.0070.0110.3900.4130.2010.2150.050 BSC0.2910.3230.0200.0330.0430.0590 _10 _0.0280.035–––0.056cb0.13 (0.005)MA10.10 (0.004)http://onsemi.com7元器件交易网www.cecb2b.com
MC14013B
ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changeswithout further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particularpurpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability,including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/orspecifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must bevalidated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others.SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applicationsintended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury ordeath may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and holdSCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonableattorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claimalleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer.
PUBLICATION ORDERING INFORMATION
CENTRAL/SOUTH AMERICA:
Spanish Phone:303–308–7143 (Mon–Fri 8:00am to 5:00pm MST)
Email:ONlit–spanish@hibbertco.comASIA/PACIFIC: LDC for ON Semiconductor – Asia Support
Phone:303–675–2121 (Tue–Fri 9:00am to 1:00pm, Hong Kong Time)
Toll Free from Hong Kong & Singapore:001–800–4422–3781
Email: ONlit–asia@hibbertco.com
JAPAN: ON Semiconductor, Japan Customer Focus Center
4–32–1 Nishi–Gotanda, Shinagawa–ku, Tokyo, Japan 141–8549Phone: 81–3–5740–2745Email: r14525@onsemi.com
ON Semiconductor Website: http://onsemi.comFor additional information, please contact your localSales Representative.http://onsemi.com8MC14013B/D