12−Stage Binary RippleCounter
The MC74AC4040 consists of 12 master-slave flip-flops. Theoutput of each flip-flop feeds the next and the frequency at each outputis half that of the preceding one. The state of the counter advances onthe negative-going edge of the Clock input. Reset is asynchronous andactive-high.
State changes of the Q outputs do not occur simultaneously becauseof internal ripple delays. Therefore, decoded output signals are subjectto decoding spikes and may have to be gated with the Clock of theMC74AC4040 for some designs.
Features
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161PDIP−16N SUFFIXCASE 648•••••
140 MHz Typ. Clock
Outputs Source/Sink 24 mA
Operating Voltage Range: 2.0 to 6.0 VHigh Noise Immunity
Pb−Free Packages are Available
VCC16Q1115Q1014Q813Q912RESETCLK1110Q19161SOIC−16D SUFFIXCASE 751B161SOEIAJ−16M SUFFIXCASE 966ORDERING INFORMATION
DeviceMC74AC4040N
1Q12
2Q6
3Q5
4Q7
5Q4
6Q3
7Q2
8GND
MC74AC4040NGMC74AC4040DMC74AC4040DGMC74AC4040DR2
Output StateNo ChangeAdvance to next stateAll Outputs are lowMC74AC4040MMC74AC4040DR2G
PackagePDIP−16PDIP−16(Pb−Free)SOIC−16SOIC−16(Pb−Free)SOIC−16
Shipping†25 Units/Rail25 Units/Rail48 Units/Rail48 Units/Rail2500 Tape & Reel
Figure 1. Pinout: 16−Lead Packages Conductors
(Top View)FUNCTION TABLEClockResetLLXHSOIC−162500 Tape & Reel(Pb−Free)SOEIAJ−16
50 Units/Rail
†For information on tape and reel specifications,including part orientation and tape sizes, pleaserefer to our Tape and Reel Packaging SpecificationsBrochure, BRD8011/D.
DEVICE MARKING INFORMATION
See general marking information in the device markingsection on page 4 of this data sheet.
© Semiconductor Components Industries, LLC, 20061
November, 2006 − Rev. 7
Publication Order Number:
MC74AC4040/D
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MC74AC4040
9765CLOCK10324131214151RESET11Q1Q2Q3Q4Q5Q6Q7Q8Q9Q10Q11Q12
PIN 16 = VCCPIN 8 = GND
Figure 2. Logic Diagram
MAXIMUM RATINGS
SymbolVCCVINVOUTIINIOUTICCPD
DC Supply Voltage (Referenced to GND)DC Input Voltage (Referenced to GND)DC Output Voltage (Referenced to GND)DC Input Current, per PinDC Output Current, per Pin
DC VCC or GND Current per Output PinPower Dissipation in Still Air
Plastic{
SOIC Package{Storage Temperature
Lead Temperature, 1 mm from Case for 10 seconds(Plastic DIP or SOIC Package)
Parameter
Value−0.5 to +7.0−0.5 to VCC +0.5−0.5 to VCC +0.5
±20±50±50750500−65 to +150
260
°C°CUnitVVVmAmAmAmW
TstgTL
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above theRecommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affectdevice reliability.
†Derating: Plastic DIP: − 10mW/°C from 65°C to 125°C SOIC Package: −7.0 mW/°C from 65°C to 125°C
RECOMMENDED OPERATING CONDITIONS
SymbolVCCVIN/VOUTTAtr/tf
DC Supply Voltage (Referenced to GND)
Input Voltage, Output Voltage (Referenced to GND)Operating Temperature, All Package TypesInput Rise/Fall Time(Figure 1)
VCC = 3.0 VVCC = 4.5 VVCC = 5.5 V
Parameter
Min2.00−40000
Max6.0VCC+851504025
UnitV−°Cns/V
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MC74AC4040
DC CHARACTERISTICS (unless otherwise specified)
SymbolICC
Parameter
Maximum Quiescent Supply Voltage
Value80
UnitmA
Vin = VCC or GND
VCC = 5.5 V, TA = Worst CaseVin = VCC or GNDVCC = 5.5 V, TA = 25°C
ICC
Maximum Quiescent Supply Current8.0mA
DC CHARACTERISTICS
74AC
VCC
SymbolVIH
Parameter
Minimum High Level Input Voltage
(V)3.04.55.53.04.55.53.04.55.53.04.55.5
VOL
Maximum Low Level Output Voltage
3.04.55.53.04.55.5
IINIOLDIOHD
Maximum Input Leakage CurrentMinimum Dynamic Output Current{
5.55.55.5
TA = +25°CTyp−−−−−−2.994.495.49−−−0.0020.0010.001−−−−−−
74AC
TA = −40°C to +85°CGuaranteed Limits2.13.153.850.91.351.652.94.45.42.563.864.860.10.10.10.360.360.36±0.1−−
2.13.153.850.91.351.652.94.45.42.463.764.760.10.10.10.440.440.44±1.075−75
UnitV
ConditionsVOUT = 0.1 Vor VCC − 0.1 VVOUT = 0.1 Vor VCC − 0.1 VIOUT = −50 mA
V
*VIN = VIL or VIH
−12 mA
IOH−24 mA
−24 mAIOUT = 50 mA
V
*VIN = VIL or VIH
12 mA
IOL24 mA
24 mAVI = VCC, GNDVOLD = 1.65 V MaxVOHD = 3.85 V Min
VIL
Maximum Low Level Input Voltage
V
VOH
Minimum High Level Output Voltage
V
V
mAmAmA
*All outputs loaded; thresholds on input associated with output under test.†Maximum test duration 2.0 ms, one output loaded at a time.
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MC74AC4040
AC CHARACTERISTICS (For Figures and Waveforms − See Section 3 of the ON Semiconductor FACT Data Book, DL138/D)
74ACTA = +25°C
VCC*
SymbolfmaxnCP to Q1Qn to Qn +1MR to QtHL
trec
nCP to MRtw nCPtw MR
Parameter
Maximum ClockFrequencyPropagation DelaynCP to Q1Propagation DelayQn to Qn +1Propagation DelayMR to QRecovery TimeMinimum Pulse WidthClock Pin
Minimum Pulse WidthMaster Reset
(V)3.35.03.35.03.35.03.35.03.35.03.35.03.33.0
Min1101302.02.0003.03.0004.03.04.03.0
CL = 50 pF
Typ120140−−−−−−−2.5−1.53.52.53.52.5
Max−−118.05.53.51210−−−−−−
74AC
TA = −40°C to +85°C
CL = 50 pFMin1001202.02.0003.03.0004.53.54.53.5
Max−−14106.54.51512−−−−−−
UnitMHznsnsnsnsnsns
Fig. No.
−−−−−−−
*Voltage Range 3.3 V is 3.3 V ±0.3 V.*Voltage Range 5.0 V is 5.0 V ±0.5 V.
CAPACITANCE
SymbolCINCPD
Input Capacitance
Power Dissipation Capacitance
Parameter
ValueTyp4.550
UnitpFpF
Test ConditionsVCC = 5.0 VVCC = 5.0 V
MARKING DIAGRAMS
PDIP−16MC74AC4040NAWLYYWWG
SOIC−16AC4040GAWLYWW
SOEIAJ−16
74AC4040ALYW
AWL, LYY, YWW, WG= Assembly Location= Wafer Lot= Year
= Work Week
= Pb−Free Package
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MC74AC4040
PACKAGE DIMENSIONS
PDIP−16CASE 648−08ISSUE T
−A−169NOTES:
1.DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2.CONTROLLING DIMENSION: INCH.3.DIMENSION L TO CENTER OF LEADS
WHEN FORMED PARALLEL.
4.DIMENSION B DOES NOT INCLUDE
MOLD FLASH.
5.ROUNDED CORNERS OPTIONAL.
B18FSCL−T−HKGD16 PLSEATINGPLANEJTAMM
0.25 (0.010)MDIMABCDFGHJKLMS
INCHESMINMAX0.7400.7700.2500.2700.1450.1750.0150.0210.0400.700.100 BSC0.050 BSC0.0080.0150.1100.1300.2950.3050 _10 _0.0200.040MILLIMETERSMINMAX18.8019.556.356.853.694.440.390.531.021.772.54 BSC1.27 BSC0.210.382.803.307.507.740 _10 _0.511.01
STYLE 1:
PIN 1.CATHODE
2.CATHODE3.CATHODE4.CATHODE5.CATHODE6.CATHODE7.CATHODE8.CATHODE9.ANODE10.ANODE11.ANODE12.ANODE13.ANODE14.ANODE15.ANODE16.ANODESTYLE 2:
PIN 1.COMMON DRAIN
2.COMMON DRAIN3.COMMON DRAIN4.COMMON DRAIN5.COMMON DRAIN6.COMMON DRAIN7.COMMON DRAIN8.COMMON DRAIN9.GATE10.SOURCE11.GATE12.SOURCE13.GATE14.SOURCE15.GATE16.SOURCE
SOIC
CASE 751B−05
ISSUE J
−A−169NOTES:
1.DIMENSIONING AND TOLERANCING PER ANSIY14.5M, 1982.
2.CONTROLLING DIMENSION: MILLIMETER.3.DIMENSIONS A AND B DO NOT INCLUDEMOLD PROTRUSION.
4.MAXIMUM MOLD PROTRUSION 0.15 (0.006)PER SIDE.
5.DIMENSION D DOES NOT INCLUDE DAMBARPROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTALIN EXCESS OF THE D DIMENSION ATMAXIMUM MATERIAL CONDITION.
DIMABCDFGJKMPRMILLIMETERSMINMAX9.8010.003.804.001.351.750.350.490.401.251.27 BSC0.190.250.100.250 7 __5.806.200.250.50INCHESMINMAX0.3860.3930.1500.1570.0540.0680.0140.0190.0160.0490.050 BSC0.0080.0090.0040.0090 7 __0.2290.2440.0100.019−B−18P8 PL0.25 (0.010)MBSGFKC−T−SEATINGPLANERX 45_MD16 PLMJ0.25 (0.010)TB
SA
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MC74AC4040
PACKAGE DIMENSIONS
SOEIAJ−16CASE 966−01ISSUE A
169LEQ1EHEM_LDETAIL P18ZDeAVIEW PNOTES:
1.DIMENSIONING AND TOLERANCING PER ANSIY14.5M, 1982.
2.CONTROLLING DIMENSION: MILLIMETER.3.DIMENSIONS D AND E DO NOT INCLUDE MOLDFLASH OR PROTRUSIONS AND ARE MEASUREDAT THE PARTING LINE. MOLD FLASH ORPROTRUSIONS SHALL NOT EXCEED 0.15 (0.006)PER SIDE.4.TERMINAL NUMBERS ARE SHOWN FORREFERENCE ONLY.5.THE LEAD WIDTH DIMENSION (b) DOES NOTINCLUDE DAMBAR PROTRUSION. ALLOWABLEDAMBAR PROTRUSION SHALL BE 0.08 (0.003)TOTAL IN EXCESS OF THE LEAD WIDTHDIMENSION AT MAXIMUM MATERIAL CONDITION.DAMBAR CANNOT BE LOCATED ON THE LOWERRADIUS OR THE FOOT. MINIMUM SPACEBETWEEN PROTRUSIONS AND ADJACENT LEADTO BE 0.46 ( 0.018).cb0.13 (0.005)MA10.10 (0.004)DIMAA1bcDEeHELLEMQ1ZMILLIMETERSMINMAX−−−2.050.050.200.350.500.100.209.9010.505.105.451.27 BSC7.408.200.500.851.101.500 _10 _0.700.90−−−0.78INCHESMINMAX−−−0.0810.0020.0080.0140.0200.0070.0110.3900.4130.2010.2150.050 BSC0.2910.3230.0200.0330.0430.0590 _10 _0.0280.035−−−0.031ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liabilityarising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. Alloperating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rightsnor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applicationsintended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. ShouldBuyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or deathassociated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an EqualOpportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
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