FUJITSU SEMICONDUCTOR
DATA SHEET
DS07-13741-2E
16-bit Proprietary Microcontroller
CMOS
F2MC-16LX MB90945 Series
MB90F946A/947A/F947/F947A/F949/F949A/V390HA/V390HB
■DESCRIPTION
The MB90945 series with one FULL-CAN* interface and FLASH ROM is especially designed for automotive HVACapplications. Its main feature is the on board CAN* Interface, which conform to V2.0 Part A and Part B, whilesupporting a very flexible message buffer scheme and so offering more functions than a normal FULL-CAN*approach. With the new 0.35 µm CMOS technology, Fujitsu now offers on-chip FLASH-ROM program memoryup to 384 K bytes. An internal voltage booster removes the necessity for a second programming voltage. An on board voltage regulator provides 3 V to the internal MCU core. This creates a major advantage in termsof EMI and power consumption.
The internal PLL clock frequency multiplier provides an internal 42 ns instruction cycle time from an external 4 MHz clock.
The unit features a 4-channel Output Compare Unit and a 6-channel Input Capture Unit with two separate 16-bitfree running timers. Up to 3 UARTs, one Serial I/O and one I2C constitute additional functionality for communicationpurposes.
* : Controller Area Network (CAN) - License of Robert Bosch GmbH
■PACKAGE 100-pin Plastic QFP (FPT-100P-M06) 元器件交易网www.cecb2b.com
MB90945 Series
■FEATURES
••••••••••••••••••••••••
16-bit core CPU; 4 MHz external clock (24 MHz internal, 42 ns instr. cycle time) New 0.35 µm CMOS Process Technology
Internal voltage regulator supports 3 V MCU core, offering low EMI and low power consumption figures
One FULL-CAN interface; conforming to Version 2.0 Part A and Part B, flexible message buffering (mailboxand FIFO buffering can be mixed)
Powerful interrupt functions (8 progr. priority levels; 8 external interrupts)
EI2OS - Automatic transfer function independant of CPU; 16 channels of intelligent I/O Services18-bit Time-base counterWatchdog Timer
1 full duplex UART; support 10.4 KBaud (USA standard) up to 2 full duplex UARTs (LIN/SCI/SPI) 1 Serial I/O (SPI) 1I2C interface
A/D Converter : 15 channels analog inputs (Resolution 10-bit or 8-bit)
16-bit reload timer × 1channel
ICU (Input capture) 16-bit × 6 channelsOCU (Output compare) 16-bit × 4 channels
16-bit free running timer × 2 channels (FRT0 : ICU 0/1, OCU 0/1/2/3, FRT1 : ICU 2/3/4/5) 8/16-bit Programmable Pulse Generator 6 channels × 8/16-bit
Optimized instruction set for controller applications (bit, byte, word and long-word data types; 23 differentaddressing modes; barrel shift; variety of pointers) 4-byte instruction execution queue
signed multiply (16-bit × 16-bit) and divide (32-bit/16-bit) instructions availableProgram Patch Function (3 address match registers) Fast Interrupt processing
Low Power Consumption modeSleep mode
Timebase timer modeStop mode
CPU intermittent modeAutomotive input levels
Package : 100-pin plastic QFP
••
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MB90945 Series
■PRODUCT LINEUP
Part Number
MB90947A
ParameterCPUSystem clock
MB90F946A
MB90F947, MB90F947A MB90F949, MB90F949A
MB90V390HA MB90V390HB
F2MC-16LX CPU
On-chip PLL clock multiplier (×1, ×2, ×3, ×4, ×6, 1/2 when PLL stops)
Minimum instruction execution time : 42 ns (4 MHz oscillation clock, PLL clock
multiplied by 6)
Boot-blockFlash memory384 Kbytes
Boot-blockFlash memory
256 Kbytes: MB90F949
MB90F949A
128 Kbytes: MB90F947
MB90F947A12 Kbytes: MB90F949
MB90F949A
6 Kbytes: MB90F947
MB90F947A
ROM
ROM memory128 Kbytes
External
RAM
Emulator-specific power supply*1Technology
6 Kbytes16 Kbytes30 Kbytes
⎯
0.35 µm CMOS with on-chip voltage regulator for internal power supply
0.35 µm CMOS with on-chip voltage regulator for internal power supply + Flash memory with on-chip charge pump for programming voltage
Yes
0.35 µm CMOS with on-chip voltage
regulator for internal power supply
5 V ± 10%
⎯PGA-299C2 channels
Operating voltage rangeTemperature rangePackage
3.5 V to 5.5 V : other than conditions listed below4.0 V to 5.5 V : when writing to Flash4.5 V to 5.5 V : if A/D Converter is used
−40 °C to +105 °C
QFP-100P1 channel
UART
Full duplex double buffer
Supports asynchronous/synchronous (with start/stop bit) transfer
Baud rate : 4808/9615/10417/19230/38460/62500/500000 bps (asynchronous)
500 K/1 M/2 Mbps (synchronous) at System clock = 20 MHz
1 channel
2 channels
1 channel
2 channels
UART
(LIN/SCI/SPI)
Serial I/O
1 channel
Transfer can be started from MSB or LSB
Supports internal clock synchronized transfer and external clock synchronized transferSupports positive-edge and negative-edge clock synchronization
Baud rate : 31.25 K/62.5 K/125 K/500 K/1 Mbps at System clock = 20 MHz
1 channel
(Continued)
I2C (400 Kbps)
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MB90945 Series
Part Number
MB90947A
Parameter
MB90F946A
MB90F947, MB90F947A MB90F949, MB90F949AMB90V390HA MB90V390HB
10-bit or 8-bit resolution
A/D Converter
Conversion time : Min 4.9 µs includes sample time (per one channel, only at certain
(15 input channels)
machine clock frequencies)
1 channel
2 channels
16-bit Reload TimerOperation clock frequency : fsys/21, fsys/23, fsys/25 (fsys = System clock frequency)
Supports External Event Count function16-bit I/O Timer (2 channels)
Signals an interrupt when overflowing
Supports Timer Clear when a match with Output Compare (ch0)
Operation clock freq. : fsys, fsys/21, fsys/22, fsys/23, fsys/24, fsys/25, fsys/26, fsys/27 (fsys = System clock freq.)
I/O Timer 0 (clock input FRCK0) corresponds to ICU 0/1, OCU 0/1/2/3I/O Timer 1 (clock input FRCK1) corresponds to ICU 2/3/4/5Rising edge, falling edge or rising & falling edge sensitiveSix 16-bit Capture registers
Signals an interrupt upon external event
⎯4 channels
16-bit
Output Compare
Signals an interrupt when a match with 16-bit I/O TimerEight 16-bit compare registers.
A pair of compare registers can be used to generate an output signal.
⎯
ICU 3/5 inputs are shared with OCU 6/7
outputsICU 3/5 inputs are shared with OCU 6/7
outputs
8 channels
16-bit
Input Capture (6 channels)
8/16-bit
Programmable Pulse Generator (6 channels)
Supports 8-bit and 16-bit operation modesTwelve 8-bit reload counters
Twelve 8-bit reload registers for L pulse widthTwelve 8-bit reload registers for H pulse width
A pair of 8-bit reload counters can be configured as one 16-bit reload counter or as 8-bit prescaler plus 8-bit reload counter
Operation clock freq. : fsys, fsys/21, fsys/22, fsys/23, fsys/24 or 102.4 µs (fosc = 5 MHz) (fsys = System clock frequency, fosc = Oscillation clock frequency)
1 channel
5 channels
Conforms to CAN Specification Version 2.0 Part A and BAutomatic re-transmission in case of error
Automatic transmission responding to Remote FramePrioritized 16 message buffers for data and ID’sSupports multiple messages
Flexible configuration of acceptance filtering :
Full-bit compare/Full-bit mask/Two partial bit masksSupports up to 1 Mbps
MB90F947/F949/V390HA: Do not use clock modulation and CAN at the same time
(Continued)
CAN Interface
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MB90945 Series
Part Number
MB90947A
ParameterExternal Interrupt (8 channels) Stepping motor controllerWatch TimerSound generatorMachine clock out-put
Program patch function
MB90F946A
MB90F947, MB90F947A MB90F949, MB90F949AMB90V390HA MB90V390HB
Can be programmed edge sensitive or level sensitive
⎯⎯⎯⎯
3 address match registers
Virtually all external pins can be used as general purpose I/OAll push-pull outputs
Bit-wise programmable as input/output or peripheral signal
2 channels1 channel1 channel2 channels
(non-inverted and in-verted) 5 address match
registers
I/O Ports
Port-wise program-Automotive input level (P21/RX1, P42/SDA, P43/SCL have CMOS mable as Automotive Schmitt input level) (default) or CMOS
Schmitt input level
All ports except P42, P43
P42, P43
⎯
All ports except P80, P81, PA0 to PA7, P42, P43
P42, P43P80, P81, PA0 to PA7
Phase modulation mode
Frequency and phase
modulation mode
I/O Ports with 4 mA CMOS outputI/O Ports with 3 mA CMOS outputI/O Ports with 30 mA CMOS output with slewrate control
Clock Modulator
Phase modulation mode
MB90F947/F949/V390HA:
Do not use clock modulation and CAN at the same time
Reduces EMI by modulating the PLL clock
Start-up time at power-on reset
218 oscillation cycles (65.536 ms at 4 MHz
3 × 216 oscillation cycles (49.152 ms at 4 MHz oscillation) + oscilla-oscillation) +
tion time of oscillator*2
oscillation time of os-cillator*2
(Continued)
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MB90945 Series
(Continued)
Part Number
MB90947A
Parameter
MB90F946A
MB90F947, MB90F947A MB90F949, MB90F949A
MB90V390HA MB90V390HB
FlashMemory
⎯
Supports automatic programming, Embedded AlgorithmTM*3
Write/Erase/Erase-Suspend/Resume com-mands
A flag indicating completion of the algorithmNumber of erase cycles : 10,000 timesData retention time : 20 years*4
Hard-wired reset vector available in order to point to a fixed boot sector in Flash Memory (address FFA000H, mode data 00H) Boot block configuration
Erase can be performed on each block
Block protection with external programming voltage
Write and erase at Fmax = 20 MHz
⎯
*1 : It is setting of Jumper switch SI when Emulation Pod (MB2147) is used.
Please refer to the Emulator hardware manual about details.*2 : Oscillation time of the oscillator is the time that the amplitude reaches 90%.*3 : Embedded Algorithm is a trade mark of Advanced Micro Devices Inc.
*4 : Data is based on reliability tests during process qualification (the value for TA = + 85 °C is calculated via
the Arrenhius formula from data of accelerated measurements at elevated temperature) .
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MB90945 Series
■PIN ASSIGNMENTS
•MB90947A/F946A/F947/F947A/F949/F949A (TOP VIEW) P23/INT3P22/INT2P21/RX1P20/TX1P17P16P15/TOT0X0X1VssVccP14/TIN0P13P12P11/OUT3P10/OUT2P07/OUT1P06/OUT0P05/IN5P04/IN4P24/INT4P25/INT5P26/INT6P27/INT7P30P31P32P33P34/SOT0P35/SCK0P36/SIN0P37P44P45/ADTGVccVssCP40P41P42/SDAP43/SCLP46/INT0P47/INT1P50/PPG10PB0/PPG02/AN8PB1/PPG03/AN9PB2/PPG04/AN10PB3/PPG05/AN11PB4/SIN4/AN12PB5/SCK4/AN1312345678910111213141516171819202122232425262728293010099989796959493929190898887868584838281PB6/SOT4/AN14AVccAVRHAVRLAVssP60/AN0P61/AN1P62/AN2P63/AN3P64/AN4P65/AN5P66/AN6P67/AN7VssP51/PPG11P52/PPG12P53/PPG13P54/PPG14PB7/FRCK0P97/FRCK13132333435363738394041424344454647484950807978777675747372717069686766656463626160595857565554535251P03/IN3P02/IN2P01/IN1P00/IN0P81P80PA7PA6PA5PA4PA3PA2PA1PA0VssVccP96P92P91P94/SCK3P95/SOT3P93/SIN3P90P57/PPG01P56/PPG00P55/PPG15RSTMD0MD1MD2 (FPT-100P-M06) 7
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MB90945 Series
•MB90V390HA/V390HB (TOP VIEW) P23/INT3P22/INT2P21/RX1P20/TX1P17/SGAP16/SGOP15/TOT0X0X1VssVccP14/TIN0P13/OUT5P12/OUT4P11/OUT3P10/OUT2P07/OUT1P06/OUT0P05/IN5/OUT7P04/IN4P24/INT4P25/INT5P26/INT6P27/INT7P30/RX0P31/TX0P32/TIN1P33/TOT1P34/SOT0P35/SCK0P36/SIN0P37/SIN1P44P45/ADTGVccVssCP40/SCK1P41/SOT1P42/SDAP43/SCLP46/INT0P47/INT1P50/PPG10PB0/PPG02/TX3/AN8PB1/PPG03/RX3/AN9PB2/PPG04/TX4/AN10PB3/PPG05/RX4/AN11PB4/SIN4/AN12PB5/SCK4/AN13100999897969594939291908988878685848382811234567891011121314151617181920212223242526272829308079787776757473727170696867666564636261605958575655545352518
PB6/SOT4/AN14AVccAVRHAVRLAVssP60/AN0P61/AN1P62/AN2P63/AN3P64/AN4P65/AN5P66/AN6P67/AN7VssP51/PPG11P52/PPG12P53/PPG13P54/PPG14PB7/FRCK0/HCLKP97/FRCK1/HCLKX3132333435363738394041424344454647484950P03/IN3/OUT6P02/IN2P01/IN1P00/IN0P81P80PA7/PWM2M5PA6/PWM2P5PA5/PWM1M5PA4PWM1P5PA3/PWM2M4PA2/PWM2P4PA1/PWM1M4PA0/PWM1P4DVssDVccP96/WOTP92/SOT2P91/SCK2P94/SCK3P95/SOT3P93/SIN3P90/SIN2P57/PPG01/TX2P56/PPG00/RX2P55/PPG15RSTMD0MD1MD2 (FPT-100P-M06) As seen with QFP100 probe cable元器件交易网www.cecb2b.com
MB90945 Series
■PIN DESCRIPTION
Pin no.92935477 to 82
Pin name
X1X0RSTP00 to P05IN0 to IN5P06, P07P10, P11OUT0 to OUT3
87, 88899495, 96979899, 1001 to 45 to 89101112131418, 1920
P12, P13P14TIN0P15TOT0P16, P17P20TX1P21RX1P22 to P27INT2 to INT7P30 to P33
P34SOT0P35SCK0P36SIN0P37P44P45ADTGP40, P41P42SDA
DDDDDFDDDDDDDDDFCircuit type
ABD
Pin for oscillationPin for oscillationReset input
General purpose I/O
Inputs for the Input Captures 0-5General purpose I/O
Outputs for the Output ComparesGeneral purpose I/OGeneral purpose I/O
TIN0 input for the 16-bit Reload Timer 0General purpose I/O
TOT0 output for the 16-bit Reload Timer 0General purpose I/OGeneral purpose I/O
TX output for CAN Interface 1General purpose I/ORX input for CAN Interface 1General purpose I/O
External interrupt inputs for INT2 to INT7General purpose I/OGeneral purpose I/OSOT output for UART0General purpose I/OSCK input/output for UART0General purpose I/OSIN input for UART0General purpose I/OGeneral purpose I/OGeneral purpose I/O
External trigger input of the A/D ConverterGeneral purpose I/OGeneral purpose I/OSerial data for I2C interface
(Continued)
Function
83 to 86D
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MB90945 Series
Pin no.2122, 2324
Pin nameP43SCLP46, P47INT0, INT1
P50PPG10PB0 to PB3PPG02 to PPG05AN8 to AN11
PB4
Circuit type
FDD
General purpose I/O
Function
Serial clock for I2C interfaceGeneral purpose I/O
External interrupt inputs for INT0, INT1General purpose I/OOutput for the PPG1General purpose I/OOutputs for the PPG4, 6, 8, AInputs for the A/D ConverterGeneral purpose I/O
25 to 28E
29SIN4AN12PB5
ESIN input for Serial I/OInput for the A/D ConverterGeneral purpose I/O
30SCK4AN13PB6
ESCK input/output for Serial I/OInput for the A/D ConverterGeneral purpose I/O
31SOT4AN14P60 to P67AN0 to AN7P51 to P54PPG11 to PPG14
PB7FRCK0P97FRCK1P55PPG15P56, P57PPG00, PPG01
P90
ESOT output for Serial I/OInput for the A/D ConverterGeneral purpose I/OInputs for the A/D ConverterGeneral purpose I/OOutputs for the PPG3, 5, 7, 9General purpose I/O
FRCK0 input for the 16-bit I/O Timer 0General purpose I/O
FRCK1 input for the 16-bit I/O Timer 1General purpose I/OOutputs for the PPGBGeneral purpose I/OOutputs for the PPG0, PPG2General purpose I/O
SIN input for UART 2 (LIN/SCI/SPI) (only MB90V390HA, MB90V390HB and MB90F946A)General purpose I/O
SIN input for UART3 (LIN/SCI/SPI)
(Continued)
36 to 4345 to 4849505556, 57
EDDDDD
58
SIN2P93SIN3
D
59D
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MB90945 Series
(Continued)Pin no.
6061
Pin nameP95SOT3P94SCK3P91
Circuit type
DD
General purpose I/O
Function
SOT output for UART3 (LIN/SCI/SPI) General purpose I/O
SCK input/output for UART3 (LIN/SCI/SPI) General purpose I/O
SCK input/output for UART 2 (LIN/SCI/SPI) (only MB90V390HA, MB90V390HB and MB90F946A)General purpose I/O
SOT output for UART 2 (LIN/SCI/SPI) (only MB90V390HA, MB90V390HB and MB90F946A)General purpose I/O
General purpose I/O. For the EVA device, these pins are high current outputs.
General purpose I/O. For the EVA device, these pins are high current outputs.
Dedicated power supply pin (5 V) for the A/D converterDedicated pos. reference voltage pin for the A/D converterDedicated neg. reference voltage pin for the A/D converterDedicated power supply pin (0 V) for the A/D converter
These are input pins used to designate the operating mode. They should be connected directly to VCC or VSS.
This is an input pin used to designate the operating mode. It should be connected directly to VCC or VSS.
These are power supply (5 V) input pins. For the EVA device, pin 65 is the DVCC supply pin for the high current outputs.
These are power supply (0 V) input pins. For the EVA device, pin 66 is the DVSS supply pin for the high current outputs.
This is the power supply stabilization capacitor pin. It should be connected to higher than or equal to 0.1 µF ceramic capacitor.
62
SCK2P92
D
636467 to 7475, 763233343552, 53511565901644669117
SOT2P96PA0 to PA7P80, P81AVCCAVRHAVRLAVssMD1, MD0MD2Vcc
DDHH⎯⎯⎯⎯CG⎯
Vss⎯
C⎯
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MB90945 Series
■I/O CIRCUIT TYPE
TypeX1Clock inputPchNchCircuitRemarks•Oscillation feedback resistor : 1 MΩ approx.X0AStandby control signalVCCBR (pull-up)RCMOS Hysteresis•CMOS Hysteresis input with pull-upresistor : 50 kΩ approx.CRCMOS Hysteresis•EVA/ROM device : CMOS Hysteresis input •Flash device : CMOS input.•CMOS output (4 mA) •Automotive Hysteresis inputVCCPchDNchAutomotive HysteresisR(Continued)
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MB90945 Series
(Continued) TypeVCCPchCircuitRemarks•CMOS output (4 mA) •Automotive Hysteresis input•Analog inputNchEPchAnalog inputNchRAutomotive HysteresisVCCPch•CMOS outputP42, P43 : 3mAP21 : 4 mA•CMOS Hysteresis inputFNchCMOS HysteresisRRCMOS HysteresisGR (pull-down)•EVA/ROM device : CMOS Hysteresis input with pull-down resistor : 50 kΩ approx.•Flash device : CMOS input without pull-down.VCCPchHNchAutomotive Hysteresis•EVA/ROM device : CMOS high current output (30 mA) with slewrate control•Flash device : CMOS output (4 mA) •Automotive Hysteresis inputR13
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MB90945 Series
■HANDLING DEVICES
Special care is required for the following when handling the device : •Preventing latch-up
•Stabilization of supply voltage•Treatment of unused pins•Using external clock
•Power supply pins (VCC/VSS) •Pull-up/pull-down resistors•Crystal Oscillator Circuit
•Turning-on Sequence of Power Supply to A/D Converter and Analog Inputs•Connection of Unused Pins of A/D Converter if A/D Converter is unused.•Caution on Operations during PLL Clock Mode
1.Preventing latch-up
CMOS IC chips may suffer latch-up under the following conditions :
•A voltage higher than VCC or lower than VSS is applied to an input or output pin.•A voltage higher than the rated voltage is applied between VCC and VSS.•The AVCC power supply is applied before the VCC voltage.
Latch-up may increase the power supply current drastically, causing thermal damage to the device.In using the devices, take sufficient care to avoid exceeding maximum ratings.
For the same reason, also be careful not to let the analog power-supply voltage (AVCC, AVRH) exceed the digitalpower-supply voltage.
2.Stabilization of supply voltage
A sudden change in the supply voltage may cause the device to malfunction even within the specified VCC supplyvoltage operation range. Therefore, the VCC supply voltage should be stabilized.
For reference, the supply voltage should be controlled so that VCC ripple variations (peak-to-peak values) atcommercial frequencies (50 Hz to 60 Hz) fall below 10 % of the standard VCC supply voltage and the coefficientof fluctuation does not exceed 0.1 V/ms at instantaneous power switching.
3.Treatment of unused pins
Leaving unused input pins open may result in misbehavior or latch up and possible permanent damage of thedevice. Therefore they must be pulled up or pulled down through resistors. In this case those resistors shouldbe more than 2 kΩ .
Unused bidirectional pins should be set to the output state and can be left open, or the input state with the abovedescribed connection.
4.Using external clock
To use external clock, drive the X0 pin and leave X1 pin open.MB90945 SeriesX0X114
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MB90945 Series
5.Power supply pins (VCC/VSS)
•If there are multiple VCC and VSS pins, from the point of view of device design, pins to be of the same potentialare connected the inside of the device to prevent such malfunctioning as latch up.
To reduce unnecessary radiation, prevent malfunctioning of the strobe signal due to the rise of ground level,and observe the standard for total output current, be sure to connect the VCC and VSS pins to the power supplyand ground externally.
•Connect VCC and VSS to the device from the current supply source at a low impedance.
•As a measure against power supply noise, connect a capacitor of about 0.1 µF as a bypass capacitor betweenVCC and VSS in the vicinity of VCC and VSS pins of the device.VCCVSSVCCVSSVCCMB90945SeriesVCCVSSVSSVCCVSS6.Pull-up/pull-down resistors
The MB90945 series does not support internal pull-up/pull-down resistors option. Use external componentswhere needed.
7.Crystal Oscillator Circuit
Noises around X0 or X1 pins may be possible causes of abnormal operations. Make sure to provide bypasscapacitors via shortest distance from X0, X1 pins, crystal oscillator (or ceramic oscillator) and ground lines, andmake sure, to the utmost effort, that lines of oscillation circuit not cross the lines of other circuits while you designa printed circuit.
It is highly recommended to provide a printed circuit board art work surrounding X0 and X1 pins with a groundarea for stabilizing the operation.
8.Turning-on Sequence of Power Supply to A/D Converter and Analog Inputs
Make sure to turn on the A/D converter power supply (AVCC, AVRH, AVRL) and analog inputs (AN0 to AN14)after turning-on the digital power supply (VCC) .
Turn-off the digital power after turning off the A/D converter supply and analog inputs. In this case, make surethat the voltage not exceed AVRH or AVCC (turning on/off the analog and digital power supplies simultaneouslyis acceptable) .
9.Connection of Unused Pins of A/D Converter if A/D Converter is unused
Connect unused pins of A/D converter to AVCC = VCC, AVSS = AVRH = AVRL = VSS.
10.Notes on During Operation of PLL Clock Mode
If the PLL clock mode is selected, the microcontroller attempt to be working with the self-oscillating circuit evenwhen there is no external oscillator or external clock input is stopped. Performance of this operation, however,cannot be guaranteed.
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MB90945 Series
■BLOCK DIAGRAMS
•MB90F946AX0, X1RSTClockControllerwith PhaseModulatorF2MC-16LXCPUIO Timer 0FRCK0RAM 16 K bytesInputCapture6 channelsOutputCompare4 channelsIO Timer 1IN5 to IN0Flash384 K bytesOUT3 to OUT0PrescalerFRCK1SOT0SCK0SIN0Prescaler x2UART08/16-bitPPG6 channelsPPG15 to PPG10PPG05 to PPG00Internal data busCANInterface 1RX1TX1SOT2/3SCK2/3SIN2/3UART2/3(LIN/SCI/SPI)ExternalInterruptINT7 to INT0PrescalerSOT4SCK4SIN4AVCCAVSSAN [14:0]AVRHAVRLADTG10-bit A/D Converter 15 input channelSerial I/OI2CInterfaceSDASCL16-bit Reload Timer1 channelTIN0TOT016
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MB90945 Series
•MB90947AX0, X1RSTClockControllerwith PhaseModulatorF2MC-16LXCPUIO Timer 0FRCK0RAM 6 K bytesInputCapture6 channelsOutputCompare4 channelsIO Timer 1IN5 to IN0ROM128 K bytesOUT3 to OUT0PrescalerFRCK1SOT0SCK0SIN0PrescalerUART08/16-bitPPG6 channelsPPG15 to PPG10PPG05 to PPG00Internal data busCANInterface 1RX1TX1SOT3SCK3SIN3UART3(LIN/SCI/SPI)ExternalInterruptINT7 to INT0PrescalerSOT4SCK4SIN4AVCCAVSSAN [14:0]AVRHAVRLADTG10-bit A/D Converter 15 input channelSerial I/OI2CInterfaceSDASCL16-bit Reload Timer1 channelTIN0TOT017
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MB90945 Series
•MB90F947, MB90F947AX0, X1RSTClockControllerwith PhaseModulatorF2MC-16LXCPUIO Timer 0FRCK0RAM 6 K bytesInputCapture6 channelsOutputCompare4 channelsIO Timer 1IN5 to IN0Flash128 K bytesOUT3 to OUT0PrescalerFRCK1SOT0SCK0SIN0PrescalerUART08/16-bitPPG6 channelsPPG15 to PPG10PPG05 to PPG00Internal data busCANInterface 1RX1TX1SOT3SCK3SIN3UART3(LIN/SCI/SPI)ExternalInterruptINT7 to INT0PrescalerSOT4SCK4SIN4AVCCAVSSAN14 to AN0AVRHAVRLADTG10-bit A/D Converter 15 input channelSerial I/OI2CInterfaceSDASCL16-bit Reload Timer1 channelTIN0TOT018
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MB90945 Series
•MB90F949, MB90F949AX0, X1RSTClockControllerwith PhaseModulatorF2MC-16LXCPUIO Timer 0FRCK0RAM 12 K bytesInputCapture6 channelsOutputCompare4 channelsIO Timer 1IN5 to IN0Flash256 K bytesOUT3 to OUT0PrescalerFRCK1SOT0SCK0SIN0PrescalerUART08/16-bitPPG6 channelsPPG15 to PPG10PPG05 to PPG00Internal data busCANInterface 1RX1TX1SOT3SCK3SIN3UART3(LIN/SCI/SPI)ExternalInterruptINT7 to INT0PrescalerSOT4SCK4SIN4AVCCAVSSAN14 to AN0AVRHAVRLADTG10-bit A/D Converter 15 input channelSerial I/OI2CInterfaceSDASCL16-bit Reload Timer1 channelTIN0TOT019
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MB90945 Series
■MEMORY MAP
MB90947AMB90F947MB90F947A
FFFFFFH
ROM (FF bank)ROM (FE bank)ROM (FD bank)
FF0000HFEFFFFHFE0000H
FFFFFFH
ROM (FF bank)ROM (FE bank)
FF0000HFEFFFFHFE0000HFDFFFFHFD0000HFCFFFFHFC0000H
FBFFFFHFB0000HFAFFFFHFA0000HF9FFFFHF90000H
ROM (FB bank)ROM (FA bank)ROM (F9 bank)
MB90F946A
FFFFFFHFF0000HFEFFFFHFE0000HFDFFFFHFD0000H
MB90F949MB90F949A
ROM (FF bank)ROM (FE bank)ROM (FD bank)ROM (FC bank)
FFFFFFHFF0000HFEFFFFHFE0000HFDFFFFHFD0000HFCFFFFHFC0000HFBFFFFHFB0000HFAFFFFHFA0000HF9FFFFHF90000H8017FFH800000H
MB90V390HAMB90V390HB
ROM (FF bank)ROM (FE bank)
ROM (FD bank)ROM (FC bank)ROM (FB bank)ROM (FA bank)ROM (F9 bank)RAM 6 KbytesROM (Image ofFF bank)
00FFFFH008000H
ROM (Image ofFF bank)
00FFFFH
ROM (Image ofFF bank) 004000H/
008000H
00FFFFH
ROM (Image ofFF bank) 004000H/
008000H
00FFFFH008000H0070FFH
0050FFH004100H003FFFH003500H0030FFH
RAM 12 Kbytes
RAM 4 Kbytes
003FFFH
Peripheral
003500H
Peripheral
003FFFH003500H0030FFH
Peripheral
004100H003FFFH003500H0030FFH
Peripheral
RAM 12 Kbytes
000100H0000BFH000000H
Peripheral
0018FFH000100H0000BFH000000H
RAM 6 KbytesPeripheral
000100H0000BFH000000H
RAM 12 Kbytes
000100H
Peripheral
0000BFH000000H
RAM 12 Kbytes
Peripheral
: No access
Note : The high-order portion of bank 00 gives the image of the FF bank ROM to make the small model of the C
compiler effective. Since the low-order 16 bits are the same, the table in ROM can be referenced without using the far specification in the pointer declaration.
For example, an attempt to access 00C000H accesses the value at FFC000H in ROM.
The ROM area in bank FF exceeds 32/48 K bytes, and its entire image cannot be shown in bank 00.
The image between FF4000H/FF8000H and FFFFFFH is visible in bank 00, while the image between FF0000H and FF3FFFH/FF7FFFH is visible only in bank FF.20
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MB90945 Series
■I/O MAP
Address00H01H02H03H04H05H06H07H08H09H0AH0BH0CH0DH0EH0FH10H11H12H13H14H15H16H17H18H19H1AH1BH1CH to 1FH
Port 8 direction registerPort 9 direction registerPort A direction registerPort B direction registerPort 8 data registerPort 9 data registerPort A data registerPort B data registerAnalog Input Enable 0
Analog Input Enable 1/ ADC SelectInput Level Select Register
(MB90V390HA/MB90V390HB only) Input Level Select Register
(MB90V390HA/MB90V390HB only) Port 0 direction registerPort 1 direction registerPort 2 direction registerPort 3 direction registerPort 4 direction registerPort 5 direction registerPort 6 direction register
Register
Port 0 data registerPort 1 data registerPort 2 data registerPort 3 data registerPort 4 data registerPort 5 data registerPort 6 data register
Abbrevia-Access
tionPDR0PDR1PDR2PDR3PDR4PDR5PDR6ReservedPDR8PDR9PDRAPDRBADER0ADER1ILSRILSRDDR0DDR1DDR2DDR3DDR4DDR5DDR6ReservedDDR8DDR9DDRADDRBReserved
(Continued)
R/WR/WR/WR/W
Port 8Port 9Port APort B
XXXXXX00000000000000000000000000
R/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/W
Port 8Port 9Port APort BPort 6, A/DPort B, A/DPortsPortsPort 0Port 1Port 2Port 3Port 4Port 5Port 6
XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX1111111101111111000000000000000000000000000000000000000000000000000000000000000000000000
R/WR/WR/WR/WR/WR/WR/W
Resource name
Port 0Port 1Port 2Port 3Port 4Port 5Port 6
Initial valueXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
21
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MB90945 Series
Address20H21H22H23H24H to 2BH
2CH2DH2EH2FH30H31H32H33H34H35H36H37H38H39H3AH3BH3CH3DH3EH3FH40H41H42H43H44H45H46H47H
Register
Serial Mode Control 0Status 0
Input/Output Data 0Rate and Data 0Serial Mode Control 4Serial Mode Control 4Serial Data 4
Serial I/O Prescaler/Edge Selector 4External Interrupt EnableExternal Interrupt RequestExternal Interrupt LevelExternal Interrupt LevelA/D Control Status 0A/D Control Status 1A/D Data 0A/D Data 1
PPG0 operation mode control registerPPG1 operation mode control registerPPG0 and PPG1 clock select registerPPG2 operation mode control registerPPG3 operation mode control registerPPG2 and PPG3 clock select registerPPG4 operation mode control registerPPG5 operation mode control registerPPG4 and PPG5 clock select registerPPG6 operation mode control registerPPG7 operation mode control registerPPG6 and PPG7 clock select register
Abbrevia-Access
tionUMC0USR0UIDR0/UODR0URD0ReservedSMCS4SMCS4SDR4CDCR4ENIREIRRELVRELVRADCS0ADCS1ADCR0ADCR1PPGC0PPGC1PPG01ReservedPPGC2PPGC3PPG23ReservedPPGC4PPGC5PPG45ReservedPPGC6PPGC7PPG67Reserved
R/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WRR/WR/WR/WR/WR/WR/WR/WR/W
Resource nameInitial value0000010000010000
UART0
XXXXXXXX0000000XXXXX0000
Serial I/OInterface
00000010XXXXXXXX0 X 0 X 000000000000XXXXXXXX00000000000000000000000000000000XXXXXXXX000000XX0X000XX10X000001000000XX0X000XX10X000001000000XX0X000XX10X000001000000XX0X000XX10X000001000000XX(Continued)
External Interrupt
A/D Converter
16-bit Programable
Pulse Generator 0/1
16-bit Programable
Pulse Generator 2/3
16-bit Programable
Pulse Generator 4/5
16-bit Programable
Pulse Generator 6/7
22
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MB90945 Series
Address48H49H4AH4BH4CH4DH4EH4FH50H51H52H to 53H
54H55H56H57H58H59H5AH5BH5CH to 6EH6FH70H to 7FH90H to 9DH
9EH9FHA0HA1HA2H to A7H
A8HA9HAAH to ADH
ROM Mirror
Register
PPG8 operation mode control registerPPG9 operation mode control registerPPG8 and PPG9 clock select registerPPGA operation mode control registerPPGB operation mode control registerPPGA and PPGB clock select registerTimer Control Status 0Timer Control Status 0
Input Capture Control Status 0/1Input Capture Control Status 2/3Input Capture Control Status 4/5Output Compare Control Status 0Output Compare Control Status 1Output Compare Control Status 2Output Compare Control Status 3
Abbrevia-Access
tionPPGC8PPGC9PPG89ReservedPPGCAPPGCBPPGABReservedTMCSR0TMCSR0ReservedICS01ICS23ICS45ReservedOCS0OCS1OCS2OCS3ReservedROMMReservedReserved
WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/W
Resource name16-bit Programable
Pulse Generator 8/9
Initial value0X000XX10X000001000000XX0X000XX10X000001000000XX00000000
16-bit Programable
Pulse Generator A/B
16-bit Reload Timer
0
XXXX00000000000000000000000000000000XX000XX000000000XX000XX00000
Input Capture 0/1Input Capture 2/3Input Capture 4/5
Output Compare 0/1Output Compare 2/3
ROM MirrorXXXXXXX1
80H to 8FHReserved for CAN Interface 1. Refer to “■ CAN CONTROLLER”
ROM Correction Control Status 0Delayed Interrupt/releaseLow-power ModeClock Selector
PACSR0DIRRLPMCRCKSCRReserved
Watchdog ControlTimebase timer Control
WDTCTBTCReserved
(Continued)
23
R/WR/W
Watchdog TimerTimebase timer
XXXXX1111XX00100
R/WR/WR/WR/W
ROM Correction 0Delayed InterruptLow Power ControllerLow Power Controller
00000000XXXXXXX00001100011111100
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MB90945 Series
AddressAEHAFHB0HB1HB2HB3HB4HB5HB6HB7HB8HB9HBAHBBHBCHBDHBEHBFHC0H to FFH
Interrupt control register 00Interrupt control register 01Interrupt control register 02Interrupt control register 03Interrupt control register 04Interrupt control register 05Interrupt control register 06Interrupt control register 07Interrupt control register 08Interrupt control register 09Interrupt control register 10Interrupt control register 11Interrupt control register 12Interrupt control register 13Interrupt control register 14Interrupt control register 15
Register
Flash Control Status
(Flash devices only. Otherwise reserved)
Abbrevia-Access
tionFMCSReservedICR00ICR01ICR02ICR03ICR04ICR05ICR06ICR07ICR08ICR09ICR10ICR11ICR12ICR13ICR14ICR15Reserved
(Continued)R/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/W
Interrupt controller
00000111000001110000011100000111000001110000011100000111000001110000011100000111000001110000011100000111000001110000011100000111
R/W
Resource nameFlash memory
Initial value000X0000
24
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MB90945 Series
Address3500H3501H3502H3503H3504H3505H3506H3507H3508H3509H350AH350BH350CH350DH350EH350FH3510H3511H3512H3513H3514H3515H3516H3517H3518H3519H351AH351BH351CH351DH351EH351FH
Reload LReload HReload LReload HReload LReload HReload LReload HReload LReload HReload LReload HReload LReload HReload LReload HReload LReload HReload LReload HReload LReload HReload LReload H
Serial Mode RegisterSerial Control Register
Reception/Transmission Data RegisterSerial Status Register
Extended Communication Control Reg.Extended Status/Control RegisterBaud Rate Register 0Baud Rate Register 1
Register
Abbrevia-Access
tionPRLL0PRLH0PRLL1PRLH1PRLL2PRLH2PRLL3PRLH3PRLL4PRLH4PRLL5PRLH5PRLL6PRLH6PRLL7PRLH7PRLL8PRLH8PRLL9PRLH9PRLLAPRLHAPRLLBPRLHBSMR3SCR3RDR3/TDR3SSR3ECCR3ESCR3BGR03BGR13
R/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/W
UART3Resource name
Initial valueXXXXXXXX
16-bit Programable XXXXXXXX
Pulse
XXXXXXXXGenerator 0/1
XXXXXXXX
XXXXXXXX
16-bit Programable XXXXXXXX
Pulse
XXXXXXXXGenerator 2/3
XXXXXXXX
XXXXXXXX
16-bit Programable XXXXXXXX
Pulse
XXXXXXXXGenerator 4/5
XXXXXXXX
XXXXXXXX
16-bit Programable XXXXXXXX
Pulse
XXXXXXXXGenerator 6/7
XXXXXXXX
XXXXXXXX
16-bit Programable XXXXXXXX
Pulse
XXXXXXXXGenerator 8/9
XXXXXXXX
XXXXXXXX
16-bit Programable XXXXXXXX
Pulse
XXXXXXXXGenerator A/B
XXXXXXXX
00000000000000000000000000001000000000XX000001000000000000000000(Continued)
25
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MB90945 Series
Address3520H3521H3522H3523H3524H3525H3526H3527H3528H3529H352AH352BH352CH352DH352EH352FH3530H3531H3532H3533H3534H3535H3536H3537H3538H to 353BH353CH353DH353EH353FH3540H3541H3542H to 356DH
Timer Data 1Timer Data 1Timer Control 1Timer Control 1Input Capture 0Input Capture 0Input Capture 1Input Capture 1Input Capture 2Input Capture 2Input Capture 3Input Capture 3Input Capture 4Input Capture 4Input Capture 5Input Capture 5Timer Data 0Timer Data 0Timer Control 0Timer Control 0
Register
Abbrevia-Access
tionIPCP0IPCP0IPCP1IPCP1IPCP2IPCP2IPCP3IPCP3IPCP4IPCP4IPCP5IPCP5TCDT0TCDT0TCCS0TCCS0OCCP0OCCP0OCCP1OCCP1OCCP2OCCP2OCCP3OCCP3ReservedTCDT1TCDT1TCCS1TCCS1TMR0/TMRLR0TMR0/TMRLR0Reserved
R/WR/WR/WR/WR/WR/WRRRRRRRRRRRRR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/W
Resource nameInitial valueXXXXXXXX
Input Capture 0/1
XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX0000000000000000000000000XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
Input Capture 2/3
Input Capture 4/5
I/O Timer 0
Output Compare 0Output Compare 0Output Compare 1Output Compare 1Output Compare 2Output Compare 2Output Compare 3Output Compare 3
Output Compare 0/1
Output Compare 2/3
00000000
I/O Timer 1
00000000000000000XXXXXXX
16-bit Reload Timer 0
XXXXXXXXXXXXXXXX
Timer 0/Reload 0Timer 0/Reload 0
(Continued)
26
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MB90945 Series
Address356EH356FH to 359FH35A0H35A1H35A2H35A3H35A4H35A5H35A6H35A7H35A8H35A9H to 35AAH35ABH35ACH to 35C8H35C9H35CAH35CBH35CCH to 35CEH35CFH35D0H to 35D7H35D8H35D9H35DAH35DBH35DCH35DDH35DEH35DFH
Register
CAN Direct Mode Register
Abbrevia-Access
tionCDMRReserved
R/W
Resource nameCAN clock sync
Initial valueXXXXXXX0
I2C bus status registerI2C bus control register
I2C ten bit slave address registerI2C ten bit address mask registerI2C seven bit slave address registerI2C seven bit address mask registerI2C data register
IBSRIBCRITBALITBAHITMKLITMKHISBAISMKIDARReserved
RR/WR/WR/WR/WR/WR/WR/WR/W
I2C Interface
000000000000000000000000000000001111111100111111000000000111111100000000
I2C clock control registerICCRReserved
R/WI2C Interface00011111
Input Capture Edge 0/1Input Capture Edge 2/3Input Capture Edge 4/5
ICE01ICE23ICE45Reserved
R/WRR/W
Input Capture 0/1Input Capture 2/3Input Capture 4/5
XXXXX0XXXXXXXXXXXXXXX0XX
PLL and Special Configuration Control Register
PSCCRReserved
WPLLXXXX0000
Serial Mode RegisterSerial Control Register
Reception/Transmission Data RegisterSerial Status Register
Extended Communication Control Reg.Extended Status/Control RegisterBaud Rate Register 0Baud Rate Register 1
SMR2SCR2RDR2/TDR2SSR2ECCR2ESCR2BGR02BGR12
R/WR/WR/WR/WR/WR/WR/WR/W
UART2
(MB90V390HA, MB90V390HB and MB90F946A only)UART2
(MB90V390HA, MB90V390HB and MB90F946A only)
00000000000000000000000000001000000000XX000001000000000000000000
27
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MB90945 Series
Address35E0H35E1H35E2H35E3H35E4H35E5H(Continued)Address35E6H35E7H35E8H35E9H to 37FFH3800H to 38FFH3900H to 39FFH3A00H to 3FFFH
_ : Unused bitX : Unknown value
Note : Any write access to reserved addresses in I/O map should not be performed.
A read access to reserved address results in reading “X”.
Register
ROM Correction Address 2ROM Correction Address 2ROM Correction Address 2
Abbrevia-Access
tionPADR2PADR2PADR2Reserved
Reserved for CAN Interface 1. Refer to “■ CAN CONTROLLER”Reserved for CAN Interface 1. Refer to “■ CAN CONTROLLER”
Reserved
R/WR/WR/W
Resource name
Initial valueXXXXXXXX
Address Matching
XXXXXXXX
Detection Function 0
XXXXXXXX
Register
ROM Correction Address 0ROM Correction Address 0ROM Correction Address 0ROM Correction Address 1ROM Correction Address 1ROM Correction Address 1
Abbrevia-Access
tionPADR0PADR0PADR0PADR1PADR1PADR1
R/WR/WR/WR/WR/WR/W
Resource name
Initial valueXXXXXXXXXXXXXXXX
Address Matching XXXXXXXXDetection Function 0XXXXXXXX
XXXXXXXXXXXXXXXX(Continued)28
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MB90945 Series
■CAN CONTROLLER
The CAN controller has the following features :
•Conforms to CAN Specification Version 2.0 Part A and B
- Supports transmission/reception in standard frame and extended frame formats•Supports transmitting of data frames by receiving remote frames•16 transmitting/receiving message buffers- 29-bit ID and 8-byte data
- Multi-level message buffer configuration
•Provides full-bit comparison, full-bit mask, acceptance mask register 0/acceptance mask register 1 for eachmessage buffer as ID acceptance mask
- Two acceptance mask registers in either standard frame format or extended frame formats•Bit rate programmable from 10 Kbps to 2 Mbps (when input clock is at 16 MHz)
List of Control Registers (1)
AddressCAN1000080H000081H000082H000083H000084H000085H000086H000087H000088H000089H00008AH00008BH00008CH00008DH00008EH00008FH
RegisterMessage buffervalid registerTransmit request
registerTransmit cancel
registerTransmit complete registerReceive complete registerRemote request receiving
register
Receive overrun
registerReceive interrupt enable
register
AbbreviationBVALRTREQRTCANRTCRRCRRRTRRROVRRRIER
AccessR/WR/WWR/WR/WR/WR/WR/W
Initial Value00000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 00000000
29
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MB90945 Series
List of Control Registers (2)
AddressCAN1003900H003901H003902H003903H003904H003905H003906H003907H003908H003909H00390AH00390BH00390CH00390DH00390EH00390FH003910H003911H003912H003913H003914H003915H003916H003917H003918H003919H00391AH00391BH
Acceptance mask register 1
AMR1
R/W
XXXXXXXXXXXXXXXX
Acceptance mask register 0
AMR0
R/W
XXXXXXXXXXXXXXXXXXXXXXXX XXXXXXXX
Acceptance mask select
register
AMSR
R/W
XXXXXXXX XXXXXXXXXXXXXXXX XXXXXXXX
RegisterControl statusregisterLast eventindicator registerReceive/transmit error counter
Bit timingregisterIDE registerTransmit RTRregisterRemote frame receive waiting
registerTransmit
interrupt enable register
Abbreviation
CSRLEIRRTECBTRIDERTRTRR
AccessR/W, RR/WRR/WR/WR/W
Initial Value00XXX000 0XXXX0X1XXXXXXXX000X000000000000 00000000X1111111 11111111XXXXXXXX XXXXXXXX00000000 00000000XXXXXXXX XXXXXXXX00000000 00000000XXXXXXXX XXXXXXXX
RFWTRR/W
TIERR/W
30
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MB90945 Series
List of Message Buffers (ID Registers) (1)
AddressCAN1003800H
to00381FH003820H003821H003822H003823H003824H003825H003826H003827H003828H003829H00382AH00382BH00382CH00382DH00382EH00382FH003830H003831H003832H003833H003834H003835H003836H003837H003838H003839H00383AH00383BH00383CH00383DH00383EH00383FH
ID register 7
IDR7
R/W
XXXXXXXXXXXXXXXX
31
ID register 6
IDR6
R/W
XXXXXXXXXXXXXXXXXXXXXXXX XXXXXXXX
ID register 5
IDR5
R/W
XXXXXXXXXXXXXXXXXXXXXXXX XXXXXXXX
ID register 4
IDR4
R/W
XXXXXXXXXXXXXXXXXXXXXXXX XXXXXXXX
ID register 3
IDR3
R/W
XXXXXXXXXXXXXXXXXXXXXXXX XXXXXXXX
ID register 2
IDR2
R/W
XXXXXXXXXXXXXXXXXXXXXXXX XXXXXXXX
ID register 1
IDR1
R/W
XXXXXXXX XXXXXXXXXXXXXXXX XXXXXXXX
ID register 0
IDR0
R/W
XXXXXXXXXXXXXXXXXXXXXXXX XXXXXXXX
RegisterGeneral-purpose RAM
Abbreviation
Access
Initial ValueXXXXXXXX
to
XXXXXXXXXXXXXXXX XXXXXXXX
⎯R/W
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MB90945 Series
List of Message Buffers (ID Registers) (2)
AddressCAN1003840H003841H003842H003843H003844H003845H003846H003847H003848H003849H00384AH00384BH00384CH00384DH00384EH00384FH003850H003851H003852H003853H003854H003855H003856H003857H003858H003859H00385AH00385BH00385CH00385DH00385EH00385FH
ID register 15
IDR15
R/W
XXXXXXXXXXXXXXXX
ID register 14
IDR14
R/W
XXXXXXXXXXXXXXXXXXXXXXXX XXXXXXXX
ID register 13
IDR13
R/W
XXXXXXXXXXXXXXXXXXXXXXXX XXXXXXXX
ID register 12
IDR12
R/W
XXXXXXXXXXXXXXXXXXXXXXXX XXXXXXXX
ID register 11
IDR11
R/W
XXXXXXXXXXXXXXXXXXXXXXXX XXXXXXXX
ID register 10
IDR10
R/W
XXXXXXXXXXXXXXXXXXXXXXXX XXXXXXXX
ID register 9
IDR9
R/W
XXXXXXXXXXXXXXXXXXXXXXXX XXXXXXXX
ID register 8
IDR8
R/W
XXXXXXXXXXXXXXXXXXXXXXXX XXXXXXXX
Register
Abbreviation
Access
Initial ValueXXXXXXXX XXXXXXXX
32
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MB90945 Series
List of Message Buffers (DLC Registers and Data Registers) (1)
AddressCAN1003860H003861H003862H003863H003864H003865H003866H003867H003868H003869H00386AH00386BH00386CH00386DH00386EH00386FH003870H003871H003872H003873H003874H003875H003876H003877H003878H003879H00387AH00387BH00387CH00387DH00387EH00387FH
RegisterDLC register 0DLC register 1DLC register 2DLC register 3DLC register 4DLC register 5DLC register 6DLC register 7DLC register 8DLC register 9DLC register 10DLC register 11DLC register 12DLC register 13DLC register 14DLC register 15
AbbreviationDLCR0DLCR1DLCR2DLCR3DLCR4DLCR5DLCR6DLCR7DLCR8DLCR9DLCR10DLCR11DLCR12DLCR13DLCR14DLCR15
AccessR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/W
Initial ValueXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
33
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MB90945 Series
List of Message Buffers (DLC Registers and Data Registers) (2)
AddressCAN1003880H
to 003887H003888H
to 00388FH003890H
to 003897H003898H
to 00389FH0038A0H
to 0038A7H0038A8H
to 0038AFH0038B0H
to 0038B7H0038B8H
to 0038BFH0038C0H
to 0038C7H0038C8H
to 0038CFH0038D0H
to 0038D7H0038D8H
to 0038DFH0038E0H
to 0038E7H0038E8H
to 0038EFH
Register
Abbreviation
Access
Initial ValueXXXXXXXX
to XXXXXXXXXXXXXXXX
to XXXXXXXXXXXXXXXX
to XXXXXXXXXXXXXXXX
to XXXXXXXXXXXXXXXX
to XXXXXXXXXXXXXXXX
to XXXXXXXXXXXXXXXX
to XXXXXXXXXXXXXXXX
to XXXXXXXXXXXXXXXX
to XXXXXXXXXXXXXXXX
to XXXXXXXXXXXXXXXX
to XXXXXXXXXXXXXXXX
to XXXXXXXXXXXXXXXX
to XXXXXXXXXXXXXXXX
to XXXXXXXX
Data register 0 (8 bytes) DTR0R/W
Data register 1 (8 bytes) DTR1R/W
Data register 2 (8 bytes) DTR2R/W
Data register 3 (8 bytes) DTR3R/W
Data register 4 (8 bytes) DTR4R/W
Data register 5 (8 bytes) DTR5R/W
Data register 6 (8 bytes) DTR6R/W
Data register 7 (8 bytes) DTR7R/W
Data register 8 (8 bytes) DTR8R/W
Data register 9 (8 bytes) DTR9R/W
Data register 10 (8 bytes) DTR10R/W
Data register 11 (8 bytes) DTR11R/W
Data register 12 (8 bytes) DTR12R/W
Data register 13 (8 bytes) DTR13R/W
34
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MB90945 Series
List of Message Buffers (DLC Registers and Data Registers) (3)
AddressCAN10038F0H
to 0038F7H0038F8H
to 0038FFH
Register
Abbreviation
Access
Initial ValueXXXXXXXX
to XXXXXXXXXXXXXXXX
to XXXXXXXX
Data register 14 (8 bytes) DTR14R/W
Data register 15 (8 bytes) DTR15R/W
35
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MB90945 Series
■INTERRUPT FACTORS, INTERRUPT VECTORS, INTERRUPT CONTROL REGISTER
Interrupt causeResetINT9 instructionExceptionTimebase timerExternal Interrupt INT0 to INT7ReservedReservedCAN 1 RXCAN 1 TX/NSPPG 0/1PPG 2/3PPG 4/5PPG 6/7PPG 8/9PPG A/B16-bit Reload Timer 0ReservedInput Capture 0/1Output compare 0/1Input Capture 2/3Output Compare 2/3Input Capture 4/5I2CA/D ConverterI/O Timer 0 / I/O Timer 1Serial I/OReservedUART 0 RXUART 0 TXReservedReservedN/AN/AN/AN/AN/AN/AN/AN/AN/AEI2OS clearN/AN/AN/AN/AInterrupt vectorNumber#08#09#10#11#12#13#14#15#16#17#18#19#20#21#22#23#24#25#26#27#28#29#30#31#32#33#34#35#36#37#38AddressFFFFDCHFFFFD8HFFFFD4HFFFFD0HFFFFCCHFFFFC8HFFFFC4HFFFFC0HFFFFBCHFFFFB8HFFFFB4HFFFFB0HFFFFACHFFFFA8HFFFFA4HFFFFA0HFFFF9CHFFFF98HFFFF94HFFFF90HFFFF8CHFFFF88HFFFF84HFFFF80HFFFF7CHFFFF78HFFFF74HFFFF70HFFFF6CHFFFF68HFFFF64HInterrupt control registerNumber⎯⎯⎯ICR00ICR01ICR02ICR03ICR04ICR05ICR06ICR07ICR08ICR09ICR10ICR11ICR12ICR13Address⎯⎯⎯0000B0H0000B1H0000B2H0000B3H0000B4H0000B5H0000B6H0000B7H0000B8H0000B9H0000BAH0000BBH0000BCH0000BDH(Continued)
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MB90945 Series
(Continued)
Interrupt cause
UART 2 RX / UART 3 RXUART 2 TX / UART 3 TXFlash memoryDelayed interrupt
N/AN/AEI2OS clear
Interrupt vectorNumber#39#40#41#42
AddressFFFF60HFFFF5CHFFFF58HFFFF54H
Interrupt control
registerNumberICR14ICR15
Address0000BEH0000BFH
: The interrupt request flag is cleared by the EI2OS interrupt clear signal.
: The interrupt request flag is cleared by the EI2OS interrupt clear signal. A stop request is available. : Unavailable
N/A : The interrupt request flag is not cleared by the EI2OS interrupt clear signal.
Notes : •For a peripheral module with two interrupt causes for a single interrupt number, both interrupt request
flags are cleared by the EI2OS interrupt clear signal.
•At the end of EI2OS, the EI2OS clear signal will be asserted for all the interrupt flags assigned to the same interrupt number. If one interrupt flag starts the EI2OS and in the meantime another interrupt flag is set by hardware event, the later event is lost because the flag is cleared by the EI2OS clear signal caused by the first event. So it is recommended not to use the EI2OS for this interrupt number.
•If EI2OS is enabled, EI2OS is initiated when one of the two interrupt signals in the same interrupt control register (ICR) is asserted. This means that different interrupt sources share the same EI2OS Descriptor which should be unique for each interrupt source. For this reason, when one interrupt source uses the EI2OS, the other interrupt should be disabled.
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MB90945 Series
■ELECTRICAL CHARACTERISTICS
1.Absolute Maximum Ratings
Parameter
SymbolVCC
Power supply voltage*1
AVCC
RatingMinVSS − 0.3VSS − 0.3
MaxVSS + 6.0VSS + 6.0VSS + 6.0VSS + 6.0VSS + 6.0+4.04015410050−15−4−100−50500525+105+150
UnitVVVVVmAmAmAmAmAmAmAmAmAmA
VCC = AVCC *2
AVCC ≥ AVRH, AVCC ≥ AVRL, AVRH ≥ AVRL*3*3*5*5*4*4*4*4*4*4*4*4
Remarks
AVRH,
VSS − 0.3
AVRLVIVOICLAMPΣ|ICLAMP|IOL1IOLAV1ΣIOL1ΣIOLAV1IOH1IOHAV1ΣIOH1ΣIOHAVPDTATSTG
VSS − 0.3VSS − 0.3−4.0⎯⎯⎯⎯⎯⎯⎯⎯⎯⎯⎯
Input voltage*1Output voltage*1
Maximum Clamp CurrentTotal Maximum Clamp Current“L” level maximum output current“L” level average output current“L” level maximum overall output current“L” level average overall output current“H” level maximum output current“H” level average output current“H” level maximum overall output current“H” level average overall output currentPower consumptionOperating temperatureStorage temperature
MB90947A/F947/F947A/F949/mWF949A
MB90F946A °C °C
−40−55
*1 : This parameter is based on VSS = AVSS = 0 V.
*2 : Set AVCC and VCC to the same voltage. Make sure that AVCC does not exceed VCC and that the voltage at the
analog inputs does not exceed AVCC when the power is switched on.*3 : VI and VO should not exceed VCC + 0.3 V. VI should not exceed the specified ratings. However if the maximum
current to/from a input is limited by some means with external components, the ICLAMP rating supercedes the VI rating.*4 : Applicable to pins : P00 to P07, P10 to P17, P20 to P27, P30 to P37, P40 to P47, P50 to P57, P60 to P67,
P80, P81, P90 to P97, PA0 to PA7, PB0 to PB7*5 : •Applicable to pins : P00 to P07, P10 to P17, P20 to P27, P30 to P37, P40 to P47, P50 to P57, P60 to P67,
P80, P81, P90 to P97, PA0 to PA7, PB0 to PB7
•Use within recommended operating conditions.•Use at DC voltage (current)
•The +B signal should always be applied a limiting resistance placed between the +B signal and themicrocontroller.
•The value of the limiting resistance should be set so that when the +B signal is applied the input current tothe microcontroller pin does not exceed rated values, either instantaneously or for prolonged periods.•Note that when the microcontroller drive current is low, such as in the power saving modes, the +B inputpotential may pass through the protective diode and increase the potential at the VCC pin, and this may affectother devices.38
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MB90945 Series
•Note that if a +B signal is input when the microcontroller power supply is off (not fixed at 0 V) , the powersupply is provided from the pins, so that incomplete operation may result.
•Note that if the +B input is applied during power-on, the power supply is provided from the pins and the resultingsupply voltage may not be sufficient to operate the power-on reset.•Care must be taken not to leave the +B input pin open.
•Note that analog system input/output pins other than the A/D input pins (LCD drive pins, comparator inputpins, etc.) cannot accept +B signal input.•Sample recommended circuits : • Input/output equivalent circuitsProtective diodeLimitingresistance+B input (0 V to 16 V)NchVCCPchRWARNING:Semiconductor devices can be permanently damaged by application of stress (voltage, current,
temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
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MB90945 Series
2.Recommended Conditions
(VSS = AVSS = 0 V)
Parameter
Symbol
Value
Min3.5
Power supply voltage
VCC, AVCC
4.04.52.0
Smoothing capacitorOperating temperature
CSTA
0.1−40
Typ5.05.05.0⎯⎯⎯
Max5.55.55.55.51.0+105
Unit
Remarks
Other than when writing to Flash memory and when using the A/D converter
When writing to Flash memoryWhen using the A/D converterRetain RAM data in stop mode*
VVVVµF °C
* : Use a ceramic capacitor, or a capacitor of similar frequency characteristics. On the VCC pin, use a bypass capacitor that has a larger capacity than that of CS. Refer to the following figure for connection of smoothing capacitor CS.• C Pin Connection DiagramCCSWARNING:The recommended operating conditions are required in order to ensure the normal operation of the
semiconductor device. All of the device’s electrical characteristics are warranted when the device isoperated within these ranges.
Always use semiconductor devices within their recommended operating condition ranges. Operationoutside these ranges may adversely affect reliability and could result in device failure.
No warranty is made with respect to uses, operating conditions, or combinations not represented onthe data sheet. Users considering application outside the listed conditions are advised to contact theirFUJITSU representatives beforehand.
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MB90945 Series
3.DC Characteristics
(TA = −40 °C to +105 °C, VCC = 5.0 V ± 10%, VSS = AVSS = 0 V)
Parameter
Sym-bolVIHA
Pin
Condition
Value
Min0.8 VCC
Typ⎯
MaxVCC + 0.3
Unit
RemarksPort inputs except ports P21/RX1, P42/SDA, P43/SCLPort inputs P21/RX1, P42/SDA, P43/SCL
RST input pin (CMOS Hysteresis) MD input pinPort inputs except ports P21/RX1, P42/SDA, P43/SCLPort inputs P21/RX1, P42/SDA, P43/SCL
RST input pin (CMOS Hysteresis) MD input pin
⎯⎯V
Input “H” voltage
VIHSVIHRVIHMVILA
⎯⎯⎯⎯
⎯⎯⎯⎯
0.7 VCC0.8 VCCVCC − 0.3VSS − 0.3
⎯⎯⎯⎯
VCC + 0.3VCC + 0.3VCC + 0.30.5 VCC
VVVV
Input “L”voltage
VILSVILRVILM
⎯⎯⎯Normal outputsI2CoutputsNormal outputsI2Coutputs
⎯
⎯⎯⎯
VCC = 4.5 V, IOH1 = −4.0 mAVCC = 4.5 V, IOH1 = −3.0 mAVCC = 4.5 V, IOL1 = 4.0 mAVCC = 4.5 V, IOL1 = 3.0 mAVCC = 5.5 V, VSS < VI < VCC
VSS − 0.3VSS − 0.3VSS − 0.3VCC − 0.5VCC − 0.5⎯⎯−1
⎯⎯⎯⎯⎯⎯⎯⎯
0.3 VCC0.2 VCCVSS + 0.3⎯⎯0.40.41
VVVVVVVµA
Output “H” voltageOutput “H” voltageOutput “L” voltageOutput “L” voltageInput leak current
VOHVOHIVOLVOLIIIL
(Continued)
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MB90945 Series
(Continued)
(TA = −40 °C to +105 °C, VCC = 5.0 V ± 10%, VSS = AVSS = 0 V)
ParameterPull-down resistance
Sym-bolRDOWN
PinMD2
Condition
⎯
VCC = 5.0 V,
Internal frequency : 24 MHz,
At normal operation.VCC = 5.0 V,
Internal frequency : 20 MHz,
At normal operation.VCC = 5.0 V,
Internal frequency : 20 MHz,
At writing FLASH memory.VCC = 5.0 V,
Internal frequency : 20 MHz,
At erasing FLASH memory.VCC = 5.0 V,
Internal frequency : 24 MHz,
At Sleep mode.
VCC = 5.0 V,
Internal frequency : 2 MHz,
At Main Timebase timer modeVCC = 5.0 V,
Internal frequency : 24 MHz,
At PLL Timebase timer mode, external frequency = 4 MHz
ValueMin25⎯⎯⎯⎯⎯⎯⎯⎯⎯⎯⎯
Typ50606550556570707525280.3
Max100758565758090859535400.6
UnitkOhmmAmAmAmAmAmAmAmAmAmAmA
Remarksonly ROM devicesMB90947AMB90F947/AMB90F949/AMB90F946AMB90947AMB90F947/AMB90F949/AMB90F946AMB90F947/AMB90F949/AMB90F946AMB90F947/AMB90F949/AMB90F946AMB90947AMB90F947/AMB90F949/AMB90F946AMB90947AMB90F946AMB90F947/AMB90F949/AMB90947AMB90F946AMB90F947/AMB90F949/AMB90947AMB90F946AMB90F947/AMB90F949/A
ICC
Power supply current*
ICCS
VCC
ICTS
ICTSPLL6
⎯57mA
ICCH
Other than C, AVCC, AVSS, AVRH, AVRL, VCC, VSS
VCC = 5.0 V, At Stop mode, TA = +25°C
⎯5100µA
Input capacityCIN
⎯⎯515pF
* : The power supply current is measured with an external clock.
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MB90945 Series
4.AC Characteristics
(1) Clock Timing
(TA = −40 °C to +105 °C, VCC = 3.5V to 5.5 V, VSS = AVSS = 0 V)
Parameter
Sym-bol
Value
Pin
Min34
X0, X1
444
Clockfrequency
fC
434
X0
4444
Clockcycle timeInput clockpulse widthInput clockrise and falltime
Machine clockfrequencyMachine clockcycle time
tCYLPWH, PWLtCR, tCF
X0, X1125
Typ⎯⎯⎯⎯⎯⎯⎯⎯⎯⎯⎯⎯⎯
MaxCS2 = 0CS2 = 18886.675⎯1212106.675⎯
333333⎯52420666666
8⎯8⎯6412⎯12⎯64
MHz
× 1/2 (When PLL stops)
When using an oscillation circuitUnit
Remarks
MHzPLL × 1 When using an oscillation circuitMHzPLL × 2 When using an oscillation circuitMHzPLL × 3 When using an oscillation circuitMHzPLL × 4 When using an oscillation circuitMHzPLL × 6 When using an oscillation circuitMHz
× 1/2 (When PLL stops)
When using an external circuit
MHzPLL × 1 When using an external circuitMHzPLL × 2 When using an external circuitMHzPLL × 3 When using an external circuitMHzPLL × 4 When using an external circuitMHzPLL × 6 When using an external circuitnsWhen using an oscillation circuitns
When using an external clock
X0, X183.33⎯X0X0⎯
20⎯1.51.5
⎯⎯⎯⎯
nsDuty ratio is about 30% to 70%.nsWhen using external clock
MHzExcept programming or erasing Flash memory. When programming or erasing Flash memory.MHzBe sure that the maximum momentary
frequency Fmax does not exceed 20MHz.nsExcept programming or erasing Flash memory.ns
When programming or erasing Flash memory.
fCP
⎯⎯⎯
tCP
41.67⎯50
⎯
• Clock TimingtCYLX0PWHtCFPWLtCR0.8 VCC0.2 VCC43
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MB90945 Series
• Guaranteed PLL operation rangeGuaranteed operation rangeGuaranteed PLL operation range (CS2=1)5.5Power supply voltage VCC (V)4.53.5Guaranteed PLL operation range (CS2=0)Guaranteed A/D converter operation range1.548Machine clock fCP (MHz)2024Guaranteed operation range of MB90F947/MB90F949• CS2 (bit 0 in PSCCR register) = 0Machine clock fCP (MHz)2016128641.5346810External clock fC (MHz)*2×1*1 (CS=000)×4 (CS=011)×3 (CS=010)Guaranteed oscilation frequency range×2 (CS=001)×1/2 (PLL off)12• CS2 (bit 0 in PSCCR register) = 1×6 (CS=110)×4 (CS=101)Guaranteed oscilation frequency range×2 (CS=100)24Machine clock fCP (MHz)16861.5346810×1/2 (PLL off)12External clock fC (MHz)*2*1 : PLL × 1 guaranteed operation range is from 4.0 MHz to 12 MHz.*2 : When using a crystal oscillator or a ceramic oscillator, the maximum oscillation clock frequency is 8 MHzExternal clock frequency and Machine clock frequency44
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MB90945 Series
(2) Reset Standby Input
(TA = −40 °C to +105 °C, VCC = 3.5V to 5.5 V, VSS = AVSS = 0.0 V)
Parameter
Symbol
Pin
ValueMin16 tCP*1
Reset input time
tRSTL
RSTOscillation time of oscillator*2
+ 100 + 16 tCP*1
100
Max⎯⎯⎯
Unitnsµsµs
Remarks
Under normal operationIn Stop mode
In Timebase timer mode
*1 : “tCP” represents one cycle time of the machine clock.
No reset can fully initialize the Flash memory if it is performing the automatic algorithm.
*2 : Oscillation time of oscillator is the time that the amplitude reaches 90%.
In the crystal oscillator, the oscillation time is between several ms and to tens of ms. In FAR / ceramic oscillators, the oscillation time is between hundreds of µs to several ms. With an external clock, the oscillation time is 0 ms.
Under normal operation : tRSTLRST0.2 VCC0.2 VCCIn Stop mode : tRSTLRST0.2 VCC90% ofamplitude0.2 VCCX0Internal operationclockOscillation timeof oscillator+100 µs16 tCPOscillation stabilizationwaiting timeInstruction executionInternal reset45
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MB90945 Series
(3) Power On Reset
(TA = −40 °C to +105 °C, VCC = 3.5V to 5.5 V, VSS = AVSS = 0.0 V)
ParameterPower on rise timePower off time
SymboltRtOFF
PinVCCVCC
Condition
⎯
ValueMin0.051
Max30⎯
Unitmsms
Due to repetitive operation
Remarks
tR2.7 V0.2 V0.2 VtOFFIf you change the power supply voltage too rapidly, a power on reset may occur. We recommend that you startup smoothly by restraining voltages when changing the power supply voltage during operation, as shown in the figure below. Perform while not using the PLL clock. However, if voltage drops are within 1 V/s, you can operate while using the PLL clock.0.2 VVCCVCC3 VVSSHolds RAM dataWe recommend a rise of 50 mV/ms maximum.46
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MB90945 Series
(4) UART0, SIO Timing
(TA = −40 °C to +105 °C, VCC = 3.5V to 5.5 V, VSS = AVSS = 0.0 V)
Parameter
Serial clock cycle timeSCK ↓ → SOT delay timeValid SIN → SCK ↑
SCK ↑ → Valid SIN hold timeSerial clock “H” pulse widthSerial clock “L” pulse widthSCK ↓ → SOT delay timeValid SIN → SCK ↑
SCK ↑ → Valid SIN hold time
Sym-boltSCYCtSLOVtIVSHtSHIXtSHSLtSLSHtSLOVtIVSHtSHIX
PinSCK0, SCK4SCK0, SCK4,SOT0, SOT4
Internal clock operation output
SCK0, SCK4, pins are SIN0, SIN4CL = 80 pF + 1 TTL.SCK0, SCK4, SIN0, SIN4SCK0, SCK4SCK0, SCK4
External clock operation output
SCK0, SCK4, pins are
CL = 80 pF + 1 TTL.SIN0, SIN4SCK0, SCK4,
SOT0, SOT4SCK0, SCK4,SIN0, SIN4
Condition
ValueMin8 tCP−80100604 tCP4 tCP⎯6060
Max⎯+80⎯⎯⎯⎯150⎯⎯
Unitnsnsnsnsnsnsnsnsns
Re-marks
Notes : • AC characteristics in CLK synchronized mode.
• CL is load capacity value of pins when testing.
• tCP is the machine clock cycle time (Unit : ns) . Refer to “ (1) Clock timing” rating for tCP.
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MB90945 Series
• Internal Shift Clock ModetSCYCSCK2.4 V0.8 VtSLOV 0.8 VSOT2.4 V0.8 VtIVSHtSHIXVIHVILSINVIHVIL• External Shift Clock ModetSLSHtSHSLVIHVILtSLOVVILVIHSCKSOT2.4 V0.8 VtIVSHtSHIXVIHVILSINVIHVIL48
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MB90945 Series
(5) UART2/3 Timing
•Bit setting : ESCR : SCES = 0, ECCR : SCDE = 0
(TA = −40 °C to +105 °C, VCC = 3.5V to 5.5 V, VSS = AVSS = 0V)
Parameter
Serial clock cycle timeSCK ↓ → SOT delay timeValid SIN → SCK ↑
SCK ↑ → Valid SIN hold timeSerial clock “H” pulse widthSerial clock “L” pulse widthSCK ↓ → SOT delay timeValid SIN → SCK ↑
SCK ↑ → Valid SIN hold timeSCK fall timeSCK rise time
Sym-boltSCYCtSLOVItIVSHItSHIXItSHSLtSLSHtSLOVEtIVSHEtSHIXEtFtR
PinSCK2,SCK3
Condition
ValueMin5 tCP
Max⎯+50⎯⎯⎯⎯2 tCP + 60
⎯⎯1010
UnitRemarksnsnsnsnsnsnsnsnsnsnsns
SCK2,SCK3
−50
SOT2,SOT3Internal clock
operation output
SCK2,SCK3pins are
tCP + 80
SIN2,SIN3CL = 80 pF + 1 TTL.SCK2,SCK3
0
SIN2,SIN3SCK2,SCK3SCK2,SCK3
SCK2,SCK3
SOT2,SOT3External clock SCK2,SCK3operation output SIN2,SIN3pins are
SCK2,SCK3CL = 80 pF + 1 TTL.SIN2,SIN3SCK2,SCK3SCK2,SCK3
tCP + 103 tCP − tR
⎯30tCP + 30⎯⎯
.Note : tCP is the machine clock cycle time (Unit : ns) . Refer to “ (1) Clock timing” rating for tCP
• Internal Shift Clock ModetSCYCSCK2.4 V0.8 VtSLOVI2.4 V0.8 VtIVSHItSHIXIVIHVIL0.8 VSOTSINVIHVIL49
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MB90945 Series
• External Shift Clock ModetSLSHtSHSLVIHVILtFtSLOVE2.4 V0.8 VtIVSHEtSHIXEVIHVILVILtRVIHSCKSOTSINVIHVIL•Bit setting : ESCR : SCES = 1, ECCR : SCDE = 0 (TA = −40 °C to +105 °C, VCC = 3.5V to 5.5V, VSS = AVSS = 0V)
Parameter
Serial clock cycle timeSCK ↑ → SOT delay timeValid SIN → SCK ↓
SCK ↓ → Valid SIN hold timeSerial clock “H” pulse widthSerial clock “L” pulse widthSCK ↑ → SOT delay timeValid SIN → SCK ↓
SCK ↓ → Valid SIN hold timeSCK fall timeSCK rise time
Sym-boltSCYCtSHOVItIVSLItSLIXItSHSLtSLSHtSHOVEtIVSLEtSLIXEtFtR
PinSCK2,SCK3
Condition
ValueMin5 tCP
Max⎯+50⎯⎯⎯⎯2 tCP + 60⎯⎯1010
UnitRemarksnsnsnsnsnsnsnsnsnsnsns
SCK2,SCK3
−50
SOT2,SOT3Internal clock
operation output
SCK2,SCK3pins are
tCP + 80
SIN2,SIN3CL = 80 pF + 1 TTL.SCK2,SCK3
0
SIN2,SIN3SCK2,SCK3SCK2,SCK3SCK2,SCK3SOT2,SOT3
3 tCP − tRtCP + 10⎯
External clock
SCK2,SCK3operation output
30
SIN2,SIN3pins are
C
SCK2,SCK3L = 80 pF + 1 TTL.
tCP + 30
SIN2,SIN3SCK2,SCK3SCK2,SCK3
⎯⎯
Note : tCP is the machine clock cycle time (Unit : ns) . Refer to “ (1) Clock timing” rating for tCP.
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MB90945 Series
• Internal Shift Clock ModetSCYCSCK2.4 V0.8 VtSHOVISOT2.4 V0.8 VtIVSLItSLIXIVIHVILSINVIHVIL • External Shift Clock ModetSHSLtSLSHVIHVILtRtSHOVE2.4 V0.8 VtIVSLEtSLIXEVIHVILtFVILSCKVIHSOTSINVIHVIL51
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MB90945 Series
•Bit setting : ESCR : SCES = 0, ECCR : SCDE = 1
(TA = −40 °C to +105 °C, VCC = 3.5V to 5.5V, VSS = AVSS = 0V)
Parameter
Serial clock cycle timeSCK ↑ → SOT delay timeValid SIN → SCK ↓
SCK ↓ → Valid SIN hold timeSOT → SCK ↓ delay time
Sym-boltSCYCtSHOVItIVSLItSLIXItSOVLI
PinSCK2,SCK3SCK2,SCK3SOT2,SOT3
Condition
ValueMin5 tCP−50
Max⎯+50⎯⎯⎯
Unitnsnsnsnsns
Remarks
Internal clock
SCK2,SCK3
tCP + 80operation output
SIN2,SIN3
pins are
SCK2,SCK3CL = 80 pF + 1 TTL.
0
SIN2,SIN3SCK2,SCK3SOT2,SOT3
3 tCP − 70
.Note : tCP is the machine clock cycle time (Unit : ns) . Refer to “ (1) Clock timing” rating for tCP
tSCYCSCKtSOVLI2.4 V0.8 V tSHOVI2.4 V0.8 VtIVSLItSLIXIVIHVIL0.8 VSOT2.4 V0.8 VSINVIHVIL52
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MB90945 Series
•Bit setting : ESCR : SCES = 1, ECCR : SCDE = 1
(TA = −40 °C to +105 °C, VCC = 3.5V to 5.5V, VSS = AVSS = 0V)
Parameter
Serial clock cycle timeSCK ↓ → SOT delay timeValid SIN → SCK ↑
SCK ↑ → Valid SIN hold timeSOT → SCK ↑ delay time
Sym-boltSCYCtSLOVItIVSHItSHIXItSOVHI
Pin ConditionSCK2,SCK3SCK2,SCK3SOT2,SOT3
ValueMin5 tCP−50
Max⎯+50⎯⎯⎯
Unitnsnsnsnsns
Remarks
Internal clock
SCK2,SCK3
tCP + 80operation output
SIN2,SIN3
pins are
SCK2,SCK3CL = 80 pF + 1 TTL.
0
SIN2,SIN3SCK2,SCK3SOT2,SOT3
3 tCP − 70
.Note : tCP is the machine clock cycle time (Unit : ns) . Refer to “ (1) Clock timing” rating for tCP
tSCYCSCKtSOVHI2.4 V0.8 VtSLOVI2.4 V0.8 VtIVSHItSHIXIVIHVIL2.4 VSOT2.4 V0.8 VSINVIHVIL53
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MB90945 Series
(6) Trigger Input Timing
(TA = −40 °C to +105 °C, VCC = 3.5V to 5.5V, VSS = AVSS = 0.0 V)
ParameterInput pulse width
SymboltTRGHtTRGL
PinINT0 to INT7ADTG
Condition
⎯
ValueMin200tCP + 200
Max⎯⎯
Unitnsns
Remarks
Note : tCP is the machine clock cycle time (Unit : ns) . Refer to “ (1) Clock timing” rating for tCP.• Trigger Input TimingVIHVIHVILtTRGHtTRGLVIL (7) Timer Related Resource Input Timing
(TA = −40 °C to +105 °C, VCC = 3.5V to 5.5V, VSS = AVSS = 0.0 V)
ParameterInput pulse width
SymboltTIWHtTIWL
PinTIN0,
IN0 to IN5
Condition
⎯
ValueMin4 tCP
Max⎯
Unitns
Remarks
Note : tCP is the machine clock cycle time (Unit : ns) . Refer to “ (1) Clock timing” rating for tCP.• Timer Input TimingVIHVIHVILtTIWHtTIWLVIL54
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MB90945 Series
(8) I2C Timing
Parameter
SCL clock frequency
Hold time (repeated) START conditionSDA ↓ → SCL ↓“L” width of SCL clock“H” width of SCL clock
Set-up time for a repeated START conditionSCL ↑ → SDA ↓Data hold timeSCL ↑ → SDA ↓↑Data set-up timeSDA ↓↑ → SCL ↑
Set-up time for STOP conditionSCL ↑ → SDA ↑
Bus free time between STOP and STARTcondition
(TA = −40 °C to +105 °C, VCC = 3.5V to 5.5V, VSS = AVSS = 0.0 V)
Standard-modeFast-mode*4
UnitSymbolCondition
MinMaxMinMaxfSCLtHDSTAtLOWtHIGHtSUSTAtHDDATtSUDATtSUSTOtBUS
R = 1.3 kΩ,
C = 50 pF*1
04.04.74.04.702504.04.7
100⎯⎯⎯⎯3.45*2⎯⎯⎯
00.61.30.60.601000.61.3
400⎯⎯⎯⎯0.9*3⎯⎯⎯
kHzµsµsµsµsµsnsµsµs
*1 : R, C : Pull-up resistor and load capacitor of the SCL and SDA lines.
*2 : The maximum tHDDAT only has to be met if the devie does not stretch the “L” width (tLOW) of the SCL signal.*3 : A Fast-mode I2C-bus device can be used in a Standard-mode I2C-bus system, but the requirement
tSUDAT ≥ 250 ns must then be met.*4 : For use at over 100 kHz, set the machine clock to at least 6 MHz.• I2C TimingSDAtBUStLOWtSUDATtHDSTASCLtHDSTAtHDDATtHIGHtSUSTAtSUSTO55
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MB90945 Series
5.A/D Converter
(TA = −40 °C to +105 °C, 3.0 V ≤ AVRH − AVRL, VCC = AVCC = 5.0 V ± 10%, VSS = AVSS = 0 V)
ParameterResolutionTotal errorNonlinearity errorDifferential
nonlinearity errorZero reading voltageFull scale reading voltageCompare timeSampling timeAnalog port input current
Analog input voltage range
Reference voltage range
Power supply currentReference voltage current
Offset between input channels
Symbol⎯⎯⎯⎯VOTVFST⎯⎯IAINVAIN⎯IAIAHIRIRH⎯
Pin⎯⎯⎯⎯
Value
Min⎯⎯⎯⎯
⎯⎯⎯Typ
Max10±3.0±2.5±1.9
UnitbitLSBLSBLSB
Remarks
AN0 to AN14AVRL − 1.5AVRL + 0.5AVRL + 2.5LSBAN0 to AN14AVRH − 3.5AVRH − 1.5AVRH + 0.5LSB
⎯⎯AN0 to AN14AN0 to AN14
AVRHAVRLAVCCAVCCAVRHAVRHAN0 to AN14
3.31.6−0.3AVRLAVRL + 2.7
0⎯⎯⎯⎯⎯
66 tCP32 tCP⎯⎯⎯⎯3.5⎯165⎯⎯
16500∞+0.3AVRHAVCCAVRH − 2.7
7.5525054
µsµsµAVVVmAµA*µAµA*LSB
* : When not operating A/D converter, this is the current (VCC = AVCC = AVRH = 5.0 V) .Terminology
Conversion error
: Absolute maximum conversion deviation with respect to the theoretical conversion line.
Nonlinearity : Relative maximum conversion deviation with respect to the theoretical conversion
line conncecting to the device unigque zero reading voltage and full scale reading voltage.
Differential nonlinearity : Max conversion deviation in any two adjacent reading voltages with respect to the
theoretical LSB conversion step.
Zero reading voltage : Input voltage which results in the minimum conversion value.Full scale reading voltage : Input voltage which results in the maximum conversion value.
Notes : •tCP is the machine clock cycle time (Unit : ns) . Refer to “4. AC Characteristics (1) Clock timing” rating
.for tCP
•The accuracy gets worse as |AVRH − AVRL| becomes smaller.
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MB90945 Series
6.Definition of A/D Converter Terms
ResolutionLinear error
: Analog variation that is recognized by an A/D converter.
: Deviation between a line across zero-transition line ( “00 0000 0000” ← → “00 0000 0001” ) and full-scale transition line ( “11 1111 1110” ← → “11 1111 1111” ) and actual conversion characteristics.
Differential linear : Deviation of input voltage, which is required for changing output code by 1 LSB, from an ideal errorvalue.Total error : Difference between an actual value and an ideal value. A total error includes zero transition
error, full-scale transition error, and linear error.
Total error3FFH3FEH3FDH Digital output{1 LSB × (N − 1) + 0.5 LSB}Actual conversioncharacteristics1.5 LSB004H003H002H001H0.5 LSBAVRLAnalog inputVNT(Actually-measured value)Actual conversioncharacteristicsIdeal characteristicsAVRHVNT − {1 LSB × (N − 1) + 0.5 LSB}1 LSBAVRH − AVRL1 LSB (Ideal value) = [V]1024VOT (Ideal value) = AVRL + 0.5 LSB [V]Total error of digital output “N” = VFST (Ideal value) = AVRH − 1.5 LSB [V]VNT : A voltage at which digital output transitions from (N − 1) to N.[LSB](Continued)57
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MB90945 Series
(Continued)Linear error3FFH3FEH3FDHDigital outputActual conversioncharacteristics{1 LSB × (N − 1) + VOT }N + 1VFST (actualmeasurement value)VNT (actualmeasurement value)Actual conversioncharacteristicsIdeal characteristics001HVOT (actual measurement value)AVRLAnalog inputAVRHAVRLActual conversioncharacteristicsDifferential linear errorIdeal characteristicsDigital outputN004H003H002HN − 1V (N + 1) T(actual measurementvalue)VNT(actual measurement value)Actual conversioncharacteristicsAVRHN − 2Analog inputLinear error of digital output N =Differential linear error of digital output N =1 LSB =VNT − {1 LSB × (N − 1) + VOT}1 LSBV (N+1) T − VNT1 LSBVFST − VOT1022−1 LSB [LSB][V][LSB]VOT : Voltage at which digital output transits from “000H” to “001H.”VFST : Voltage at which digital output transits from “3FEH” to “3FFH.”58
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MB90945 Series
7.Notes on A/D Converter Section
• About the external impedance of the analog input and its sampling time
•A/D converter with sample and hold circuit. If the external impedance is too high to keep sufficient samplingtime, the analog voltage charged to the internal sample and hold capacitor is insufficient, adversely affectingA/D conversion precision.• Analog input circuit modelRAnalog inputCComparatorDuring sampling : ONRCNote : The values are reference values.MB90F946A/947A/F947/F947A/F949/F949A2.4 kΩ (Max) 36.4 pF (Max) •To satisfy the A/D conversion precision standard, consider the relationship between the external impedanceand minimum sampling time and either adjust the resistor value and operating frequency or decrease theexternal impedance so that the sampling time is longer than the minimum value.• The relationship between the external impedance and minimum sampling time (External impedance = 0 kΩ to 100 kΩ) MB90F947MB90F949 (External impedance = 0 kΩ to 20 kΩ) MB90F947MB90F94910020External impedance [kΩ]8070605040302010005101520253035External impedance [kΩ]90181614121086420012345678Minimum sampling time [µs]Minimum sampling time [µs]•If the sampling time cannot be sufficient, connect a capacitor of about 0.1 µF to the analog input pin.• About the error
The accuracy gets worse as |AVRH − AVRL| becomes smaller.
59
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MB90945 Series
8.Flash Memory Program/Erase Characteristics
ParameterSector erase time
Conditions
Value
Min⎯⎯⎯⎯
⎯AverageTA = +85 °C
10,00020
Typ15716⎯⎯
Max15⎯⎯3,600⎯⎯
UnitsssµscycleYear
*
Remarks
Excludes programming prior to erasure
MB90F947, Excludes pro-gramming prior to erasureMB90F949, Excludes pro-gramming prior to erasureExcept for the overhead time of the system
Chip erase time
TA = +25 °CVCC = 5.0 V
Word (16-bit width) programming timeProgram/Erase cycleFlash Data Retention Time
* : This value comes from the technology qualification (using Arrhenius equation to translate high temperature measurements into normalized value at +85 °C) .
60
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MB90945 Series
■EXAMPLE CHARACTERISTICS
•MB90F947ICC - VCCTA = +25 ˚C, at external clock operatingf = Internal operation frequency6030ICCS - VCCTA = +25 ˚C, at external clock operatingf = Internal operation frequency50f = 24 MHzf = 20 MHzICCS [mA]f = 16 MHz2540ICC [mA]20f = 24 MHz15f = 20 MHzf = 16 MHz10f = 12 MHzf = 10 MHzf = 8 MHzf = 4 MHzf = 2 MHz02.03.04.05.0VCC [V]ICTSPLL6 - VCCTA = +25 ˚C, at external clock operatingf = Internal operation frequency10987ICTSPLL6 [mA]65432102.03.04.05.0VCC [V]6.07.0f = 24 MHz6.07.030f = 12 MHz20f = 10 MHzf = 8 MHzf = 4 MHzf = 2 MHz02.03.04.05.0VCC [V]ICTS - VCCTA = +25 ˚C, at external clock operatingf = Internal operation frequency5004504003506.07.0105ICTS [µA]3002502001501005002.03.04.05.0VCC [V]6.07.0f = 2 MHz(Continued)61
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MB90945 Series
(Continued)ICCH - VCCTA = +25 ˚C, at stop10987ICCH [µA]65432102.03.04.05.0VCC [V]6.07.062
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MB90945 Series
•MB90F949ICC - VCCTA = +25 ˚C, at external clock operatingf = Internal operation frequency60f = 24 MHz30ICCS - VCCTA = +25 ˚C, at external clock operatingf = Internal operation frequency502540ICC [mA]f = 20 MHz20f = 16 MHzICCS [mA]f = 24 MHzf = 20 MHzf = 16 MHz10f = 12 MHzf = 10 MHzf = 8 MHzf = 4 MHzf = 2 MHz2.03.04.05.0VCC [V]6.07.030f = 12 MHz20f = 10 MHzf = 8 MHzf = 4 MHzf = 2 MHz02.03.04.05.0VCC [V]6.07.0151050ICTS - VCCTA = +25 ˚C, at external clock operatingf = Internal operation frequency500450400350ICTSPLL6 [mA]ICTS [µA]3002502001501005002.03.04.05.0VCC [V]6.07.0f = 2 MHz1098765432102.03.0ICTSPLL6 - VCCTA = +25 ˚C, at external clock operatingf = Internal operation frequencyf = 24 MHz4.05.0VCC [V]6.07.0(Continued)63
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MB90945 Series
(Continued)ICCH - VCCTA = +25 ˚C, at stop10987ICCH [µA]65432102.03.04.05.0VCC [V]6.07.064
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MB90945 Series
•I/O Characteristic (VCC−VOH) − IOHTA = +25 °C, VCC = 4.5 V900800VCC-VOH (mV)7006005004003002001000VOL − IOLTA = +25 °C, VCC = 4.5 V10009008007006005004003002001000012345IOL (mA)6789100123456IOH (mA)78910Automotive VIN − VCCTA = +25 °C5.04.54.03.53.02.52.01.51.00.50.05.04.54.03.53.02.52.01.51.00.50.0VOL (mV)CMOS VIN − VCCCAN RX pin, I2C pinTA = +25 °CVIHAVILAVIN (V)VIHSVIN (V)VILS2.53.03.54.04.55.05.56.06.57.02.53.03.54.04.55.05.56.06.57.0VCC (V)VCC (V)65
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MB90945 Series
■ORDERING INFORMATION
Part number
MB90F946APFMB90947APF
Package100-pin Plastic QFP(FPT-100P-M06)100-pin Plastic QFP(FPT-100P-M06)100-pin Plastic QFP (FPT-100P-M06) 100-pin Plastic QFP (FPT-100P-M06) 100-pin Plastic QFP (FPT-100P-M06) 100-pin Plastic QFP (FPT-100P-M06) 299-pin Ceramic PGA (PGA-299C-A01) 299-pin Ceramic PGA (PGA-299C-A01)
For evaluation
It is recommended to use MB90V390HBFor evaluation
It is recommended to use MB90F949A,because MB90F949 does not support clock modulation and CAN at the same time
It is recommended to use MB90F947A,because MB90F947 does not support clock modulation and CAN at the same time
Remarks
MB90F947PF
MB90F947APF
MB90F949PF
MB90F949APFMB90V390HACRMB90V390HBCR
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MB90945 Series
■PACKAGE DIMENSIONS
100-pin Plastic QFP (FPT-100P-M06) 23.90±0.40(.941±.016)*20.00±0.20(.787±.008)8051Note 1) * : These dimensions do not include resin protrusion.Note 2) Pins width and pins thickness include plating thickness.Note 3) Pins width do not include tie bar cutting remainder.81500.10(.004)17.90±0.40(.705±.016)*14.00±0.20(.551±.008)INDEXDetails of \"A\" part100311300.25(.010)+0.353.00–0.20+.014.118–.008(Mounting height)0~8˚0.17±0.06(.007±.002)0.65(.026)\"A\"0.32±0.05(.013±.002)0.13(.005)M0.80±0.20(.031±.008)0.88±0.15(.035±.006)0.25±0.20(.010±.008)(Stand off)C2002 FUJITSU LIMITED F100008S-c-5-5Dimensions in mm (inches) .Note : The values in parentheses are reference values.67
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MB90945 Series
FUJITSU LIMITED
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