DistributorMarch 6, 2008
LMK01000/LMK01010/LMK01020
1.6 GHz High Performance Clock Buffer, Divider, andDistributor
General Description
Features
The LMK01000/LMK01010/LMK01020 family provides aneasy way to divide and distribute high performance clock sig-■30 fs additive jitter (100 Hz to 20 MHz)nals throughout the system. These devices provide best-in-■Dual clock inputs
class noise performance and are designed to be pin-to-pin■Programmable output channels (0 to 1600 MHz)
and footprint compatible with LMK03000/LMK02000 family of—LMK01000: 3 LVDS outputs (CLKout0 - CLKout2) + 5precision clock conditioners.
LVPECL outputs (CLKout3 - CLKout7)The LMK01000/LMK01010/LMK01020 family features two—LMK01010: 8 LVDS outputsprogrammable clock inputs (CLKin0 and CLKin1) that allow—LMK01020: 8 LVPECL outputs
the user to dynamically switch between different clock do-—Channel divider values of 1, 2 to 510 (even divides)mains.
—Programmable output skew controlEach device features 8 clock outputs with independently pro-grammable dividers and delay adjustments. The outputs of■External synchronization
the device can be easily synchronized by an external pin■Pin compatible family of clocking devices(SYNC*).
■3.15 to 3.45 V operation
■
Package: 48 pin LLP (7.0 x 7.0 x 0.8 mm)
Target Applications
■High performance Clock Distribution■Wireless Infrastructure■Medical Imaging
■Wired Communications■Test and Measurement■
Military / Aerospace
System Diagram
30042806
TRI-STATE® is a registered trademark of National Semiconductor Corporation.
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LMK01000/LMK01010/LMK01020Functional Block Diagram
30042801
Connection Diagram
48-Pin LLP Package
30042802
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LMK01000/LMK01010/LMK01020Pin Descriptions
Pin #1, 252, 7, 9,10, 32
Pin NameGNDNC
I/O---IIII
Ground
No Connect. Pin is not connected to the die.Power Supply
MICROWIRE Clock InputMICROWIRE Data InputMICROWIRE Latch Enable InputGlobal Output Enable
This is an output pin used strictly for test purposesand should be not connected for normal operation.However, any load of an impedance of more than 1kΩ is acceptable.Clock Output 0Clock Output 1Clock Output 2Clock Output 3
Global Clock Output SynchronizationCLKin 0 Input; Must be AC coupledCLKin 1 Input; Must be AC coupledBias BypassClock Output 4Clock Output 5Clock Output 6Clock Output 7
Die Attach Pad should be connected to ground.
Description
3, 8, 13, 16, 19, 22, 26,Vcc1, Vcc2, Vcc3, Vcc4, Vcc5, Vcc6, Vcc7,30, 31, 33, 37, 40, 43, 46Vcc8, Vcc9, Vcc10, Vcc11, Vcc12, Vcc13, Vcc14
45611
CLKuWireDATAuWireLEuWireGOE
12TestO
14, 1517, 1820, 2123, 242728, 2934, 353638, 3941, 4244, 4547, 48DAP
CLKout0, CLKout0*CLKout1, CLKout1*CLKout2, CLKout2*CLKout3, CLKout3*
SYNC*CLKin0,CLKin0*CLKin1, CLKin1*
Bias
CLKout4, CLKout4*CLKout5, CLKout5*CLKout6, CLKout6*CLKout7, CLKout7*
DAP
OOOOIIIIOOOO-
The LMK01000 family is footprint compatible with the LMK03000/02000 family of devices. All CLKout pins are pin-to-pin compatible,and CLKin0 and CLKin1 are equivalent to OSCin and Fin, respectively .
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LMK01000/LMK01010/LMK01020Absolute Maximum Ratings (Notes 1, 2)
If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributorsfor availability and specifications.
Parameter
Power Supply VoltageInput Voltage
Storage Temperature RangeLead Temperature (solder 4 s)Junction Temperature
SymbolVCC
VINTSTGTLTJ
Ratings-0.3 to 3.6-0.3 to (VCC + 0.3)
-65 to 150+260125
UnitsVV°C°C°C
Recommended Operating Conditions
Parameter
Ambient TemperaturePower Supply Voltage
SymbolTAVCC
Min-403.15
Typ253.3
Max853.45
Units°CV
Note 1:\"Absolute Maximum Ratings\" indicate limits beyond which damage to the device may occur, including inoperability and degradation of device reliabilityand/or performance. Functional operation of the device and/or non-degradation at the Absolute Maximum Ratings or other conditions beyond those indicated inthe Recommended Operating Conditions is not implied. The Recommended Operating Conditions indicate conditions at which the device is functional and thedevice should not be operated beyond such conditions.
Note 2:This device is a high performance integrated circuit with ESD handling precautions. Handling of this device should only be done at ESD protected workstations. The device is rated to a HBM-ESD of > 2 kV, a MM-ESD of > 200 V, and a CDM-ESD of > 1.2 kV.
Package Thermal Resistance
Package48-Lead LLP (Note 3)
θJA27.4° C/W
θJ-PAD (Thermal Pad)
5.8° C/W
Note 3:Specification assumes 16 thermal vias connect the die attach pad to the embedded copper plane on the 4-layer JEDEC board. These vias play a keyrole in improving the thermal performance of the LLP. It is recommended that the maximum number of vias be used in the board layout.
Electrical Characteristics
(Note 4)
(3.15 V ≤ Vcc ≤ 3.45 V, -40 °C ≤ TA ≤ 85 °C, Differential Inputs/Outputs; except as specified. Typical values represent most likelyparametric norms at Vcc = 3.3 V, TA = 25 °C, and at the Recommended Operation Conditions at the time of product characterizationand are not guaranteed).Symbol
Parameter
Conditions
Current ConsumptionAll outputsenabled, nodivide or delay( CLKoutX_MUX= Bypassed )Per channel, nodivide or delay(CLKoutX_MUX= Bypassed )
LMK01000LMK01010LMK01020LVDS
LVPECL
(Includes EmitterResistors)
10.53040-13
27116033817.8401
1600 70605
MHzV/ns%dBmmA
Min
Typ
Max
Units
ICC
Power Supply Current(Note 5)
ICCPDfCLKinSLEWCLKinDUTYCLKinPCLKin
Power Down CurrentCLKin Frequency Range
CLKin Frequency Input Slew RateCLKin Frequency Input Duty CycleInput Power Range for CLKin orCLKin*
POWERDOWN = 1
CLKin0, CLKin0*, CLKin1, CLKin1*
(Notes 6, 8)fCLKin ≤ 800 MHzfCLKin > 800 MHzAC coupled
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LMK01000/LMK01010/LMK01020Symbol
Parameter
Conditions
Clock Distribution Section--Delays
fCLKoutX ≤ 1 GHz
(Delay is limited to maximumprogrammable value)
fCLKoutX > 1 GHz
(Delay is limited to 1/2 of a period)
Clock Distribution Section - Divides
DivideCLKoutX
Allowable divide range. (Note that 1 isfCLKinX ≤ 1300 MHzthe only allowable odd divide value)1300 MHz < f
CLKinX ≤ 1600 MHz
Clock Distribution Section - LVDS Clock Outputs
fCLKoutX = 200 MHzRL = 100 Ω
Bandwidth =fCLKoutX = 800 MHz100 Hz to 20 MHz
fCLKoutX = 1600 MHz
Vboost = 1RL = 100Vboost = 1
fCLKoutX = 200 MHzfCLKoutX = 800 MHzfCLKoutX = 1600 MHz
-30250 -501.070-35-24-12
803025-156-153-148±4350390 1.25
30450 501.370352412
psdBc/Hzfs
11
5102
n/a
2250
ps
0.5/fCLKoutX
Min
Typ
Max
Units
DelayCLKout
Maximum Allowable Delay(Note 8)
JitterADD
Additive RMS Jitter (Note 7)
Noise FloorDivider Noise Floor(Note 7)
tSKEW
CLKoutX to CLKoutY (Note 8)
Equal loading and identical clockconfigurationRL = 100 Ω(Note 9)RL = 100 ΩRL = 100 ΩRL = 100 Ω
Single ended outputs shorted to GNDComplementary outputs tied together
Vboost=0Vboost=1
VODΔVODVOSΔVOSISAISBISAB
Differential Output VoltageChange in magnitude of VOD forcomplementary output statesOutput Offset Voltage
Change in magnitude of VOS forcomplementary output statesClock Output Short Circuit Currentsingle ended
Clock Output Short Circuit Currentdifferential
mVmVVmVmAmA
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LMK01000/LMK01010/LMK01020Symbol
Parameter
Conditions
fCLKoutX = 200 MHzRL = 100 Ω
Bandwidth =fCLKoutX = 800 MHz100 Hz to 20 MHz
fCLKoutX = 1600 MHz
Vboost = 1RL = 100Vboost = 1
fCLKoutX = 200 MHzfCLKoutX = 800 MHzfCLKoutX = 1600 MHz
Min -30
Typ652525-158-154-148±3Vcc -0.98Vcc -1.8810865
Max 30
psdBc/HzfsUnits
Clock Distribution Section - LVPECL Clock Outputs
JitterADD
Additive RMS Jitter(Note 7)
Noise FloorDivider Noise Floor(Note 7)
tSKEWVOHVOLVOD
CLKoutX to CLKoutY (Note 8)
Equal loading and identical clockconfiguration
Termination = 50 Ω to Vcc - 2 V
Output High Voltage
Termination = 50 Ω to Vcc - 2 V
Output Low VoltageDifferential Output Voltage
(Note 9)
Vboost = 0Vboost = 1
VIH = VccVIL = 0IOH = +500 µAIOL = -500 µA
660 2.0 -5.0-40.0Vcc -0.4
965 Vcc0.85.05.0 0.4
VVmV
Digital LVTTL Interfaces (Note 10)
VIHVILIIHIILVOHVOL
High-Level Input VoltageLow-Level Input VoltageHigh-Level Input CurrentLow-Level Input CurrentHigh-Level Output VoltageLow-Level Output Voltage
VVµAµAVV
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LMK01000/LMK01010/LMK01020SymbolVIHVILIIHIILtCStCHtCWHtCWLtEStCEStEWH
Parameter
High-Level Input VoltageLow-Level Input VoltageHigh-Level Input CurrentLow-Level Input CurrentData to Clock Set Up TimeData to Clock Hold TimeClock Pulse Width HighClock Pulse Width LowClock to Enable Set Up TimeEnable to Clock Set Up TimeEnable Pulse Width High
VIH = VccVIL = 0
MICROWIRE TimingSee Data Input TimingSee Data Input TimingSee Data Input TimingSee Data Input TimingSee Data Input TimingSee Data Input TimingSee Data Input Timing
2582525252525
nsnsnsnsnsnsns
Conditions
Digital MICROWIRE Interfaces (Note 11)
1.6 -5.0-5.0
Vcc0.45.05.0
VVµAµA
Min
Typ
Max
Units
Note 4:The Electrical Characteristics tables list guaranteed specifications under the listed Recommended Operating Conditions except as otherwise modifiedor specified by the Electrical Characteristics Conditions and/or Notes. Typical specifications are estimations only and are not guaranteed.Note 5:See section 3.2 for more current consumption / power dissipation calculation information.Note 6:For all frequencies the slew rate, SLEWCLKin1, is measured between 20% and 80%.
Note 7:The noise floor of the divider is measured as the far out phase noise of the divider. Typically this offset is 40 MHz, but for lower frequencies thismeasurement offset can be as low as 5 MHz due to measurement equipment limitations. If the delay is used, then use section 1.3.Note 8:Specification is guaranteed by characterization and is not tested in production.Note 9:See characterization plots to see how this parameter varies over frequency.Note 10:Applies to GOE, LD, and SYNC*.
Note 11:Applies to CLKuWire, DATAuWire, and LEuWire.
Serial Data Timing Diagram
30042803
Data bits set on the DATAuWire signal are clocked into a shift register, MSB first, on each rising edge of the CLKuWire signal. Onthe rising edge of the LEuWire signal, the data is sent from the shift register to the addressed register determined by the LSB bits.After the programming is complete the CLKuWire, DATAuWire, and LEuWire signals should be returned to a low state. The slewrate of CLKuWire, DatauWire, and LEuWire should be at least 30 V/µs.
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LMK01000/LMK01010/LMK01020Typical Performance Characteristics
LVDS Single-Ended Peak to Peak Voltage
LVPECL Single-Ended Peak to Peak Voltage
3004280730042808
LVDS Output Noise FloorLVPECL Output Noise Floor
3004280930042810
Delay Noise Floor (Adds to Output Noise Floor)
30042811
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LMK01000/LMK01010/LMK010201.0 Functional Description
The LMK010X0 family of clock distribution devices include aprogrammable divider, a phase synchronization circuit, a pro-grammable delay, a clock output mux, and an LVDS orLVPECL output buffer in each channel. This allows multipleinteger-related and phase-adjusted copies of the reference tobe distributed to up to eight system components.
This family of devices comes in a 48-pin LLP package that ispin-to-pin and footprint compatible with other LMK02000/LMK03000 family of clocking devices.
1.1 BIAS PIN
To properly use the device, bypass Bias (pin 36) with a lowleakage 1 µF capacitor connected to Vcc. This is importantfor low noise performance.
1.2 CLKin0/CLKin0* and CLKin1/CLKin1 INPUT PORTSThe device can be driven either by the CLKin0/CLKin0* or theCLKin1/CLKin1* pins. The choice of which one to use is soft-ware selectable. These input ports must be AC coupled. Todrive these inputs in a single ended fashion, AC ground thecomplementary input with a 0.1 µF capacitor.
1.3 CLKout DELAYS
Each individual clock output includes a delay adjustment.Clock output delay registers (CLKoutX_DLY) support a 150ps step size and range from 0 to 2250 ps of total delay. Whenthe delay is enabled it adds to the output noise floor; the totaladditive noise is 10(log( 10^(Output Noise Floor/10) + 10^(Delay Noise Floor/10) ). Refer to the Typical PerformanceCharacteristics plots for the Delay Noise Floor information.1.4 LVDS/LVPECL OUTPUTS
Each LVDS or LVPECL output may be disabled individuallyby programming the CLKoutX_EN bits. All the outputs maybe disabled simultaneously by pulling the GOE pin low orprogramming EN_CLKout_Global to 0.
1.5 GLOBAL CLOCK OUTPUT SYNCHRONIZATION
The SYNC* pin synchronizes the clock outputs. When theSYNC* pin is held in a logic low state, the divided outputs arealso held in a logic low state. When the SYNC* pin goes high,the divided clock outputs are activated and will transition to ahigh state simultaneously. Clocks in the Bypassed state arenot affected by SYNC* and are always synchronized with thedivided outputs.
The SYNC* pin must be held low for greater than one clockcycle of the Frequency Input port, also known as the distribu-tion path. Once this low event has been registered, the out-puts will not reflect the low state for four more cycles. Whenthe SYNC* pin becomes high, the outputs will not simultane-ously transition high until four more distribution path clockcycles have passed. See the SYNC* timing diagram for fur-ther detail. In the timing diagram below the clocks are pro-grammed as CLKout0_MUX = Bypassed, CLKout1_MUX =Divided, CLKout1_DIV = 2, CLKout2_MUX = Divided, andCLKout2_DIV = 4.
SYNC* Timing Diagram
30042804
The SYNC* pin provides an internal pull-up resistor as shownon the functional block diagram. If the SYNC* pin is not ter-minated externally the clock outputs will operate normally. Ifthe SYNC* function is not used, clock output synchronizationis not guaranteed.
1.6 CONNECTION TO LVDS OUTPUTS
LMK01000/10 LVDS outputs can be connected in AC or DCcoupling configurations; however, in DC coupling configura-tion, proper conditions must be presented by the LVDS re-ceiver. To ensure such conditions, we recommend the usageof LVDS receivers without fail-safe or internal input bias suchas DS90LV110T. LMK01000/10 LVDS drivers will provide theadequate DC bias for the LVDS receiver. We recommend ACcoupling when using LVDS receivers with fail-safe or internalinput bias.
1.7 CLKout OUTPUT STATES
Each clock output may be individually enabled with theCLKoutX_EN bits. Each individual output enable control bit isgated with the Global Output Enable input pin (GOE) and theGlobal Output Enable bit (EN_CLKout_Global).
All clock outputs can be disabled simultaneously if the GOEpin is pulled low by an external signal or EN_CLKout_Globalis set to 0.CLKoutX_EN bit
1Don't care
01
EN_CLKout_Global bit
10Don't care
1
GOE pinLowDon't careDon't careHigh / NoConnect
Clock XOutput State
LowOffOffEnabled
When an LVDS output is in the Off state, the outputs are at avoltage of approximately 1.5 volts. When an LVPECL outputis in the Off state, the outputs are at a voltage of approximately1 volt.
1.8 GLOBAL OUTPUT ENABLE
The GOE pin provides an internal pull-up resistor. If it is notterminated externally, the clock output states are determinedby the Clock Output Enable bits (CLKoutX_EN) and theEN_CLKout_Global bit.
1.9 POWER-ON-RESET
When supply voltage to the device increases monotonicallyfrom ground to Vcc, the power-on-reset circuit sets all regis-ters to their default values, which are specified in the GeneralProgramming Information section. Voltage should be appliedto all Vcc pins simultaneously.
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LMK01000/LMK01010/LMK010202.0 General ProgrammingInformation
The LMK01000/LMK01010/LMK01020 device is pro-grammed using several 32-bit registers which control thedevice's operation. The registers consist of a data field andan address field. The last 4 register bits, ADDR[3:0] form theaddress field. The remaining 28 bits form the data field DATA[27:0].
During programming, LEuWire is low and serial data isclocked in on the rising edge of clock (MSB first). WhenLEuWire goes high, data is transferred to the register bankselected by the address field. Only registers R0 to R7 and R14need to be programmed for proper device operation.It is required to program register R14.
2.1 RECOMMENDED PROGRAMMING SEQUENCE
The recommended programming sequence involves pro-gramming R0 with the reset bit set (RESET = 1) to ensure thedevice is in a default state. It is not necessary to program R0again, but if R0 is programmed again, the reset bit is pro-grammed clear (RESET = 0). An example programming se-quence is shown below.
•Program R0 with the reset bit set (RESET = 1). This
ensures the device is in a default state. When the reset bitis set in R0, the other R0 bits are ignored.
—If R0 is programmed again, the reset bit is programmedclear (RESET = 0).
•Program R0 to R7 as necessary with desired clocks withappropriate enable, mux, divider, and delay settings.•Program R14 with global clock output bit, power downsetting.
—R14 must be programmed in accordance with theregister map as shown in the register map (see 2.2).
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2.2 LMK01000/LMK01010/LMK01020 REGISTER MAP25Data [27:0]0000000CLKout0_MUX[1:0]CLKout0_DIV[7:0]0CLKout0_DLY[3:0]CLKout1_MUX[1:0]CLKout1_DIV[7:0]CLKout1_DLY[3:0]CLKout2_MUX[1:0]CLKout2_DIV[7:0]CLKout3_MUX[1:0]CLKout3_DIV[7:0]CLKout4_MUX[1:0]CLKout4_DIV[7:0]CLKout5_MUX[1:0]CLKout6_MUX[1:0]CLKout7_MUX[1:0]01Vboost0CLKout5_DIV[7:0]CLKout2_DLY[3:0]00A3A2A102423222120191817161514131211109876543210A00RESET
0000000000000000000000CLKout3_DLY[3:0]00000000CLKout4_DLY[3:0]0R0Register
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R1000000001R2000000010R3000000011R4000000100CLKout0CLKout1CLKout2CLKout3CLKout4CLKout5CLKout6CLKout7_EN_EN_EN_EN_EN_EN_EN_EN
LMK01000/LMK01010/LMK0102011
R50000000000000CLKout5_DLY[3:0]0101R60000000000000CLKout6_DIV[7:0]CLKout6_DLY[3:0]0110R70000000000000CLKout7_DIV[7:0]01010100CLKout7_DLY[3:0]0000111R910100000000001001POWERDOWN
EN_CLKout_GlobalCLKin_SELECT
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LMK01000/LMK01010/LMK010202.3 REGISTER R0 to R7
Registers R0 through R7 control the eight clock outputs. Reg-ister R0 controls CLKout0, Register R1 controls CLKout1, andso on. There is one additional bit in register R0 called RESET.
Aside from this, the functions of these bits are identical. TheX in CLKoutX_MUX, CLKoutX_DIV, CLKoutX_DLY, andCLKoutX_EN denote the actual clock output which may befrom 0 to 7.
Default Register Settings after Power-on-Reset
Bit Name
RESETCLKoutX_MUXCLKoutX_ENCLKoutX_DIVCLKoutX_DLYCLKin_SELECTEN_CLKout_GlobalPOWERDOWN
DefaultBit Value
00010010
BypassedDisabledDivide by 20 psCLKin1
Normal - CLKouts normalNormal - Device active
Bit State
No reset, normal operation
Bit Description
Reset to power on defaultsCLKoutX mux modeCLKoutX enableCLKoutX clock divideCLKoutX clock delaySelect CLKin0 or CLKin1Global clock output enableDevice power down
CLKoutX_DIV[7:0]
0000.1
0000.1
0000.1
0000.1
0000.1
0011.1
1100.1
0101.1R14R0 to R7RegisterR0
BitLocation
3118:171615:87:4282726
Clock OutputDivider value
46810...510
2.3.1 RESET Bit -- R0 only
This bit is only in register R0. The use of this bit is optionaland it should be set to '0' if not used. Setting this bit to a '1'forces all registers to their power-on-reset condition andtherefore automatically clears this bit. If this bit is set, all otherR0 bits are ignored and R0 needs to be programmed again ifused with its proper values and RESET = 0.
2.3.2 CLKoutX_MUX[1:0] -- Clock Output MultiplexersThese bits control the Clock Output Multiplexer for each clockoutput. Changing between the different modes changes theblocks in the signal path and therefore incurs a delay relativeto the Bypassed mode. The different MUX modes and asso-ciated delays are listed below.CLKoutX_MUX
[1:0]
01
Mode
Added DelayRelative toBypassed Mode
0 ps100 ps400 ps
(In addition to theprogrammeddelay)500 ps
(In addition to theprogrammeddelay)
Bypassed (default)
Divided
2.3.4 CLKoutX_DLY[3:0] -- Clock Output Delays
These bits control the delay stages for each clock output. Inorder for these delays to be active, the respectiveCLKoutX_MUX (See 2.3.2) bit must be set to either \"Delayed\"or \"Divided and Delayed\" mode. By adding the delay block tothe output path a fixed delay of approximately 400 ps is in-curred in addition to the delay shown in the table below.
CLKoutX_DLY[3:0]
0123456789101112131415
Delay (ps)0 (default)150300450600750900105012001350150016501800195021002250
2Delayed
3
Divided andDelayed
2.3.3 CLKoutX_DIV[7:0] -- Clock Output Dividers
These bits control the clock output divider value. In order forthese dividers to be active, the respective CLKoutX_MUX(See 2.3.2) bit must be set to either \"Divided\" or \"Divided andDelayed\" mode. After all the dividers are programed, theSYNC* pin must be used to ensure that all edges of the clockoutputs are aligned (See 1.7). By adding the divider block tothe output path a fixed delay of approximately 100 ps is in-curred.
The actual Clock Output Divide value is twice the binary valueprogrammed as listed in the table below.
CLKoutX_DIV[7:0]
00
00
00
00
00
00
00
01
Clock OutputDivider value
Invalid2 (default)
12
2.3.5 CLKoutX_EN bit -- Clock Output Enables
These bits control whether an individual clock output is en-abled or not. If the EN_CLKout_Global bit is set to zero or ifGOE pin is held low, all CLKoutX_EN bit states will be ignoredand all clock outputs will be disabled.
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LMK01000/LMK01010/LMK01020CLKoutX_EN bit
01
Conditions
CLKoutX State
2.4.2 POWERDOWN Bit -- Device Power Down
This bit can power down the device. Enabling this bit powersdown the entire device and all blocks, regardless of the stateof any of the other bits or pins.POWERDOWN bit
0
2.4 REGISTER R9 and R14
The LMK01000 family requires register R14 to be pro-grammed as shown in the register map (see 2.2). R9 onlyneeds to be programmed if Vboost is set to 1.
2.4.1 Vboost - Voltage Boost Bit
Enabling this bit sets all clock outputs in voltage boost modewhich increases the voltage at these outputs. This can im-prove the noise floor performance of the output, but alsoincreases current consumption, and can cause the outputs tobe too high to meet the LVPECL/LVDS specifications.Vboostbit0
fCLKoutX < 1300
MHzRecommended tohit voltage levelspecifications forLVPECL/LVDSVoltage May
overdrive LVPECL/LVDS
specifications, butnoise floor is about2-4 dB better andcurrent
consumption isincreased
1300 MHz ≤fCLKoutX <1500 MHz
1500 MHz ≤fCLKoutX ≤1600 MHz
1
Mode
Normal Operation (default)Entire Device Powered Down
EN_CLKout_GlobalDisabled (default)
bit = 1
GOE pin = High / NoEnabled
Connect 1
2.4.3 INPUT_MUX Bit -- Device CLKin SelectThis bit determines which CLKin pin is used.
CLKin bit
01
ModeCLKin1 (default)
CLKin0
Insufficient voltage level forLVDS/LVPECL
specifications, but savescurrentVoltage issufficient forLVDS/LEVPECLspecifications. Currentconsumptionis increased,but noise flooris about thesame.
Insufficientvoltage forLVDS/LVPECL
specifications, but stillhigher thanwhen
Vboost=0.Increasedcurrent
consumption.
1
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LMK01000/LMK01010/LMK010203.0 Application Information
3.1 SYSTEM LEVEL DIAGRAM
The following shows the LMK01000LMK01010/LMK01020 ina typical application. In this setup the clock may be divided,skewed, and redistributed.
30042870
FIGURE 1. Typical Application
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LMK01000/LMK01010/LMK010203.2 CURRENT CONSUMPTION / POWER DISSIPATIONCALCULATIONS ( Vcc = 3.3 V, TA = 25° C )
CurrentConsumption at 3.3 V(mA)
199917.84017.400.51.55.38.55.89.985.863.6108323.8212.8390.4
PowerDissipatedin device(mW)
62.729.729.758.77238.301.655.017.528.019.132.7223.1209.9236.4768.5702.3808.3
PowerDissipated inLVPECL emitterresistors (mW)
----6019.1-- ----60-120300-480
BlockCondition
Core CurrentAll outputs disabled. Includes input buffer currents.
Low clock bufferThe low clock buffer is enabled anytime one of CLKout0(internal)through CLKout3 are enabledHigh clockThe high clock buffer is enabled anytime one of the CLKout4buffer (internal)through CLKout7 are enabled
LVDS output, Bypassed modeLVPECL output, Bypassed mode(includes 120 Ω emitter resistors)
Output buffers
LVPECL output, disabled mode(includes 120 Ω emitter resistors)LVPECL output, disabled mode.
No emitter resistors placed; open outputs
VboostDivide circuitryper outputDelay circuitryper output
Additional current per channel dueLVPECL Outputto setting Vboost from 0 to 1.LVDS OutputDivide enabled, divide = 2Divide enabled, divide > 2Delay enabled, delay < 8Delay enabled, delay > 7
Entire deviceLMK01000
CLKout0 &LMK01010CLKout4enabled inLMK01020Bypassed mode
Entire deviceLMK01000all outputsLMK01010enabled with no
delay and divideLMK01020value of 2
From the above table, the current can be calculated in anyconfiguration. For example, the current for the entire devicewith 1 LVDS (CLKout0) & 1 LVPECL (CLKout4) output in By-passed mode can be calculated by adding up the followingblocks: core current, low clock buffer, high clock buffer, oneLVDS output buffer current, and one LVPECL output buffercurrent. There will also be one LVPECL output drawing emit-ter current, but some of the power from the current draw isdissipated in the external 120 Ω resistors which doesn't addto the power dissipation budget for the device. If delays ordivides are switched in, then the additional current for thesestages needs to be added as well.
For power dissipated by the device, the total current enteringthe device is multiplied by the voltage at the device minus thepower dissipated in any emitter resistors connected to any of
the LVPECL outputs. If no emitter resistors are connected tothe LVPECL outputs, this power will be 0 watts. For example,in the case of 1 LVDS (CLKout0) & 1 LVPECL (CLKout4) op-erating at 3.3 volts for LMK01000, we calculate 3.3 V × (10 +9 + 9 + 17.8 + 40) mA = 3.3 V × 85.8 mA = 283.1 mW. Becausethe LVPECL output (CLKout4) has the emitter resistorshooked up and the power dissipated by these resistors is 60mW, the total power dissipation is 283.1 mW - 60 mW = 223.1mW. When the LVPECL output is active, ~1.9 V is the averagevoltage on each output as calculated from the LVPECL Voh& Vol typical specification. Therefore the power dissipated ineach emitter resistor is approximately (1.9 V)2 / 120 Ω = 30mW. When the LVPECL output is disabled, the emitter resis-tor voltage is ~1.07 V. Therefore the power dissipated in eachemitter resistor is approximately (1.07 V)2 / 120 Ω = 9.5 mW.
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LMK01000/LMK01010/LMK010203.3 THERMAL MANAGEMENT
Power consumption of the LMK01000/LMK01010/LMK01020can be high enough to require attention to thermal manage-ment. For reliability and performance reasons the die tem-perature should be limited to a maximum of 125 °C. That is,as an estimate, TA (ambient temperature) plus device powerconsumption times θJA should not exceed 125 °C.
The package of the device has an exposed pad that providesthe primary heat removal path as well as excellent electricalgrounding to the printed circuit board. To maximize the re-moval of heat from the package a thermal land pattern in-cluding multiple vias to a ground plane must be incorporatedon the PCB within the footprint of the package. The exposedpad must be soldered down to ensure adequate heat con-duction out of the package. A recommended land and viapattern is shown in Figure 2. More information on solderingLLP packages can be obtained at www.national.com.
To minimize junction temperature it is recommended that asimple heat sink be built into the PCB (if the ground planelayer is not exposed). This is done by including a copper areaof about 2 square inches on the opposite side of the PCB fromthe device. This copper area may be plated or solder coatedto prevent corrosion but should not have conformal coating (ifpossible), which could provide thermal insulation. The viasshown in Figure 2 should connect these top and bottom cop-per layers and to the ground layer. These vias act as “heatpipes” to carry the thermal energy away from the device sideof the board to where it can be more effectively dissipated.
30042873
FIGURE 2.
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LMK01000/LMK01010/LMK01020Physical Dimensions inches (millimeters) unless otherwise noted
Leadless Leadframe Package (Bottom View)
48 Pin LLP (SQA48A) Package
Order NumberLMK01000ISQLMK01000ISQXLMK01010ISQLMK01010ISQXLMK01020ISQLMK01020ISQX
Package Marking
K01000 IK01000 IK01010 IK01010 IK01020 IK01020 I
Packing
250 Unit Tape and Reel2500 Unit Tape and Reel250 Unit Tape and Reel2500 Unit Tape and Reel250 Unit Tape and Reel2500 Unit Tape and Reel
LVDS Outputs
3388--LVPECLOutputs
55--88
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LMK01000/LMK01010/LMK01020 1.6 GHz High Performance Clock Buffer, Divider, andDistributorNotes
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