MC100LVE310
3.3VECL 2:8 DifferentialFanout Buffer
Description
The MC100LVE310 is a low voltage, low skew 2:8 differential ECLfanout buffer designed with clock distribution in mind. The devicefeatures fully differential clock paths to minimize both device andsystem skew. The LVE310 offers two selectable clock inputs to allowfor redundant or test clocks to be incorporated into the system clocktrees.
To ensure that the tight skew specification is met it is necessary thatboth sides of the differential output are terminated into 50 W, even ifonly one side is being used. In most applications all eight differentialpairs will be used and therefore terminated. In the case where fewerthan eight pairs are used it is necessary to terminate at least the outputpairs adjacent to the output pair being used in order to maintainminimum skew. Failure to follow this guideline will result in smalldegradations of propagation delay (on the order of 10 − 20 ps) of theoutputs being used, while not catastrophic to most designs this willresult in an increase in skew. Note that the package corners isolateoutputs from one another such that the guideline expressed aboveholds only for outputs on the same side of the package.
The MC100LVE310, as with most ECL devices, can be operatedfrom a positive VCC supply in LVPECL mode. This allows theLVE310 to be used for high performance clock distribution in +3.3 Vsystems. Designers can take advantage of the LVE310’s performanceto distribute low skew clocks across the backplane or the board. In aPECL environment series or Thevenin line terminations are typicallyused as they require no additional power supplies, if paralleltermination is desired a terminating voltage of VCC − 2.0 V will needto be provided. For more information on using PECL, designersshould refer to Application Note AN1406/D.
The VBB pin, an internally generated voltage supply, is available tothis device only. For single-ended input conditions, the unuseddifferential input is connected to VBB as a switching reference voltage.VBB may also rebias AC coupled inputs. When used, decouple VBBand VCC via a 0.01 mF capacitor and limit current sourcing or sinkingto 0.5 mA. When not used, VBB should be left open.
Features
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PLCC−28FN SUFFIXCASE 776
MARKING DIAGRAM*
1
MC100LVE310GAWLYYWW
AWLYYWWG = Assembly Location = Wafer Lot = Year
= Work Week
= Pb−Free Package
*For additional marking information, refer to Application Note AND8002/D.
ORDERING INFORMATION
See detailed ordering and shipping information in the packagedimensions section on page 5 of this data sheet.
•200 ps Part−to−Part Skew•50 ps Output−to−Output Skew•PECL Mode Operating Range: •
•Q Output will Default LOW with All Inputs Open or ••
at VEE
The 100 Series Contains Temperature CompensationPb−Free Packages are Available*
VCC = 3.0 V to 3.8 V with VEE = 0 VNECL Mode Operating Range:
VCC = 0 V with VEE = −3.0 V to −3.8 V
*For additional information on our Pb−Free strategy and soldering details, pleasedownload the ON Semiconductor Soldering and Mounting TechniquesReference Manual, SOLDERRM/D.
1
Publication Order Number:
MC100LVE310/D
© Semiconductor Components Industries, LLC, 2006
November, 2006 − Rev. 4
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MC100LVE310
Q025
VEE
CLK_SEL
CLKaVCCCLKaVBBCLKb
2627281234
5CLKb6NC
7
8
9Q7
10Q611Q6
Q024
Q1VCCOQ123
22
21
Q220
Q219181716
Q3Q3Q4VCCOQ4Q5Q5CLKaCLKaCLKbCLKbCLK_SELQ0Q0Q1Q1Q2Q2Q3Q3Q4Q4Q5Q5Q6Q6Q7Q7VBB
Pinout: 28−Lead PLCC
(Top View)
15141312
Q7VCCO
Warning: All VCC, VCCO, and VEE pins must be externallyconnected to Power Supply to guarantee proper operation.
Figure 1. Logic Diagram and Pinout AssignmentTable 1. PIN DESCRIPTIONPINCLKa, CLKa; ,CLKb CLKbQ0:7, Q0:7CLK_SELVBBVCC, VCCOVEENCFUNCTIONECL Differential Input ClocksECL Differential OutputsECL Input Clock SelectReference Voltage OutputPositive SupplyNegative SupplyNo ConnectFigure 2. Logic Symbol
Table 2. TRUTH TABLE
CLK_SEL
LH
Input Clock
CLKa SelectedCLKb Selected
Table 3. ATTRIBUTES
Characteristics
Internal Input Pulldown ResistorInternal Input Pullup ResistorESD Protection
Human Body Model
Machine Model
Pb PkgLevel 1
ValueYESN/A> 2 kV> 200 V
Pb−Free PkgLevel 3
Moisture Sensitivity, Indefinite Time Out of Drypack (Note 1)
PLCC−28
Flammability RatingTransistor Count
Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test1.For additional information, see Application Note AND8003/D.
Oxygen Index: 28 to 34
UL 94 V−0 @ 0.125 in
212 Devices
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MC100LVE310
Table 4. MAXIMUM RATINGS
SymbolVCCVEEVIIoutIBBTATstgqJAqJCTsol
Parameter
PECL Mode Power SupplyNECL Mode Power SupplyPECL Mode Input VoltageNECL Mode Input VoltageOutput CurrentVBB Sink/Source
Operating Temperature RangeStorage Temperature Range
Thermal Resistance (Junction−to−Ambient)Thermal Resistance (Junction−to−Case)Wave Solder
PbPb−Free
0 lfpm500 lfpmStandard Board
PLCC−28PLCC−28PLCC−28
Condition 1VEE = 0 VVCC = 0 VVEE = 0 VVCC = 0 VContinuousSurge
VI v VCCVI w VEE
Condition 2
Rating8 to 0−8 to 06 to 0−6 to 050100±0.5−40 to +85−65 to +150
63.543.522 to 26 ± 5%
265265
UnitVVVVmAmAmA°C°C°C/W°C/W°C/W°C
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above theRecommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affectdevice reliability.
Table 5. LVPECL DC CHARACTERISTICS VCC = 3.3 V, VEE = 0 V (Note 2)
−40°C
SymbolIEEVOHVOLVIHVILVBBVIHCMRIIHIIL
Characteristic
Power Supply CurrentOutput HIGH Voltage (Note 3)Output LOW Voltage (Note 3)Input HIGH Voltage (Single−Ended)Input LOW Voltage (Single−Ended)Output Voltage Reference
Input HIGH Voltage Common Mode
Range (Differential Configuration) (Note 4)Input HIGH CurrentInput LOW Current
0.522151470213514901.921.8Min
Typ5522951605
Max6024201745242018252.042.9150
0.522751490213514901.921.8Min
25°CTyp5523451595
Max6024201680242018252.042.9150
0.522751490213514901.921.8Min
85°CTyp6523451595
Max7024201680242018252.042.9150
UnitmAmVmVmVmVVVmAmA
NOTE:Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limitvalues are applied individually under normal operating conditions and not valid simultaneously.
2.Input and output parameters vary 1:1 with VCC. VEE can vary ±0.3 V.3.Outputs are terminated through a 50 W resistor to VCC − 2 V.
4.VIHCMR min varies 1:1 with VEE, max varies 1:1 with VCC. VIHCMR is defined as the range within which the VIH level may vary, with the devicestill meeting the propagation delay specification. The VIL level must be such that the peak to peak voltage is less than 1.0 V and greater thanor equal to VPP(min).
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MC100LVE310
Table 6. LVNECL DC CHARACTERISTICS VCC = 5.0 V, VEE = −3.3 V (Note 5)
−40°C
SymbolIEEVOHVOLVIHVILVBBVIHCMR
Characteristic
Power Supply CurrentOutput HIGH Voltage (Note 6)Output LOW Voltage (Note 6)Input HIGH Voltage (Single−Ended)Input LOW Voltage (Single−Ended)Output Voltage Reference
Input HIGH Voltage Common ModeRange (Differential Configuration)(Note 7)
Input HIGH CurrentInput LOW Current
0.5−1085−1830−1165−1810−1.38−1.5Min
Typ55−1005−1695
Max60−880−1555−880−1475−1.26−0.4
−1025−1810−1165−1810−1.38−1.5Min
25°CTyp55−955−1705
Max60−880−1620−880−1475−1.26−0.4
−1025−1810−1165−1810−1.38−1.5Min
85°CTyp65−955−1705
Max70−880−1620−880−1475−1.26−0.4
UnitmAmVmVmVmVVV
IIHIIL
150
0.5
150
0.5
150mAmA
NOTE:Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limitvalues are applied individually under normal operating conditions and not valid simultaneously.
5.Input and output parameters vary 1:1 with VCC. VEE can vary ±0.3 V.6.Outputs are terminated through a 50 W resistor to VCC − 2 V.
7.VIHCMR min varies 1:1 with VEE, max varies 1:1 with VCC. VIHCMR is defined as the range within which the VIH level may vary, with the devicestill meeting the propagation delay specification. The VIL level must be such that the peak to peak voltage is less than 1.0 V and greater thanor equal to VPP(min).
Table 7. AC CHARACTERISTICS VCC = 3.3 V; VEE = 0.0 V or VCC = 0.0 V; VEE = −3.3 V (Note 8)
−40°C
SymbolfmaxtPLHtPHLtskewtJITTERVPPtr/tf
Characteristic
Maximum Toggle Frequency
Propagation Delay to Output
IN (Differential Configuration) (Note 9)
IN (Single−Ended) (Note 10)Within−Device Skew (Note 11)
Part−to−Part Skew (Differential Configuration)Cycle−to−Cycle JitterInput Swing (Note12)
Output Rise/Fall Time (20%−80%)
500200
TBD
1000600
500200
525500Min
TypTBD
72575075250
TBD
1000600
500200
550550
Max
Min
25°CTypTBD
75080050200
TBD
1000600
575600
Max
Min
85°CTypTBD
77585050200Max
UnitGHzps
pspsmVps
NOTE:Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limitvalues are applied individually under normal operating conditions and not valid simultaneously.
8. VEE can vary ±0.3 V.
9.The differential propagation delay is defined as the delay from the crossing points of the differential input signals to the crossing point of thedifferential output signals.
10.The single-ended propagation delay is defined as the delay from the 50% point of the input signal to the 50% point of the output signal.11.The within−device skew is defined as the worst case difference between any two similar delay paths within a single device.
12.VPP(min) is defined as the minimum input differential voltage which will cause no increase in the propagation delay. The VPP(min) is AC limitedfor the LVE310 as a differential input as low as 50 mV will still produce full ECL levels at the output.
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MC100LVE310
QDriverDeviceQZo = 50 W50 W50 WDZo = 50 WDReceiverDeviceVTT
VTT = VCC − 2.0 V
Figure 3. Typical Termination for Output Driver and Device Evaluation(See Application Note AND8020/D − Termination of ECL Logic Devices.)
ORDERING INFORMATION
Device
MC100LVE310FNMC100LVE310FNGMC100LVE310FNR2MC100LVE310FNR2G
PackagePLCC−28PLCC−28(Pb−Free)PLCC−28PLCC−28(Pb−Free)
Shipping†37 Units / Rail37 Units / Rail500 / Tape & Reel500 / Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel PackagingSpecifications Brochure, BRD8011/D.
Resource Reference of Application Notes
AN1405/DAN1406/DAN1503/DAN1504/DAN1568/DAN1672/DAND8001/DAND8002/DAND8020/DAND8066/DAND8090/D
−ECL Clock Distribution Techniques−Designing with PECL (ECL at +5.0 V)−ECLinPSt I/O SPiCE Modeling Kit−Metastability and the ECLinPS Family−Interfacing Between LVDS and ECL−The ECL Translator Guide−Odd Number Counters Design−Marking and Date Codes−Termination of ECL Logic Devices−Interfacing with ECLinPS
−AC Characteristics of ECL Devices
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MC100LVE310
PACKAGE DIMENSIONS
PLCC−28FN SUFFIX
PLASTIC PLCC PACKAGE
CASE 776−02ISSUE E
Y BRKDZ−L−−M−B0.007 (0.180) MTL−M SUNS−N−0.007 (0.180) MTL−M SNSW281DVXVIEW D−DG10.010 (0.250) STL−M SNSAZREGG10.010 (0.250) STL−M SN
S0.007 (0.180) MTL−M S0.007 (0.180) MTL−M SNNSSH0.007 (0.180) MTL−M SNSCK10.004 (0.100)−T−SEATINGPLANEJKFVIEW S
0.007 (0.180) MTL−M SNSVIEW SNOTES:
1.DATUMS −L−, −M−, AND −N− DETERMINEDWHERE TOP OF LEAD SHOULDER EXITSPLASTIC BODY AT MOLD PARTING LINE.2.DIMENSION G1, TRUE POSITION TO BE
MEASURED AT DATUM −T−, SEATING PLANE.3.DIMENSIONS R AND U DO NOT INCLUDEMOLD FLASH. ALLOWABLE MOLD FLASH IS0.010 (0.250) PER SIDE.
4.DIMENSIONING AND TOLERANCING PERANSI Y14.5M, 1982.
5.CONTROLLING DIMENSION: INCH.
6.THE PACKAGE TOP MAY BE SMALLER THANTHE PACKAGE BOTTOM BY UP TO 0.012(0.300). DIMENSIONS R AND U AREDETERMINED AT THE OUTERMOSTEXTREMES OF THE PLASTIC BODYEXCLUSIVE OF MOLD FLASH, TIE BARBURRS, GATE BURRS AND INTERLEADFLASH, BUT INCLUDING ANY MISMATCHBETWEEN THE TOP AND BOTTOM OF THEPLASTIC BODY.
7.DIMENSION H DOES NOT INCLUDE DAMBARPROTRUSION OR INTRUSION. THE DAMBARPROTRUSION(S) SHALL NOT CAUSE THE HDIMENSION TO BE GREATER THAN 0.037(0.940). THE DAMBAR INTRUSION(S) SHALLNOT CAUSE THE H DIMENSION TO BESMALLER THAN 0.025 (0.635).
DIMABCEFGHJKRUVWXYZG1K1INCHESMINMAX0.4850.4950.4850.4950.1650.1800.0900.1100.0130.0190.050 BSC0.0260.0320.020−−−0.025−−−0.4500.4560.4500.4560.0420.0480.0420.0480.0420.056−−−0.0202 _10 _0.4100.4300.040−−−MILLIMETERSMINMAX12.3212.5712.3212.574.204.572.292.790.330.481.27 BSC0.660.810.51−−−0.64−−−11.4311.5811.4311.581.071.211.071.211.071.42−−−0.502 _10 _10.4210.921.02−−−http://onsemi.com
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MC100LVE310
ECLinPS is a trademark of Semiconductor Components Industries, LLC (SCILLC).
ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further noticeto any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liabilityarising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. Alloperating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rightsnor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applicationsintended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. ShouldBuyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or deathassociated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an EqualOpportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
LITERATURE FULFILLMENT:Literature Distribution Center for ON SemiconductorP.O. Box 5163, Denver, Colorado 80217 USAPhone: 303−675−2175 or 800−344−3860 Toll Free USA/CanadaFax: 303−675−2176 or 800−344−3867 Toll Free USA/CanadaEmail: orderlit@onsemi.comN. American Technical Support: 800−282−9855 Toll FreeUSA/CanadaEurope, Middle East and Africa Technical Support:Phone: 421 33 790 2910Japan Customer Focus CenterPhone: 81−3−5773−3850ON Semiconductor Website: www.onsemi.comOrder Literature: http://www.onsemi.com/orderlitFor additional information, please contact your localSales Representativehttp://onsemi.com7MC100LVE310/D
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