ADF4107锁相环

2021-11-19 来源：好走旅游网

FEATURES

7.0 GHz bandwidth

2.7 V to 3.3 V power supply

Separate charge pump supply (VP) allows extended tuning voltage in 3 V systems

Programmable dual-modulus prescaler 8/9, 16/17, 32/33, 64/65

Programmable charge pump currents Programmable antibacklash pulsewidth 3-wire serial interface

Analog and digital lock detect

Hardware and software power-down mode

PLL Frequency SynthesizerADF4107GENERAL DESCRIPTION

The ADF4107 frequency synthesizer can be used to implement local oscillators in the up-conversion and down-conversion sections of wireless receivers and transmitters. It consists of a low-noise digital PFD (phase frequency detector), a precision charge pump, a programmable reference divider, programmable A and B counters, and a dual-modulus prescaler (P/P + 1). The A (6-bit) and B (13-bit) counters, in conjunction with the dual-modulus prescaler (P/P + 1), implement an N divider (N = BP + A). In addition, the 14-bit reference counter

(R counter), allows selectable REFIN frequencies at the PFD input. A complete PLL (phase-locked loop) can be implemented if the synthesizer is used with an external loop filter and VCO (voltage controlled oscillator). Its very high bandwidth means that frequency doublers can be eliminated in many high frequency systems, simplifying system architecture and reducing cost.

APPLICATIONS

Broadband wireless access Satellite systems Instrumentation Wireless LANs

Base stations for wireless radio

FUNCTIONAL BLOCK DIAGRAM

AVDDDVDDVPCPGNDREFERENCEREFIN14-BITR COUNTER14R COUNTERLATCHCLKDATALE24-BIT INPUTREGISTERFUNCTIONLATCHA, B COUNTERLATCH1313-BITB COUNTERLOADLOAD6-BITA COUNTER6CEAGNDDGNDM3M2M1SDOUTLOCKDETECTCURRENTSETTING 1CPI3CPI2CPI1CURRENTSETTING 2CPI6CPI5CPI4HIGH Z19AVDDMUXMUXOUTPHASEFREQUENCYDETECTORRSETCHARGEPUMPCP22FROMSDOUTFUNCTIONLATCHN = BP + ARFINARFINBPRESCALERP/P + 1ADF4107

Figure 1.

Rev. 0

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective companies.

ADF4107

TABLE OF CONTENTS

ADF4107—Specifications................................................................3 Timing Characteristics.....................................................................5 Absolute Maximum Ratings............................................................5 Pin Configurations and Functional Descriptions........................6 Typical Performance Characteristics.............................................7 Functional Description....................................................................9 Reference Input Stage...................................................................9 RF Input Stage...............................................................................9 Prescaler (P/P + 1)........................................................................9 A and B Counters.........................................................................9 R Counter......................................................................................9 Phase Frequency Detector and Charge Pump........................10 MUXOUT and Lock Detect......................................................10 Input Shift Register.....................................................................10

Latch Summary...........................................................................11 Reference Counter Latch Map..................................................12 AB Counter Latch Map.............................................................13 Function Latch Map...................................................................14 Initialization Latch Map............................................................15 Function Latch............................................................................16 Initialization Latch.....................................................................17 Applications.....................................................................................18 Local Oscillator for LMDS Base Station Transmitter............18 Interfacing...................................................................................19 PCB Design Guidelines for Chip Scale Package....................19 Outline Dimensions.......................................................................20 ESD Caution....................................................................................20 Ordering Guide...............................................................................20

REVISION HISTORY

Revision 0: Initial Version

Rev. 0 | Page 2 of 20

ADF4107

ADF4107—SPECIFICATIONS

Table 1. (AVDD = DVDD = 3 V ± 10%, AVDD ≤ VP ≤ 5.5 V, AGND = DGND = CPGND = 0 V, RSET = 5.1 kΩ, dBm referred to 50 Ω, TA = TMAX to TMIN, unless otherwise noted.)

B Chips2 Unit Test Parameter B Conditions/Comments 1

Version (Typ)

RF CHARACTERISTICS RF Input Frequency (RFIN)3 1.0/7.0 1.0/7.0 GHz min/max See Figure 18 for input circuit. RF Input Sensitivity –5/+5 –5/+5 dBm min/max

300 300 MHz max Maximum Allowable Prescaler

Output Frequency REFIN CHARACTERISTICS REFIN Input Frequency 20/250 20/250 MHz min/max For f < 20 MHz, use dc-coupled square wave (0 to VDD). REFIN Input Sensitivity5 0.8/VDD 0.8/VDD V p-p min/max AC-coupled; when dc-coupled, 0 to VDD, max (CMOS

compatible).

REFIN Input Capacitance 10 10 pF max REFIN Input Current ±100 ±100 µA max PHASE DETECTOR Phase Detector Frequency6 104 104 MHz max CHARGE PUMP Programmable; see Figure 25. ICP Sink/Source High Value 5 5 mA typ With RSET = 5.1 kΩ Low Value 625 625 µA typ Absolute Accuracy 2.5 2.5 % typ With RSET = 5.1 kΩ RSET Range 3.0/11 3.0/11 kΩ typ See Figure 25. ICP Three-State Leakage 1 1 nA typ

2 2 % typ 0.5 V ≤ VCP ≤ VP – 0.5 V Sink and Source Current

Matching ICP vs. VCP 1.5 1.5 % typ 0.5 V ≤ VCP ≤ VP – 0.5 V ICP vs. Temperature 2 2 % typ VCP = VP/2 LOGIC INPUTS VIH, Input High Voltage 1.4 1.4 V min VIL, Input Low Voltage 0.6 0.6 V max IINH, IINL, Input Current ±1 ±1 µA max CIN, Input Capacitance 10 10 pF max LOGIC OUTPUTS VOH, Output High Voltage 1.4 1.4 V min Open-drain output chosen; 1 kΩ pull-up resistor to 1.8 V. VOH, Output High Voltage VDD – 0.4 VDD – 0.4 V min CMOS output chosen. IOH 100 100 µA max VOL, Output Low Voltage 0.4 0.4 V max IOL = 500 µA POWER SUPPLIES AVDD 2.7/3.3 2.7/3.3 V min/V max DVDD AVDD AVDD VP AVDD/5.5 AVDD/5.5 V min/V max AVDD ≤ VP ≤5.5V 7

IDD (AIDD + DIDD) 17 15 mA max 15 mA typ IP 0.4 0.4 mA max TA = 25°C

Power-Down Mode (AIDD + DIDD) 10 10 µA typ

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ADF4107

B Chips2 Unit Test Parameter B Conditions/Comments 1

Version (Typ)

NOISE CHARACTERISTICS ADF4107 Phase Noise Floor9 –174 –174 dBc/Hz typ @ 25 kHz PFD Frequency –166 –166 dBc/Hz typ @ 200 kHz PFD Frequency –159 –159 dBc/Hz typ @ 1 MHz PFD Frequency

Phase Noise Performance @ VCO Output

900 MHz Output –93 –93 dBc/Hz typ @ 1 kHz offset and 200 kHz PFD Frequency 6400 MHz Output12 –76 –76 dBc/Hz typ @ 1 kHz offset and 200 kHz PFD Frequency

6400 MHz Output –83 –83 dBc/Hz typ @ 1 kHz offset and 1 MHz PFD Frequency Spurious Signals

900 MHz Output –90/–92 –90/–92 dBc typ @ 200 kHz/400kHz and 200 kHz PFD Frequency 6400 MHz Output12 –65/–70 –65/–70 dBc typ @ 200 kHz/400kHz and 200 kHz PFD Frequency

6400 MHz Output –70/–75 –70/–75 dBc typ @ 1 MHz/2MHz and 1 MHz PFD Frequency

Operating temperature range (B Version) is –40°C to +85°C. 2

The B Chip specifications are given as typical values. 3

Use a square wave for lower frequencies, below the minimum stated. 4

This is the maximum operating frequency of the CMOS counters. The prescaler value should be chosen to ensure that the RF input is divided down to a frequency that is less than this value. 5

AVDD = DVDD = 3 V. 6

Guaranteed by design. Sample tested to ensure compliance. 7

TA = 25°C; AVDD = DVDD = 3 V; P = 32; RFIN = 7.0 GHz. 8

TA = 25°C; AVDD = DVDD = 3.3 V; R = 16383; A = 63; B = 891; P = 32; RFIN = 7.0 GHz. 9

The synthesizer phase noise floor is estimated by measuring the in-band phase noise at the output of the VCO and subtracting 20logN (where N is the N divider value). 10

The phase noise is measured with the EVAL-ADF4107EB1 Evaluation Board and the HP8562E Spectrum Analyzer. The spectrum analyzer provides the REFIN for the synthesizer (fREFOUT = 10 MHz @ 0 dBm). 11

fREFIN = 10 MHz; fPFD = 200 kHz; Offset Frequency = 1 kHz; fRF = 900 MHz; N = 4500; Loop B/W = 20 kHz. 12

fREFIN = 10 MHz; fPFD = 200 kHz; Offset Frequency = 1 kHz; fRF = 6400 MHz; N = 32000; Loop B/W = 20 kHz. 13

fREFIN = 10 MHz; fPFD = 1 MHz; Offset Frequency = 1 kHz; fRF = 6400 MHz; N = 6400; Loop B/W = 100 kHz.

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ADF4107

TIMING CHARACTERISTICS

Table 2. (AVDD = DVDD = 3 V ± 10%, AVDD ≤ VP ≤ 5.5 V, AGND = DGND = CPGND = 0 V, RSET = 5.1 kΩ, dBm referred to 50 Ω, TA = TMAX to TMIN, unless otherwise noted.) 1

Parameter imit2 (B Version) t1 10 t2 10 t3 25 t4 25 t5 10 t6 20

Guaranteed by design but not production tested. 2

Operating temperature range (B Version) is –40°C to +85°C.

Unit ns min ns min ns min ns min ns min ns min

Test Conditions/Comments DATA to CLOCK Setup Time DATA to CLOCK Hold Time CLOCK High Duration CLOCK Low Duration CLOCK to LE Setup Time LE Pulsewidth

t3CLOCKt4t1DATADB23 (MSB)DB22t2DB2DB1(CONTROLBITC2)DB0 (LSB)(CONTROL BIT C1)t6LEt5LE Figure 2. Timing Diagram

ABSOLUTE MAXIMUM RATINGS

Table 3. (TA = 25°C, unless otherwise noted.)

Parameter Rating Stresses above those listed under Absolute Maximum Ratings AVDD to GND1 –0.3 V to +3.6 V may cause permanent damage to the device. This is a stress AVDD to DVDD –0.3 V to +0.3 V rating only; functional operation of the device at these or any VP to GND –0.3 V to +5.8 V other conditions above those listed in the operational sections VP to AVDD –0.3 V to +5.8 V of this specification is not implied. Exposure to absolute Digital I/O Voltage to GND –0.3 V to VDD + 0.3 V maximum rating conditions for extended periods may affect Analog I/O Voltage to GND –0.3 V to VP + 0.3 V device reliability. REFIN, RFINA, RFINB to GND –0.3 V to VDD + 0.3 V

This device is a high performance RF integrated circuit with an Operating Temperature Range

ESD rating of <2 kV, and it is ESD sensitive. Proper precautions Industrial (B Version) –40°C to +85°C

should be taken for handling and assembly. Storage Temperature Range –65°C to +125°C

Maximum Junction Temperature 150°C

TSSOP θJA Thermal Impedance 150.4°C/W CSP θJA Thermal Impedance 122°C/W Lead Temperature, Soldering

Vapor Phase (60 sec) 215°C

Infrared (15 sec) 220°C

Transistor Count

CMOS 6425 Bipolar 303

GND = AGND = DGND = 0 V.

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ADF4107

PIN CONFIGURATIONS AND FUNCTIONAL DESCRIPTIONS

TSSOPRSET1CP2CPGND3AGND4161514CSP(Chip Scale Package)20 CP19RSET18VP17DVDD16DVDDVPDVDDMUXOUTCPGND 1AGND 2AGND 3RFINB4RFINA513LETOP VIEWRFINB5(Not to Scale)12DATA11109ADF4107PIN 1INDICATORRFINA6AVDD7REFIN8CLKCEDGNDADF4107TOP VIEW15 MUXOUT14LE13 DATA12 CLK11 CE

Figure 3. ADF4107 TSSOP (Top View)

AVDD 6AVDD 7REFIN 8DGND 9DGND 10

Figure 4. ADF4107 Chip Scale Package

Table 4. Pin Functional Descriptions

Mnemonic Function Connecting a resistor between this pin and CPGND sets the maximum charge pump output current. The nominal voltage potential at the RSET pin is 0.66 V. The relationship between ICP and RSET is 25.5RSET ICPMAX= RSETso, with RSET = 5.1 kΩ, ICP MAX = 5 mA. CP Charge Pump Output. When enabled, this pin provides ±ICP to the external loop filter, which in turn drives the external VCO. CPGND Charge Pump Ground. This is the ground return path for the charge pump. AGND Analog Ground. This is the ground return path of the prescaler. Complementary Input to the RF Prescaler. This point must be decoupled to the ground plane with a small bypass capacitor, RFINB typically 100 pF. See Figure 18. RFINA Input to the RF Prescaler. This small signal input is ac-coupled to the external VCO. Analog Power Supply. This voltage may range from 2.7 V to 3.3 V. Decoupling capacitors to the analog ground plane should AVDD be placed as close as possible to this pin. AVDD must be the same value as DVDD. Reference Input. This is a CMOS input with a nominal threshold of VDD/2 and a dc equivalent input resistance of 100 kΩ. See REFIN Figure 17. This input can be driven from a TTL or CMOS crystal oscillator or it can be ac-coupled. DGND Digital Ground. Chip Enable. A logic low on this pin powers down the device and puts the charge pump output into three-state mode. Taking CE the pin high will power up the device, depending on the status of the power-down bit, F2. Serial Clock Input. This serial clock is used to clock in the serial data to the registers. The data is latched into the 24-bit shift CLK register on the CLK rising edge. This input is a high impedance CMOS input. Serial Data Input. The serial data is loaded MSB first with the two LSBs being the control bits. This input is a high impedance DATA CMOS input. Load Enable, CMOS Input. When LE goes high, the data stored in the shift registers is loaded into one of the four latches, the LE latch being selected using the control bits. This multiplexer output allows either the lock detect, the scaled RF, or the scaled reference frequency to be accessed MUXOUT externally. Digital Power Supply. This may range from 2.7 V to 3.3 V. Decoupling capacitors to the digital ground plane should be placed DVDD as close as possible to this pin. DVDD must be the same value as AVDD. Charge Pump Power Supply. This voltage should be greater than or equal to VDD. In systems where VDD is 3 V, it can be set to 5 VP V and used to drive a VCO with a tuning range of up to 5 V. Rev. 0 | Page 6 of 20

ADF4107

–40–50–60PHASE NOISE– dBc/HzTYPICAL PERFORMANCE CHARACTERISTICS

10dB/DIVRL =–40dBc/HzRMS NOISE = 0.36o–70–80–90–100–110–120–130–140100HzFREQUENCY OFFSET FROM 900MHz CARRIER1MHz Figure 5. Parameter Data for the RF Input

Figure 8. Integrated Phase Noise (900 MHz, 200 kHz, 20 kHz)

0VDD = 3VVP = 3V0REF LEVEL =–14.0dBm–10–20OUTPUT POWER– dB–5RF INPUT POWER– dBm–10–30–40–50–60–70–80VDD = 3V, VP = 5VICP = 5mAPFD FREQUENCY = 200kHzLOOP BANDWIDTH = 20kHzRES BANDWIDTH = 1kHzVIDEO BANDWIDTH = 1kHzSWEEP = 2.5 SECONDSAVERAGES = 30–15TA = +85C–20TA = +25oCo–25TA =–40oC012345RF INPUT FREQUENCY– GHz67–91.0dBc/Hz–90–100–400kHz–200kHz900MHz+200kHzFREQUENCY+400kHz–30

Figure 6. Input Sensitivity

Figure 9. Reference Spurs (900 MHz, 200 kHz, 20 kHz)

0REF LEVEL =–14.3dBm0REF LEVEL =–10dBm–10–20OUTPUT POWER– dBOUTPUT POWER– dB–30–40–50–60–70–80–90–100–2kHz–1kHzVDD = 3V, VP = 5VICP = 5mAPFD FREQUENCY = 200kHzLOOP BANDWIDTH = 20kHzRES BANDWIDTH = 10HzVIDEO BANDWIDTH = 10HzSWEEP = 1.9 SECONDSAVERAGES = 10–10–20–30–40–50–60–70–80–90VDD = 3V, VP = 5VICP = 5mAPFD FREQUENCY = 1MHzLOOP BANDWIDTH = 100kHzRES BANDWIDTH = 10HzVIDEO BANDWIDTH = 10HzSWEEP = 1.9 SECONDSAVERAGES = 10–93.0dBc/Hz–83.0dBc/Hz900MHzFREQUENCY+1kHz+2kHz–100–2kHz–1kHz

6400MHzFREQUENCY+1kHz+2kHz

Figure 7. Phase Noise (900 MHz, 200 kHz, 20 kHz) Figure 10. Phase Noise (6.4 GHz, 1 MHz, 100 kHz)

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ADF4107

–40–50–60PHASE NOISE– dBc/Hz–510dB/DIVRL =–40dBc/HzRMS NOISE = 1.85oFIRST REFERENCE SPUR– dBc–15–25–35–45–55–65–75–85–95VDD = 3VVP = 5V–70–80–90–100–110–120–130–140100HzFREQUENCY OFFSET FROM 6400MHz CARRIER1MHz–10501

23TUNING VOLTAGE– V45

Figure 11. Integrated Phase Noise (6.4 GHz, 1 MHz, 100 kHz) Figure 14. Reference Spurs vs. VTUNE (6.4 GHz, 1 MHz, 100 kHz)

0REF LEVEL =–10dBm–10–20OUTPUT POWER– dB–120–30–40–50–60–70–80–90–100–2MHz–1MHzPHASE NOISE– dBc/HzVDD = 3V, VP = 5VICP = 5mAPFD FREQUENCY = 1MHzLOOP BANDWIDTH = 100kHzRES BANDWIDTH = 1kHzVIDEO BANDWIDTH = 1kHzSWEEP = 13 SECONDSAVERAGES = 1VDD = 3VVP = 5V–130–140–150–66.0dBc/Hz–65.0dBc/Hz–160–1706400MHzFREQUENCY+1MHz+2MHz–18010k

100k1M10MPHASE DETECTOR FREQUENCY– Hz100M

Figure 12. Reference Spurs (6.4 GHz, 1 MHz, 100 kHz) Figure 15. Phase Noise (referred to CP output) vs. PFD Frequency

–60VDD = 3VVP = 3V–7065432ICP– mAVP = 5VICP SETTLING = 5mAPHASE NOISE– dBc/Hz10–1–2–80–90–3–4–5–100–40–6–200204060oTEMPERATURE–C8010000.51.01.52.0

2.53.0VCP– V3.54.04.55.0

Figure 13. Phase Noise (6.4 GHz, 1 MHz, 100 kHz) vs. Temperature

Figure 16. Charge Pump Output Characteristics

Rev. 0 | Page 8 of 20

ADF4107

synchronous 4/5 core. A minimum divide ratio is possible for fully contiguous output frequencies. This minimum is

determined by P, the prescaler value, and is given by: (P2 – P).

FUNCTIONAL DESCRIPTION

Reference Input Stage

The Reference Input stage is shown in Figure 17. SW1 and SW2 are normally closed switches. SW3 is normally open. When power-down is initiated, SW3 is closed and SW1 and SW2 are opened. This ensures that there is no loading of the REFIN pin on power-down.

POWER-DOWNCONTROLA and B Counters

The A and B CMOS counters combine with the dual-modulus prescaler to allow a wide ranging division ratio in the PLL feedback counter. The counters are specified to work when the prescaler output is 300 MHz or less. Thus, with an RF input frequency of 4.0 GHz, a prescaler value of 16/17 is valid but a value of 8/9 is not valid.

NCREFIN100kΩSW2NCSW1TO R COUNTERBUFFERPulse Swallow Function The A and B counters, in conjunction with the dual-modulus prescaler, make it possible to generate output frequencies that are spaced only by the reference frequency divided by R. The equation for the VCO frequency is as follows: fVCO=[(P×B)+A]×

NOSW3

Figure 17. Reference Input Stage

RF Input Stage

The RF input stage is shown in Figure 18. It is followed by a 2-stage limiting amplifier to generate the CML clock levels needed for the prescaler.

BIASGENERATOR500Ω1.6VAVDD500ΩfREFIN RfVCO Output frequency of external voltage controlled

oscillator (VCO).

P B A

Preset modulus of dual-modulus prescaler (8/9, 16/17, etc.).

Preset divide ratio of binary 13-bit counter (3 to 8191).

Preset divide ratio of binary 6-bit swallow counter (0 to 63).

RFINAfREFIN External reference frequency oscillator.

N = BP + ARFINB13-BIT BCOUNTERFROM RFINPUT STAGEPRESCALERP/P + 1MODULUSCONTROLN DIVIDERLOADLOAD6-BIT ACOUNTERTO PFDAGND

Figure 18. RF Input Stage

Prescaler (P/P + 1)

The dual-modulus prescaler (P/P + 1), along with the A and B counters, enables the large division ratio, N, to be realized (N = BP + A). The dual-modulus prescaler, operating at CML levels, takes the clock from the RF input stage and divides it down to a manageable frequency for the CMOS A and B counters. The prescaler is programmable. It can be set in software to 8/9, 16/17, 32/33, or 64/65. It is based on a

Figure 19. A and B Counters

R Counter

The 14-bit R counter allows the input reference frequency to be divided down to produce the reference clock to the phase frequency detector (PFD). Division ratios from 1 to 16,383 are allowed.

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ADF4107

Phase Frequency Detector and Charge Pump

The phase frequency detector (PFD) takes inputs from the R counter and N counter (N = BP + A) and produces an output proportional to the phase and frequency difference between them. Figure 20 is a simplified schematic. The PFD includes a programmable delay element that controls the width of the

antibacklash pulse. This pulse ensures that there is no dead zone in the PFD transfer function and minimizes phase noise and reference spurs. Two bits in the reference counter latch, ABP2 and ABP1, control the width of the pulse. See Figure 23.

VPCHARGEPUMPThe N-channel open-drain analog lock detect should be operated with an external pull-up resistor of 10 kΩ nominal. When lock has been detected, this output will be high with narrow, low-going pulses.

DVDDIANALOG LOCK DETECTDIGITAL LOCK DETECTR COUNTER OUTPUTN COUNTER OUTPUTSDOUTMUXCONTROLMUXOUTHID1Q1U1UPDGND

R DIVIDERFigure 21. MUXOUT Circuit

CLR1

PROGRAMMABLEDELAYABP2ABP1U3CPInput Shift Register

The ADF4107 digital section includes a 24-bit input shift

register, a 14-bit R counter, and a 19-bit N counter, comprising a 6-bit A counter and a 13-bit B counter. Data is clocked into the 24-bit shift register on each rising edge of CLK. The data is clocked in MSB first. Data is transferred from the shift register to one of four latches on the rising edge of LE. The destination latch is determined by the state of the two control bits (C2, C1) in the shift register. These are the two LSBs, DB1 and DB0, as shown in the timing diagram of Figure 2. The truth table for these bits is shown in Table 5. Figure 22 shows a summary of how the latches are programmed. Table 5. C2, C1 Truth Table

Control Bits

Data Latch

C2 C1 0 0 R Counter 0 1 N Counter (A and B) 1 0 Function Latch (Including Prescaler) 1 1 nitialization Latch

HICLR2DOWND2Q2U2N DIVIDERCPGND

Figure 20. PFD Simplified Schematic and Timing (in Lock)

MUXOUT and Lock Detect

The output multiplexer on the ADF4107 allows the user to access various internal points on the chip. The state of

MUXOUT is controlled by M3, M2, and M1 in the function latch. Figure 25 shows the full truth table. Figure 21 shows the MUXOUT section in block diagram form.

Lock Detect MUXOUT can be programmed for two types of lock detect: digital lock detect and analog lock detect.

Digital lock detect is active high. When the lock detect precision (LDP) bit in the R counter latch is set to 0, digital lock detect is set high when the phase error on three consecutive phase detector (PD) cycles is less than 15 ns. With LDP set to 1, five consecutive cycles of less than 15 ns are required to set the lock detect. It will stay set high until a phase error of greater than 25 ns is detected on any subsequent PD cycle.

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ADF4107

Latch Summary

REFERENCE COUNTER LATCH

LOCKDETECTPRECISIONRESERVEDTESTMODE BITSANTI-BACKLASHWIDTH14-BIT REFERENCE COUNTERCONTROLBITSDB23DB22DB21DB20DB19DB18DB17DB16DB15DB14DB13DB12DB11DB10X00LDPT2T1ABP2ABP1R14R13R12R11R10R9DB9R8DB8R7DB7R6DB6R5DB5R4DB4R3DB3R2DB2R1DB1DB0C2 (0)C1 (0)N COUNTER LATCHCP GAINRESERVED13-BIT B COUNTER6-BIT A COUNTERCONTROLBITSDB23DB22DB21DB20DB19DB18DB17DB16DB15DB14DB13DB12DB11DB10XXG1B13B12B11B10B9B8B7B6B5B4B3DB9B2DB8B1DB7A6DB6A5DB5A4DB4A3DB3A2DB2A1DB1DB0C2 (0)C1 (1)FUNCTION LATCHFASTLOCKENABLEFASTLOCKMODECP THREE-STATEPDPOLARITYPRESCALERVALUECURRENTSETTING2COUNTERRESETDB2F1POWER-DOWN 2POWER-DOWN 1CURRENTSETTING1TIMER COUNTERCONTROLMUXOUTCONTROLCONTROLBITSDB23DB22DB21DB20DB19DB18DB17DB16DB15DB14DB13DB12DB11DB10P2P1PD2CPI6CPI5CPI4CPI3CPI2CPI1TC4TC3TC2TC1F5DB9F4DB8F3DB7F2DB6M3DB5M2DB4M1DB3PD1DB1DB0C2 (1)C1 (0)INITIALIZATION LATCH

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ADF4107

Reference Counter Latch Map

LOCKDETECTPRECISIONTESTMODE BITSANTI-BACKLASHWIDTHCONTROLBITSRESERVED14-BIT REFERENCE COUNTERDB23DB22DB21DB20DB19DB18DB17DB16DB15DB14DB13DB12DB11DB10X00LDPT2T1ABP2ABP1R14R13R12R11R10R9DB9R8DB8R7DB7R6DB6R5DB5R4DB4R3DB3R2DB2R1DB1C2 (0)DB0C1 (0)X = DON’T CARER140000...1111R130000...1111R120000...1111........................................................................................................................R30001...1111R20110...0011R11010...0101DIVIDE RATIO1234...16380163811638216383ABP20011ABP10101ANTIBACKLASH PULSEWIDTH2.9ns1.3ns6.0ns2.9nsTEST MODE BITSSHOULD BE SETTO 00 FOR NORMALOPERATION.LDP01OPERATIONTHREE CONSECUTIVE CYCLES OF PHASE DELAY LESS THAN15ns MUST OCCUR BEFORE LOCK DETECT IS SET.FIVE CONSECUTIVE CYCLES OF PHASE DELAY LESS THAN15ns MUST OCCUR BEFORE LOCK DETECT IS SET.BOTH OF THESE BITSMUST BE SET TO 0 FORNORMAL OPERATION. Figure 23. Reference Counter Latch Map

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ADF4107

AB Counter Latch Map

CP GAINCONTROLBITSRESERVED13-BIT B COUNTER6-BIT A COUNTERDB23XDB22XDB21G1DB20B13DB19B12DB18B11DB17B10DB16B9DB15B8DB14B7DB13B6DB12B5DB11B4DB10B3DB9B2DB8B1DB7A6DB6A5DB5A4DB4A3DB3A2DB2A1DB1DB0C2 (0)C1 (1)X = DON’T CAREA60000...1111A50000...1111........................................................................................................................A20011...0011A10101...0101A COUNTERDIVIDE RATIO0123...60616263B130000...1111B120000...1111B110000...1111..............................................................................................................B30000...1111B20011...0011B10101...0101B COUNTER DIVIDE RATIONOT ALLOWEDNOT ALLOWEDNOT ALLOWED3...8188818981908191F4 (FUNCTION LATCH)CP GAINFASTLOCK ENABLEOPERATION00110101CHARGE PUMP CURRENTSETTING 1 IS PERMANENTLY USED.CHARGE PUMP CURRENTSETTING 2 IS PERMANENTLY USED.CHARGE PUMP CURRENTSETTING 1 IS USED.CHARGE PUMP CURRENT ISSWITCHED TO SETTING 2. THETIME SPENT IN SETTING 2 ISDEPENDENT ON WHICH FASTLOCKMODE IS USED. SEE FUNCTIONLATCH DESCRIPTION.N = BP + A, P IS PRESCALER VALUE SET IN THE FUNCTIONLATCH. B MUST BE GREATER THAN OR EQUAL TO A. FORCONTINUOUSLY ADJACENT VALUES OF (N× FREF), AT THEOUTPUT, NMIN IS (P2– P).THESE BITS ARE NOT USEDBY THE DEVICE AND AREDON'T CARE BITS. Figure 24. AB Counter Latch Map

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ADF4107

Function Latch Map

FASTLOCKMODEFASTLOCKENABLECP THREE-STATEPDPOLARITYPRESCALERVALUECURRENTSETTING2CURRENTSETTING1COUNTERRESETDB2F1POWER-DOWN 2POWER-DOWN 1TIMER COUNTERCONTROLMUXOUTCONTROLCONTROLBITSDB23DB22DB21DB20DB19DB18DB17DB16DB15DB14DB13DB12DB11DB10P2P1PD2CPI6CPI5CPI4CPI3CPI2CPI1TC4TC3TC2TC1F5DB9F4DB8F3DB7F2DB6M3DB5M2DB4M1DB3PD1DB1C2 (1)DB0C1 (0)F201PHASE DETECTORPOLARITYNEGATIVEPOSITIVEF101COUNTEROPERATIONNORMALR, A, B COUNTERSHELD IN RESETF301CHARGE PUMPOUTPUTNORMALTHREE-STATEF4011F5X01FASTLOCK MODEFASTLOCK DISABLEDFASTLOCK MODE 1FASTLOCK MODE 2TC40000000011111111TC30000111100001111TC20011001100110011TC10101010101010101TIMEOUT(PFD CYCLES)371115192327313539434751555963M300001111M200110011M101010101OUTPUTTHREE-STATE OUTPUTDIGITAL LOCK DETECT(ACTIVE HIGH)N DIVIDER OUTPUTDVDDR DIVIDER OUTPUTN-CHANNEL OPEN-DRAINLOCK DETECTSERIAL DATA OUTPUTDGNDCPI6CPI300001111CPI5CPI200110011CP14CPI1010101013kΩ1.062.123.184.245.306.367.428.50ICP (mA)5.1kΩ0.6251.251.8752.53.1253.754.3755.011kΩ0.2890.5800.8701.1601.4501.7302.0202.320CE PIN0111P20011P10101PD2XX01PD1X011MODEASYNCHRONOUS POWER-DOWNNORMAL OPERATIONASYNCHRONOUS POWER-DOWNSYNCHRONOUS POWER-DOWNPRESCALER VALUE8/916/1732/3364/65 Figure 25. Function Latch Map

Rev. 0 | Page 14 of 20

ADF4107

FASTLOCKMODEFASTLOCKENABLECP THREE-STATEPDPOLARITYCOUNTERRESETDB2F1Initialization Latch Map

POWER-DOWN 2PRESCALERVALUECURRENTSETTING2CURRENTSETTING1POWER-DOWN 1TIMER COUNTERCONTROLMUXOUTCONTROLCONTROLBITSDB23DB22DB21DB20DB19DB18DB17DB16DB15DB14DB13DB12DB11DB10P2P1PD2CPI6CPI5CPI4CPI3CPI2CPI1TC4TC3TC2TC1F5DB9F4DB8F3DB7F2DB6M3DB5M2DB4M1DB3PD1DB1C2 (1)DB0C1 (1)F201PHASE DETECTORPOLARITYNEGATIVEPOSITIVEF101COUNTEROPERATIONNORMALR, A, B COUNTERSHELD IN RESETF301CHARGE PUMPOUTPUTNORMALTHREE-STATEF4011F5X01FASTLOCK MODEFASTLOCK DISABLEDFASTLOCK MODE 1FASTLOCK MODE 2TC40000000011111111TC30000111100001111TC20011001100110011TC10101010101010101TIMEOUT(PFD CYCLES)371115192327313539434751555963M300001111M200110011M101010101OUTPUTTHREE-STATE OUTPUTDIGITAL LOCK DETECT(ACTIVE HIGH)N DIVIDER OUTPUTDVDDR DIVIDER OUTPUTN-CHANNEL OPEN-DRAINLOCK DETECTSERIAL DATA OUTPUTDGNDCPI6CPI300001111CPI5CPI200110011CP14CPI1010101013kΩ1.062.123.184.245.306.367.428.50ICP (mA)5.1kΩ0.6251.251.8752.53.1253.754.3755.011kΩ0.2890.5800.8701.1601.4501.7302.0202.320CE PIN0111P20011P10101PD2XX01PD1X011MODEASYNCHRONOUS POWER-DOWNNORMAL OPERATIONASYNCHRONOUS POWER-DOWNSYNCHRONOUS POWER-DOWNPRESCALER VALUE8/916/1732/3364/65 Figure 26. Initialization Latch Map

Rev. 0 | Page 15 of 20

ADF4107

Function Latch

The on-chip function latch is programmed with C2 and C1 set to 1 and 0, respectively. Figure 25 shows the input data format for programming the function latch.

Fastlock Mode Bit DB10 of the function latch is the fastlock mode bit. When fastlock is enabled, this bit determines which fastlock mode is used. If the fastlock mode bit is 0, then Fastlock Mode 1 is

selected; and if the fastlock mode bit is 1, then Fastlock Mode 2 is selected.

Counter Reset DB2 (F1) is the counter reset bit. When this bit is 1, the R counter and the AB counters are reset. For normal operation, this bit should be 0. Upon powering up, the F1 bit needs to be disabled (set to 0). Then, the N counter resumes counting in close alignment with the R counter. (The maximum error is one prescaler cycle).

Fastlock Mode 1 The charge pump current is switched to the contents of Current Setting 2.

The device enters fastlock by having a 1 written to the CP gain bit in the AB counter latch. The device exits fastlock by having a 0 written to the CP gain bit in the AB counter latch.

Power-Down DB3 (PD1) and DB21 (PD2) provide programmable power-down modes. They are enabled by the CE pin.

When the CE pin is low, the device is immediately disabled regardless of the states of PD2 and PD1.

In the programmed asynchronous power-down, the device powers down immediately after latching a 1 into the PD1 bit, with the condition that PD2 has been loaded with a 0. In the programmed synchronous power-down, the device power-down is gated by the charge pump to prevent unwanted frequency jumps. Once the power-down is enabled by writing a 1 into PD1 (on condition that a 1 has also been loaded to PD2), then the device will go into power-down on the occurrence of the next charge pump event.

When a power-down is activated (either synchronous or

asynchronous mode, including CE pin activated power-down), the following events occur:

• • • • • • •

All active dc current paths are removed.

The R, N, and timeout counters are forced to their load state conditions.

The charge pump is forced into three-state mode. The digital lock detect circuitry is reset. The RFIN input is debiased.

The reference input buffer circuitry is disabled.

The input register remains active and capable of loading and latching data.

Fastlock Mode 2 The charge pump current is switched to the contents of Current Setting 2.

The device enters fastlock by having a 1 written to the CP gain bit in the AB counter latch. The device exits fastlock under the control of the timer counter. After the timeout period

determined by the value in TC4–TC1, the CP gain bit in the AB counter latch is automatically reset to 0 and the device reverts to normal mode instead of fastlock. See Figure 25 for the timeout periods.

Timer Counter Control The user has the option of programming two charge pump currents. The intent is that Current Setting 1 is used when the RF output is stable and the system is in a static state. Current Setting 2 is meant to be used when the system is dynamic and in a state of change (i.e., when a new output frequency is programmed).

The normal sequence of events is as follows:

The user initially decides what the preferred charge pump

currents are going to be. For example, the choice may be 2.5 mA as Current Setting 1 and 5 mA as Current Setting 2.

At the same time it must be decided how long the secondary current is to stay active before reverting to the primary current. This is controlled by the timer counter control bits, DB14–DB11 (TC4–TC1) in the function latch. The truth table is given in Figure 25.

Now, to program a new output frequency, the user simply

programs the AB counter latch with new values for A and B. At the same time, the CP gain bit can be set to 1, which sets the charge pump with the value in CPI6–CPI4 for a period of time determined by TC4–TC1. When this time is up, the charge pump current reverts to the value set by CPI3–CPI1. At the same time the CP gain bit in the AB counter latch is reset to 0 and is now ready for the next time that the user wishes to change the frequency.

MUXOUT Control The on-chip multiplexer is controlled by M3, M2, M1 on the ADF4107. Figure 25 shows the truth table.

Fastlock Enable Bit DB9 of the function latch is the fastlock enable bit. Fastlock is enabled only when this bit is 1.

Rev. 0 | Page 16 of 20

ADF4107

Initialization Latch Method

Apply VDD.

Program the initialization latch (11 in two LSBs of input word). Make sure that the F1 bit is programmed to 0.

Next, do a function latch load (10 in two LSBs of the control word), making sure that the F1 bit is programmed to a 0. Then do an R load (00 in two LSBs). Then do an AB load (01 in two LSBs).

When the Initialization Latch is loaded, the following occurs: 1. The function latch contents are loaded.

2. An internal pulse resets the R, AB, and timeout counters to

load-state conditions and also three-states the charge pump. Note that the prescaler band gap reference and the oscillator input buffer are unaffected by the internal reset pulse, allowing close phase alignment when counting resumes.

3. Latching the first AB counter data after the initialization

word will activate the same internal reset pulse. Successive AB loads will not trigger the internal reset pulse unless there is another initialization. CE Pin Method Apply VDD.

Bring CE low to put the device into power-down. This is an asychronous power-down in that it happens immediately. Program the function latch (10). Program the R counter latch (00). Program the AB counter latch (01).

Bring CE high to take the device out of power-down. The R and AB counters will now resume counting in close alignment.

Note that after CE goes high, a duration of 1 µs may be required for the prescaler band gap voltage and oscillator input buffer bias to reach steady state.

CE can be used to power the device up and down in order to check for channel activity. The input register does not need to be reprogrammed each time the device is disabled and enabled as long as it has been programmed at least once after VDD was initially applied. Counter Reset Method Apply VDD.

Do a Function Latch Load (10 in two LSBs). As part of this, load 1 to the F1 bit. This enables the counter reset. Do an R counter load (00 in two LSBs). Do an AB counter load (01 in two LSBs).

Do a Function latch load (10 in two LSBs). As part of this, load 0 to the F1 bit. This disables the counter reset.

This sequence provides the same close alignment as the

initialization method. It offers direct control over the internal reset. Note that counter reset holds the counters at load point and three-states the charge pump, but does not trigger synchronous power-down.

Note that there is an enable feature on the timer counter. It is enabled when Fastlock Mode 2 is chosen by setting the fastlock mode bit (DB10) in the function latch to 1.

Charge Pump Currents CPI3, CPI2, and CPI1 program Current Setting 1 for the charge pump. CPI6, CPI5, and CPI4 program Current Setting 2 for the charge pump. The truth table is given in Figure 25.

Prescaler Value P2 and P1 in the function latch set the prescaler values. The prescaler value should be chosen so that the prescaler output frequency is always less than or equal to 300 MHz. Thus, with an RF frequency of 4 GHz, a prescaler value of 16/17 is valid but a value of 8/9 is not valid.

PD Polarity This bit sets the phase detector polarity bit. See Figure 25.

CP Three-State This bit controls the CP output pin. With the bit set high, the CP output is put into three-state. With the bit set low, the CP output is enabled.

Initialization Latch

The initialization latch is programmed when C2 and C1 are set to 1 and 1. This is essentially the same as the function latch (programmed when C2, C1 = 1, 0).

However, when the initialization latch is programmed an additional internal reset pulse is applied to the R and AB

counters. This pulse ensures that the AB counter is at load point when the AB counter data is latched and the device will begin counting in close phase alignment.

If the latch is programmed for synchronous power-down (CE pin is high; PD1 bit is high; PD2 bit is low), the internal pulse also triggers this power-down. The prescaler reference and the oscillator input buffer are unaffected by the internal reset pulse and so close phase alignment is maintained when counting resumes.

When the first AB counter data is latched after initialization, the internal reset pulse is again activated. However, successive AB counter loads after this will not trigger the internal reset pulse.

Device Programming after Initial Power-Up After initially powering up the device, there are three ways to program the device.

Rev. 0 | Page 17 of 20

ADF4107

APPLICATIONS

Local Oscillator for LMDS Base Station Transmitter

Figure 27 below shows the ADF4107 being used with a VCO to produce the LO for an LMDS base station.

The reference input signal is applied to the circuit at FREFIN and, in this case, is terminated in 50 Ω. A typical base station system would have either a TCXO or an OCXO driving the reference input without any 50 Ω termination.

To have a channel spacing of 1 MHz at the output, the 10 MHz reference input must be divided by 10, using the on-chip reference divider of the ADF4107.

The charge pump output of the ADF4107 (Pin 2) drives the loop filter. In calculating the loop filter component values, a number of items need to be considered. In this example, the loop filter was designed so that the overall phase margin for the system would be 45°.

Other PLL system specifications are: KD = 5.0 mA KV = 80 MHz/V

Loop Bandwidth = 70 kHz FPFD = 1 MHz N = 6300

Extra Reference Spur Attenuation = 10 dB

All of these specifications are needed and used to derive the loop filter component values shown in Figure 27.

Figure 27 gives a typical phase noise performance of

−83 dBc/Hz at 1 kHz offset from the carrier. Spurs are better than −70 dBc.

The loop filter output drives the VCO, which, in turn, is fed back to the RF input of the PLL synthesizer and also drives the RF output terminal. A T-circuit configuration provides 50 Ω matching between the VCO output, the RF output, and the RFIN terminal of the synthesizer.

In a PLL system, it is important to know when the system is in lock. In Figure 27, this is accomplished by using the MUXOUT signal from the synthesizer. The MUXOUT pin can be programmed to monitor various internal signals in the synthesizer. One of these is the LD or lock detect signal.

VDDVPRFOUT100pF715161000pFFREFIN51ΩAVDDDVDDVP1000pFCP28REFIN100pF1.7kΩ214100pF1018Ω18ΩVCC7.5kΩ47pFV956ME0118ΩADF4107820pFCECLKDATALERFINA611, 3, 4, 5, 7, 8,9, 11, 12, 13MUXOUT14LOCKDETECT100pF51ΩSPI COMPATIBLE SERIAL BUSRSETCPGNDRFINB5AGND5.1kΩDGND34100pFNOTEDECOUPLING CAPACITORS (0.1µF/10pF) ON AVDD, DVDD,VP OF THE ADF4107 AND ON VCC OF THE V956ME01 HAVEBEEN OMITTED FROM THE DIAGRAM TO AID CLARITY.9

Figure 27. 6.3 GHz Local Oscillator Using the ADF4107

Rev. 0 | Page 18 of 20

ADF4107

ADSP2181 Interface Figure 29 shows the interface between the ADF4107 and the ADSP21xx Digital Signal Processor. The ADF4107 needs a 24-bit serial word for each latch write. The easiest way to accomplish this using the ADSP21xx family is to use the autobuffered transmit mode of operation with alternate

framing. This provides a means for transmitting an entire block of serial data before an interrupt is generated. Set up the word length for 8 bits and use three memory locations for each 24-bit word. To program each 24-bit latch, store the three 8-bit bytes, enable the autobuffered mode, and then write to the transmit register of the DSP. This last operation initiates the autobuffer transfer.

SCLKDTCLKDATALECEI/O FLAGSMUXOUT(LOCK DETECT)Interfacing

The ADF4107 has a simple SPI™ compatible serial interface for writing to the device. CLK, DATA, and LE control the data transfer. When LE (Latch Enable) goes high, the 24 bits that have been clocked into the input register on each rising edge of CLK will get transferred to the appropriate latch. See Figure 2 for the timing diagram and Table 5 for the Latch truth table. The maximum allowable serial clock rate is 20 MHz. This means that the maximum update rate possible for the device is 833 kHz or one update every 1.2 µs. This is certainly more than adequate for systems that have typical lock times in hundreds of microseconds.

ADuC812 Interface Figure 28 shows the interface between the ADF4107 and the ADuC812 MicroConverter®. Since the ADuC812 is based on an 8051 core, this interface can be used with any 8051 based microcontroller. The MicroConverter is set up for SPI master mode with CPHA = 0. To initiate the operation, the I/O port driving LE is brought low. Each latch of the ADF4107 needs a 24-bit word. This is accomplished by writing three 8-bit bytes from the MicroConverter to the device. When the third byte has been written, the LE input should be brought high to complete the transfer.

On first applying power to the ADF4107, it needs four writes (one each to the initialization latch, function latch, R counter latch, and N counter latch) for the output to become active. I/O port lines on the ADuC812 are also used to control power-down (CE input) and to detect lock (MUXOUT configured as lock detect and polled by the port input).

When operating in the mode described, the maximum

SCLOCK rate of the ADuC812 is 4 MHz. This means that the maximum rate at which the output frequency can be changed will be 166 kHz.

SCLOCKMOSICLKDATALECEMUXOUT(LOCK DETECT)ADSP21XXTFSADF4107 Figure 29. ADSP-21xx to ADF4107 Interface

PCB Design Guidelines for Chip Scale Package

The lands on the chip scale package (CP-20) are rectangular. The printed circuit board pad for these should be 0.1 mm longer than the package land length and 0.05 mm wider than the package land width. The land should be centered on the pad. This will ensure that the solder joint size is maximized. The bottom of the chip scale package has a central thermal pad. The thermal pad on the printed circuit board should be at least as large as this exposed pad. On the printed circuit board, there should be a clearance of at least 0.25 mm between the thermal pad and the inner edges of the pad pattern. This will ensure that shorting is avoided.

Thermal vias may be used on the printed circuit board thermal pad to improve thermal performance of the package. If vias are used, they should be incorporated in the thermal pad at 1.2 mm pitch grid. The via diameter should be between 0.3 mm and 0.33 mm and the via barrel should be plated with 1 oz. copper to plug the via.

ADuC812I/O PORTSADF4107 Figure 28. ADuC812 to ADF4107 Interface

The user should connect the printed circuit board thermal pad to AGND.

Rev. 0 | Page 19 of 20

ADF4107

OUTLINE DIMENSIONS

5.105.004.901694.504.404.30186.40BSCPIN10.150.050.65BSC0.300.19COPLANARITY0.101.20MAX0.200.09SEATINGPLANE8°0°0.750.600.45COMPLIANTTOJEDECSTANDARDSMO-153AB

Figure 30. 16-Lead Thin Shrink Small Outline Package [TSSOP] (RU-16)—Dimensions shown in millimeters

4.0BSC SQ0.60MAXPIN1INDICATORTOPVIEW3.75BSCSQ0.750.550.3511100.60MAX1615201BOTTOMVIEW652.252.10SQ1.9512°MAX1.000.900.80SEATINGPLANE

0.50BSC

1.00MAX0.65NOM0.050.020.00

0.300.230.18

COPLANARITY

0.08

0.20REF

COMPLIANTTOJEDECSTANDARDSMO-220-VGGD-1

Figure 31. 20-Lead Frame Chip Scale Package [LFCSP] (CP-20)—Dimensions shown in millimeters

ESD CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.

ORDERING GUIDE Model ADF4107BRU ADF4107BRU–REEL ADF4107BRU–REEL7 ADF4107BCP ADF4107BCP–REEL ADF4107BCP–REEL7 Temperature Range –40°C to + 85°C –40°C to + 85°C –40°C to + 85°C –40°C to + 85°C –40°C to + 85°C –40°C to + 85°C Package Option RU-16 RU-16 RU-16 CP-20 CP-20 CP-20 RU = Thin Shrink Small Outline Package (TSSOP) CP = Chip Scale Package Contact the factory for chip availability. Note that aluminum bond wire should not be used with the ADF4107 die. © 2003 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective companies. C03338-0-5/03(0) Rev. 0 | Page 20 of 20

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