7516资料

7516 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

REJ03B0042-0101Z

Rev.1.01Jul 01, 2003

DESCRIPTION

The 7516 group is the 8-bit microcomputer based on the 740 fam-ily core technology.

The 7516 group is designed for the household products and officeautomation equipment and includes serial I/O functions, 8-bittimer, A-D converter, and I2C-BUS interface.

FEATURES

qBasic machine-language instructions......................................71qMinimum instruction execution time..................................0.5 µs(at 8 MHz oscillation frequency)qMemory size

ROM...............................................................16 K to 32 K bytesRAM....................................................................512 to 1 K bytesqProgrammable input/output ports............................................40qInterrupts.................................................17 sources, 16 vectorsqTimers.............................................................................8-bit ✕ 4qSerial I/O1...................8-bit ✕ 1 (UART or Clock-synchronized)qSerial I/O2...................................8-bit ✕ 1(Clock-synchronized)qMulti-master I2C-BUS interface (option)......................1 channelqPWM...............................................................................8-bit ✕ 1qA-D converter...............................................10-bit ✕ 8 channelsqWatchdog timer............................................................16-bit ✕ 1

qClock generating circuit.....................................Built-in 2 circuits(connect to external ceramic resonator or quartz-crystal oscillator)qPower source voltage

In high-speed mode..................................................4.0 to 5.5 V(at 8 MHz oscillation frequency)

In high-speed mode..................................................2.7 to 5.5 V(at 4 MHz oscillation frequency)

In middle-speed mode...............................................2.7 to 5.5 V(at 8 MHz oscillation frequency)

In low-speed mode....................................................2.7 to 5.5 V(at 32 kHz oscillation frequency)qPower dissipation

In high-speed mode..........................................................34 mW(at 8 MHz oscillation frequency, at 5 V power source voltage)In low-speed mode

Except M37516F8HP........................................................60 µWM37516F8HP..................................................................450 µW(at 32 kHz oscillation frequency, at 3 V power source voltage)qOperating temperature range....................................–20 to 85°C

APPLICATION

Office automation equipment, FA equipment, Household products,Consumer electronics, etc.

36 35 34 33 32 31 30 29 28 27 26 25 P36/AN6 P37/AN7 P00/SIN2 P01/SOUT2 P02/SCLK2 P03/SRDY2 P04 P05 P06 P07 P10/(LED0) P11/(LED1)PIN CONFIGURATION (TOP VIEW) P35/AN5P34/AN4P33/AN3P32/AN2 37 3839 4041 42 43 44 45 46474824 2322 2120 1918 1716 15 14 13 P12/(LED2) P13/(LED3)P14/(LED4)P15/(LED5)P16/(LED6) P17/(LED7) P31/AN1P30/AN0 VCCM37516M8-XXXHPVSSVREFAVSSP47P46P45XOUTXIN RESETP20/XCOUTP21/XCINP43/INT2/SCMP2 P42/INT1 P41/INT0 P40/CNTR1Package type : 48P6Q-AFig. 1 M37516F8HP pin configuration

Rev.1.01 Jul 01, 2003 page 1 of 89

P27/CNTR0/SRDY1 P26/SCLK P25/SCL2/TXD P24/SDA2/RXD P23/SCL1 P22/SDA1 CNVSS P44/INT3/PWM9 10 11 12123456787516 GroupFUNCTIONAL BLOCK DIAGRAMFUNCTIONAL BLOCK元器件交易网www.cecb2b.com

Fig.2 Functional block diagramVSS 18 43 15 12 Main-clock inpu tXIN 16 Main-clock o utputXOUT 17VCCRESET R eset input CNVSS Rev.1.01 Jul 01, 2003 page 2 of 89

C P UClock generating circuit RAM(Flash)XY CNTR0 Prescaler Y (8) CNTR1 Prescaler X (8) Prescaler 12 (8)ROMA Timer 2 (8) Timer X (8) Timer Y (8) Timer 1 (8) XCIN Sub-clock input XCOUT Sub-clock output PCH Watchdog timer ResetS PCL PS SI/O1(8)I2C(8) A-Dconverter PWM (8) SI/O2(8)(10) INT0–INT3XCINXCOUT P4(8) P3(8) P2(8) P1(8) P0(8) VREFAVSS 4445 3536373839404142 46474812345 678910111314 1920212223242526 2728293031323334 I/O port P 4 I/O port P3 I/O port P 2 I/O port P 1 I/O port P 0元器件交易网www.cecb2b.com

7516 Group

Table 1 Pin description

PinVCC, VSSCNVSSVREFAVssRESETXINXOUTP00/SIN2P01/SOUT2P02/SCLK2P03/SRDY2P04–P07P10–P17P20/XCOUTP21/XCINP22/SDA1P23/SCL1

P24/SDA2/RxDP25/SCL2/TxDP26/SCLKP27/CNTR0/SRDY1

I/O port P1I/O port P2

NamePower sourceCNVSS inputReferencevoltage inputAnalog powersource inputReset inputClock inputClock outputI/O port P0

Functions

•Apply voltage of 2.7 V – 5.5 V to Vcc, and 0 V to Vss.•This pin controls the operation mode of the chip.•Normally connected to VSS.

•Reference voltage input pin for A-D converter.•Analog power source input pin for A-D converter.•Connect to Vss.

•Reset input pin for active “L”.

•Input and output pins for the clock generating circuit.

•Connect a ceramic resonator or quartz-crystal oscillator between the XIN and XOUT pins to setthe oscillation frequency.

•When an external clock is used, connect the clock source to the XIN pin and leave the XOUTpin open.

• Serial I/O2 function pin•8-bit CMOS I/O port.

•I/O direction register allows each pin to be individually

programmed as either input or output.•CMOS compatible input level.•CMOS 3-state output structure.

•P10 to P17 (8 bits) are enabled to output large current for LED drive.

• Sub-clock generating circuit I/O•8-bit CMOS I/O port.

pins (connect a resonator)•I/O direction register allows each pin to be individually

• I2C-BUS interface function pinsprogrammed as either input or output.•CMOS compatible input level.

•P22 to P25 can be switched between CMOS compat-ible input level or SMBUS input level in the I2C-BUS

interface function.

•P20, P21, P24 to P27: CMOS 3-state output structure.•P24, P25: N-channel open-drain structure in the I2C-BUS interface function.

I/O port P3

•P22, P23: N-channel open-drain structure.

•8-bit CMOS I/O port with the same function as port P0.•CMOS compatible input level.•CMOS 3-state output structure.

P40/CNTR1P41/INT0P42/INT1

P43/INT2/SCMP2P44/INT3/PWMP45–P47

I/O port P4

•8-bit CMOS I/O port with the same function as port P0.•CMOS compatible input level.•CMOS 3-state output structure.

• Timer Y function pin• Interrupt input pins

• Interrupt input pin/SCMP2 output pin• Interrupt input pin/PWM output pin• I2C-BUS interface function pin/Serial I/O1 function pins• Serial I/O1 function pin• Serial I/O1 function pin/Timer X function pin

Function except a port function

P30/AN0–P37/AN7

• A-D converter input pin

Rev.1.01 Jul 01, 2003 page 3 of 89

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7516 GroupPART NUMBERINGProduct nameM37516M8–XXXHPPackage typeHP : 48P6Q-AROM numberOmitted in One Time PROM version shipped in blank and flash memory version.– : standardOmitted in One Time PROM version shipped in blank and flash memory version.ROM/PROM/Flash memory size9: 36864 bytes1: 4096 bytes2: 8192 bytes3: 12288 bytesA: 40960 bytesB: 45056 bytesC: 49152 bytesD: 53248 bytesE: 57344 bytesF: 61440 bytes4: 16384 bytes5: 20480 bytes6: 24576 bytes7: 28672 bytes8: 32768 bytesThe first 128 bytes and the last 2 bytes of ROM are reserved areas ; they cannot be used as a user’s ROM area.However, they can be programmed or erased in the flash memory version, so that the users can use them.Memory typeM: Mask ROM versionE : One Time PROM versionF: Flash memory versionDifferences of functionsFig. 3 Part numberingRev.1.01 Jul 01, 2003 page 4 of 89

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7516 GroupGROUP EXPANSIONMitsubishi plans to expand the 7516 group as follows.Packages48P6Q-A...............................................48-pin plastic-molded QFPMemory TypeSupport for mask ROM, One Time PROM, and flash memory ver-sions.Memory SizeFlash memory size.........................................................32 K bytesMask ROM size.................................................16 K to 32 K bytesOne Time PROM size.....................................................24 K bytesRAM size...............................................................512 to 1 K bytesMemory Expansion Plan ROM size (bytes)ROMexteranal32K 28K 24K 20K 16K 12K8KNew product As of Aug. 2002 M37516M8/F8 Mass productionM37516M6/E6 Mass production M37516M4 384 512 640768 89610241152 RAM size (bytes)1280 1408 1536 2048Fig. 4 Memory expansion planRev.1.01 Jul 01, 2003 page 5 of 89

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7516 Group

Currently planning products are listed below.Table 2 Support products

Product nameM37516M4-XXXHPM37516M6-XXXHPM37516E6-XXXHPM37516E6HP

M37516M8-XXXHPM37516F8HP

ROM size (bytes)ROM size for User in ( )16384(16254)24576(24446)32768(32638)

RAM size (bytes)

512

Package

Remarks

As of Jul. 2003

Mask ROM version

48P6Q-A

One Time PROM version

One Time PROM version (blank)Mask ROM versionFlash memory version

640

1024

Rev.1.01 Jul 01, 2003 page 6 of 89

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7516 Group

FUNCTIONAL DESCRIPTION

CENTRAL PROCESSING UNIT (CPU)

The 7516 group uses the standard 740 Family instruction set. Re-fer to the table of 740 Family addressing modes and machineinstructions or the 740 Family Software Manual for details on theinstruction set.

Machine-resident 740 Family instructions are as follows:The FST and SLW instructions cannot be used.

The STP, WIT, MUL, and DIV instructions can be used.

[Stack Pointer (S)]

The stack pointer is an 8-bit register used during subroutine callsand interrupts. This register indicates start address of stored area(stack) for storing registers during subroutine calls and interrupts.The low-order 8 bits of the stack address are determined by thecontents of the stack pointer. The high-order 8 bits of the stack ad-dress are determined by the stack page selection bit. If the stackpage selection bit is “0” , the high-order 8 bits becomes “0016”. Ifthe stack page selection bit is “1”, the high-order 8 bits becomes“0116”.

The operations of pushing register contents onto the stack andpopping them from the stack are shown in Figure 6.

Store registers other than those described in Figure 6 with pro-gram when the user needs them during interrupts or subroutinecalls.

[Accumulator (A)]

The accumulator is an 8-bit register. Data operations such as datatransfer, etc., are executed mainly through the accumulator.

[Index Register X (X)]

The index register X is an 8-bit register. In the index addressingmodes, the value of the OPERAND is added to the contents ofregister X and specifies the real address.

[Program Counter (PC)]

The program counter is a 16-bit counter consisting of two 8-bitregisters PCH and PCL. It is used to indicate the address of thenext instruction to be executed.

[Index Register Y (Y)]

The index register Y is an 8-bit register. In partial instruction, thevalue of the OPERAND is added to the contents of register Y andspecifies the real address.

b7Ab7Xb7Yb7Sb15PCHb7b7PCLb0Accumulatorb0Index register Xb0Index register Yb0Stack pointerb0Program counterb0Processor status register (PS)Carry flagZero flagInterrupt disable flagDecimal mode flagBreak flagIndex X mode flagOverflow flagNegative flagNVTBDIZCFig. 5 740 Family CPU register structure

Rev.1.01 Jul 01, 2003 page 7 of 89

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7516 Group On-going Routine Interrupt request (Note) Execute JSR M (S)(PCH) M (S)(PCH) Push return address on stack (S) (S) – 1 M (S)(PCL) Push return address on stack (S) (S) – 1 M (S)(PCL) (S) (S) – 1 M (S)(PS) Push contents of processor status register on stack(S) (S)– 1 (S) (S) – 1Interrupt Service Routine Subroutine Execute RTS (S) (S) + 1 (PCL)M (S) POP returnaddress from stack Execute RTI (S) (S) + 1 (PS)M (S) I Flag is set from “0” to “1” Fetch the jump vector POP contents of processor status register from stack (S) (S) + 1M (S) (PCH)(S) (S) + 1M (S) POP returnaddress from stack (PCL) (S) (S) + 1M (S) (PCH)Note: Condition for acceptance of an interrupt Interrupt enable flag is “1”Interrupt disable flag is “0”Fig. 6 Register push and pop at interrupt generation and subroutine callTable 3 Push and pop instructions of accumulator or processor status registerPush instruction to stackAccumulatorProcessor status registerPHAPHPPop instruction from stackPLAPLPRev.1.01 Jul 01, 2003 page 8 of 89

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7516 Group

[Processor status register (PS)]

The processor status register is an 8-bit register consisting of 5flags which indicate the status of the processor after an arithmeticoperation and 3 flags which decide MCU operation. Branch opera-tions can be performed by testing the Carry (C) flag , Zero (Z) flag,Overflow (V) flag, or the Negative (N) flag. In decimal mode, the Z,V, N flags are not valid.

•Bit 0: Carry flag (C)

The C flag contains a carry or borrow generated by the arithmeticlogic unit (ALU) immediately after an arithmetic operation. It canalso be changed by a shift or rotate instruction.•Bit 1: Zero flag (Z)

The Z flag is set if the result of an immediate arithmetic operationor a data transfer is “0”, and cleared if the result is anything otherthan “0”.

•Bit 2: Interrupt disable flag (I)

The I flag disables all interrupts except for the interruptgenerated by the BRK instruction.

Interrupts are disabled when the I flag is “1”.•Bit 3: Decimal mode flag (D)

The D flag determines whether additions and subtractions areexecuted in binary or decimal. Binary arithmetic is executed whenthis flag is “0”; decimal arithmetic is executed when it is “1”.Decimal correction is automatic in decimal mode. Only the ADCand SBC instructions can be used for decimal arithmetic.

•Bit 4: Break flag (B)

The B flag is used to indicate that the current interrupt wasgenerated by the BRK instruction. The BRK flag in the processorstatus register is always “0”. When the BRK instruction is used togenerate an interrupt, the processor status register is pushedonto the stack with the break flag set to “1”.•Bit 5: Index X mode flag (T)

When the T flag is “0”, arithmetic operations are performedbetween accumulator and memory. When the T flag is “1”, directarithmetic operations and direct data transfers are enabledbetween memory locations.•Bit 6: Overflow flag (V)

The V flag is used during the addition or subtraction of one byteof signed data. It is set if the result exceeds +127 to -128. Whenthe BIT instruction is executed, bit 6 of the memory locationoperated on by the BIT instruction is stored in the overflow flag.•Bit 7: Negative flag (N)

The N flag is set if the result of an arithmetic operation or datatransfer is negative. When the BIT instruction is executed, bit 7 ofthe memory location operated on by the BIT instruction is storedin the negative flag.

Table 4 Set and clear instructions of each bit of processor status register

C flag

Set instructionClear instruction

SECCLC

Z flag__I flagSEICLI

D flagSEDCLD

B flag__T flagSETCLT

V flag_CLV

N flag__Rev.1.01 Jul 01, 2003 page 9 of 89

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7516 Group[CPU Mode Register (CPUM)] 003B16The CPU mode register contains the stack page selection bit, etc.The CPU mode register is allocated at address 003B16. b71 b0 CPU mode register (CPUM : address 003B16) Processor mode bitsb1 b000 : Single-chip mode01 : 10 : Not available11 : Stack page selection bit0 : 0 page1 : 1 page Fix this bit to “1”.Port XC switch bit0 : I/O port function (stop oscillating)1 : XCIN–XCOUT oscillating functionMain clock (XIN–XOUT) stop bit 0 : Oscillating1 : StoppedMain clock division ratio selection bitsb7 b600 : φ = f(XIN)/2 (high-speed mode)01 : φ = f(XIN)/8 (middle-speed mode)1 0 : φ = f(XCIN)/2 (low-speed mode)1 1 : Not availableFig. 7 Structure of CPU mode registerRev.1.01 Jul 01, 2003 page 10 of 89

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7516 GroupMEMORYSpecial Function Register (SFR) AreaThe Special Function Register area in the zero page contains con-trol registers such as I/O ports and timers.Interrupt Vector AreaThe interrupt vector area contains reset and interrupt vectors.Zero PageAccess to this area with only 2 bytes is possible in the zero pageaddressing mode.RAMRAM is used for data storage and for stack area of subroutinecalls and interrupts.Special PageAccess to this area with only 2 bytes is possible in the specialpage addressing mode.ROMThe first 128 bytes and the last 2 bytes of ROM are reserved fordevice testing and the rest is user area for storing programs. Product nameM37516M4M37516M6/E6M37516M8/F8 RAM size512 bytes640 bytes1024 bytes ROM size16 Kbytes24 Kbytes32 Kbytes 000016 004016RAM 010016XXXX16SFR areaZero page RAM area RAM size(bytes)5126401024 AddressXXXX16023F1602BF16043F16Not used ROM areaROM size(bytes)163842457632768AddressYYYY16C00016A00016800016AddressZZZZ16C08016A080168080160FF0160FFF16 YYYY16 ZZZZ16SFR area (Note)Not usedReserved ROM area(128 bytes) ROMFF0016 Special pageInterrupt vector areaReserved ROM areaFFDC16 F FFE16FFFF16 Note: Flash memory version onlyFig. 8 Memory map diagramRev.1.01 Jul 01, 2003 page 11 of 89

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7516 Group 000016 000116 000216 000316 000416 000516 000616 000716 000816 000916 000A16 000B16 000C16 000D16 000E16 000F16 001016 001116 001216 001316 001416 001516 001616 001716 001816 001916 001A16 001B16 001C16 001D16 001E16 001F16 Port P0 (P0) Port P0 direction register (P0D) Port P1 (P1) Port P1 direction register (P1D) Port P2 (P2) Port P2 direction register (P2D) Port P3 (P3) Port P3 direction register (P3D) Port P4 (P4) Port P4 direction register (P4D)002016002116002216002316002416002516002616002716002816002916002A16002B16002C16002D16002E16002F16003016003116Prescaler 12 (PRE12)Timer 1 (T1)Timer 2 (T2)Timer XY mode register (TM)Prescaler X (PREX)Timer X (TX)Prescaler Y (PREY)Timer Y (TY)Timer count source selection register (TCSS)I2C data shift register (S0)I2C address register (S0D)I2C status register (S1)I2C control register (S1D)I2C clock control register (S2)I2C start/stop condition control register (S2D) Reserved ✽Reserved ✽Reserved ✽Reserved ✽ Serial I/O2 control register 1 (SIO2CON1) Serial I/O2 control register 2 (SIO2CON2) Serial I/O2 register (SIO2) Transmit/Receive buffer register (TB/RB) Serial I/O1 status register (SIOSTS) Serial I/O1 control register (SIOCON) UART control register (UARTCON) Baud rate generator (BRG)PWM control register (PWMCON)PWM prescaler (PREPWM) PWM register (PWM) 003216003316003416003516003616003716003816003916003A16003B16003C16003D16003E16003F16A-D control register (ADCON)A-D conversion low-order register (ADL)A-D conversion high-order register (ADH) Reserved ✽MISRGWatchdog timer control register (WDTCON)Interrupt edge selection register (INTEDGE)CPU mode register (CPUM) Interrupt request register 1 (IREQ1)Interrupt request register 2 (IREQ2)Interrupt control register 1 (ICON1)Interrupt control register 2 (ICON2) Reserved ✽Flash memory control register (FCON) Reserved ✽0FFD16 0FFE160FFF16✽ Reserved : Do not write any data to the reserved area.Fig. 9 Memory map of special function register (SFR)Rev.1.01 Jul 01, 2003 page 12 of 89

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7516 Group

I/O PORTS

The I/O ports have direction registers which determine the input/output direction of each individual pin. Each bit in a direction reg-ister corresponds to one pin, and each pin can be set to be inputport or output port.

When “0” is written to the bit corresponding to a pin, that pin be-comes an input pin. When “1” is written to that bit, that pinbecomes an output pin.

If data is read from a pin which is set to output, the value of theport output latch is read, not the value of the pin itself. Pins set toinput are floating. If a pin set to input is written to, only the portoutput latch is written to and the pin remains floating.Table 5 I/O port function

Pin

P00/SIN2P01/SOUT2P02/SCLK2P03/SRDY2P04–P07P10–P17P20/XCOUTP21/XCINP22/SDA1P23/SCL1

Port P1Port P2

CMOS compatibleinput level

CMOS/SMBUS inputlevel (when selectingI2C-BUS interfacefunction)

N-channel open-drainoutput

CMOS compatibleinput level

CMOS/SMBUS inputlevel (when selectingI2C-BUS interfacefunction)

CMOS 3-state outputN-channel open-drainoutput (when

selecting I2C-BUSinterface function)CMOS compatibleinput level

CMOS 3-state output

Sub-clock generatingcircuit

I2C-BUS interface func-tion I/O

CPU mode registerI2C control register

(6)(7)(8)(9)

NamePort P0

Input/OutputInput/output,individualbits

I/O StructureCMOS compatibleinput level

CMOS 3-state output

Non-Port FunctionSerial I/O2 function I/O

Related SFRsSerial I/O2 controlregister

Ref.No.(1)(2)(3)(4)(5)

P24/SDA2/RxDP25/SCL2/TxD

I2C-BUS interface func-tion I/O

Serial I/O1 function I/O

I2C control registerSerial I/O1 controlregister

(10)(11)

P26/SCLKP27/CNTR0/SRDY1P30/AN0–P37/AN7P40/CNTR1P41/INT0P42/INT1

P43/INT2/SCMP2

Port P3Port P4

Serial I/O1 function I/OSerial I/O1 function I/OTimer X function I/OA-D conversion inputTimer Y function I/OExternal interrupt inputExternal interrupt inputSCMP2 output

Serial I/O1 controlregister

Serial I/O1 controlregister

Timer XY mode registerA-D control registerTimer XY mode registerInterrupt edge selectionregister

Interrupt edge selectionregister

Serial I/O2 controlregister

Interrupt edge selectionregister

PWM control register

(12)(13)

(14)(15)(16)(17)

P44/INT3/PWMExternal interrupt inputPWM output

(18)

P45–P47(5)

Rev.1.01 Jul 01, 2003 page 13 of 89

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7516 Group (1) Port P00 Directionregister (2) Port P01 P01/SOUT2 P-channel outputdisable bit Serial I/O2 transmit completion signal Serial I/O2 port selection bit Data bus Port latch Data bus DirectionregisterPort latch Serial I/O2 inputSerial I/O2 output (3) Port P02 P02/SCLK2 P-channel output disable bitSerial I/O2 synchronous clockselection bitSerial I/O2 port selection bit(4) Port P03SRDY2 output enable bitDirectionregister DirectionregisterPort latchData busData busPort latch Serial I/O2 clock output Serial I/O2 external clock inputSerial I/O2 ready output (5) Ports P04–P07, P1, P45–P47 Directionregister(6) Port P20Port XC switch bitDirectionregisterData busPort latch Data busPort latch Port P21 Oscillator (7) Port P21Port XC switch bitDirectionregisterData bus Port latchPort XC switch bit (8) Port P22I2C-BUS interface enable bitSDA/SCL pin selection bit DirectionregisterPort latchData busSub-clock generating circuit input SDA outputSDA inputFig. 10 Port block diagram (1)Rev.1.01 Jul 01, 2003 page 14 of 89

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7516 Group (9) Port P23I2 C-BUS interface enable bitSDA/SCL pin selection bitDirectionregister Data bus Port latch (10) Port P24I2C-BUS interface enable bitSDA/SCL pin selection bitSerial I/O1 enable bitReceive enable bitDirectionregisterData bus Port latch SCL output SCL inputSDA outputSDA input Serial I/O1 input (11) Port P25 (12) Port P26P-channel output disable bitSerial I/O1 synchronous clockselection bitSerial I/O1 enable bitSerial I/O1 mode selection bitSerial I/O1 enable bit Serial I/O1 enable bitTransmit enable bitI2C-BUS interface enable bitSDA/SCL pin selection bit DirectionregisterDirectionregisterData busPort latchData busPort latchSerial I/O1 outputSCL outputSCL input Serial I/O1 clock outputExternal clock input (13) Port P27 (14) Ports P30–P37Pulse output modeSerial I/O1 mode selection bitSerial I/O1 enable bitSRDY1 output enable bit DirectionregisterPort latch Data bus Directionregister Data busPort latch Pulse output modeCNTR0interrupt inputSerial ready outputTimer output A-D converter inputAnalog input pin selection bit (15) Port P40 Directionregister (16) Ports P41, P42Directionregister Data bus Port latchData busPort latch Pulse output modeTimer output CNTR1 interrupt input Interrupt inputFig. 11 Port block diagram (2)Rev.1.01 Jul 01, 2003 page 15 of 89

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7516 Group(17) Port P43Serial I/O2 input/outputcomparison signal control bit(18) Port P44PWM output enable bit Directionregister DirectionregisterData busPort latch Data busPort latch PWM output Serial I/O2 input/outputcomparison signal outputInterrupt inputInterrupt inputFig. 12 Port block diagram (3)Rev.1.01 Jul 01, 2003 page 16 of 89

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7516 Group

INTERRUPTS

Interrupts occur by 17 sources among 17 sources: seven external,nine internal, and one software.

sNotes

When setting the followings, the interrupt request bit may be set to“1”.

•When setting external interrupt active edge

Related register: Interrupt edge selection register (address 3A16)

I2C start/stop condition control register (address 3016)Timer XY mode register (address 2316)

•When switching interrupt sources of an interrupt vector addresswhere two or more interrupt sources are allocated

Related register: Interrupt edge selection register (address 3A16)When not requiring for the interrupt occurrence synchronized withthese setting, take the following sequence.

➀Set the corresponding interrupt enable bit to “0” (disabled).

➁Set the interrupt edge select bit or the interrupt source select bit.➂Set the corresponding interrupt request bit to “0” after 1 or moreinstructions have been executed.

➃Set the corresponding interrupt enable bit to “1” (enabled).

Interrupt Control

Each interrupt is controlled by an interrupt request bit, an interruptenable bit, and the interrupt disable flag except for the software in-terrupt set by the BRK instruction. An interrupt occurs if thecorresponding interrupt request and enable bits are “1” and the in-terrupt disable flag is “0”.

Interrupt enable bits can be set or cleared by software.

Interrupt request bits can be cleared by software, but cannot beset by software.

The BRK instruction cannot be disabled with any flag or bit. The I(interrupt disable) flag disables all interrupts except the BRK in-struction interrupt.

When several interrupts occur at the same time, the interrupts arereceived according to priority.

Interrupt Operation

By acceptance of an interrupt, the following operations are auto-matically performed:

1. The contents of the program counter and the processor statusregister are automatically pushed onto the stack.

2. The interrupt disable flag is set and the corresponding interruptrequest bit is cleared.

3. The interrupt jump destination address is read from the vectortable into the program counter.

Rev.1.01 Jul 01, 2003 page 17 of 89

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7516 Group

Table 6 Interrupt vector addresses and priority

Vector Addresses (Note 1)

Interrupt SourcePriority

HighLow

1FFFD16FFFC16Reset (Note 2)INT0SCL, SDAINT1INT2INT3Serial I/O2I2C

Timer XTimer YTimer 1Timer 2Serial I/O1receptionSerial I/O1transmissionCNTR0CNTR1

A-D converterBRK instruction

67891011121314151617FFF316FFF116FFEF16FFED16FFEB16FFE916FFE716FFE516FFE316FFE116FFDF16FFDD16

FFF216FFF016FFEE16FFEC16FFEA16FFE816FFE616FFE416FFE216FFE016FFDE16FFDC16

2345

FFFB16FFF916FFF716FFF516

FFFA16FFF816FFF616FFF416

Interrupt RequestGenerating ConditionsAt reset

At detection of either rising orfalling edge of INT0 inputAt detection of either rising orfalling edge of SCL or SDA inputAt detection of either rising orfalling edge of INT1 inputAt detection of either rising orfalling edge of INT2 inputAt detection of either rising orfalling edge of INT3 inputAt completion of serial I/O2 datareception/transmissionAt completion of data transferAt timer X underflowAt timer Y underflowAt timer 1 underflowAt timer 2 underflow

At completion of serial I/O1 datareception

At completion of serial I/O1transfer shift or when transmis-sion buffer is empty

At detection of either rising orfalling edge of CNTR0 inputAt detection of either rising orfalling edge of CNTR1 inputAt completion of A-D conversionAt BRK instruction execution

Remarks

Non-maskable

External interrupt

(active edge selectable)External interrupt

(active edge selectable)External interrupt

(active edge selectable)External interrupt

(active edge selectable)External interrupt

(active edge selectable)Switch by Serial I/O2/INT3interrupt source bit

STP release timer underflow

Valid when serial I/O1 is selectedValid when serial I/O1 is selectedExternal interrupt

(active edge selectable)External interrupt

(active edge selectable)Non-maskable software interrupt

Notes 1: Vector addresses contain interrupt jump destination addresses.

2: Reset function in the same way as an interrupt with the highest priority.

Rev.1.01 Jul 01, 2003 page 18 of 89

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7516 Group Interrupt request bit Interrupt enable bit Interrupt disable flag (I) Interrupt requestBRK ins tructionResetFig. 13 Interrupt control b7 b0 I nterrupt edge selection register(INTEDGE : address 003A16) INT0 active edge selection bitINT1 active edge selection bit0 : Falling edge active1 : Rising edge activeINT2 active edge selection bitINT3 active edge selection bitSerial I/O2 / INT3 interrupt source bit 0 : INT3 interrupt selected 1 : Serial I/O2 interrupt selected Not used (returns “0” when read)b7 b0Interrupt request register 1 (IREQ1 : address 003C16) INT0 interrupt request bitSCL/SDA interrupt request bitINT1 interrupt request bitINT2 interrupt request bitINT3 / Serial I/O2 interrupt request bitI2C interrupt request bitTimer X interrupt request bitTimer Y interrupt request bit0 : No interrupt request issued1 : Interrupt request issued b7 b0 b7 b0 b7 b0Interrupt request register 2(IREQ2 : address 003D16) Timer 1 interrupt request bitTimer 2 interrupt request bitSerial I/O1 reception interrupt request bitSerial I/O1 transmit interrupt request bitCNTR0 interrupt request bitCNTR1 interrupt request bit AD converter interrupt request bitNot used (returns “0” when read)0 : No interrupt request issued1 : Interrupt request issued Interrupt control register 1 (ICON1 : address 003E16) INT0 interrupt enable bitSCL/SDA interrupt enable bitINT1 interrupt enable bitINT2 interrupt enable bitINT3 / Serial I/O2 interrupt enable bitI2C interrupt enable bitTimer X interrupt enable bitTimer Y interrupt enable bitInterrupt control register 2(ICON2 : address 003F16)Timer 1 interrupt enable bitTimer 2 interrupt enable bitSerial I/O1 reception interrupt enable bitSerial I/O1 transmit interrupt enable bitCNTR0 interrupt enable bitCNTR1 interrupt enable bit AD converter interrupt enable bitNot used (returns “0” when read)(Do not write “1” to this bit.)0 : Interrupts disabled1 : Interrupts enabled0 : Interrupts disabled1 : Interrupts enabledFig. 14 Structure of interrupt-related registersRev.1.01 Jul 01, 2003 page 19 of 89

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7516 GroupTIMERSThe 7516 group has four timers: timer X, timer Y, timer 1, andtimer 2.The division ratio of each timer or prescaler is given by 1/(n + 1),where n is the value in the corresponding timer or prescaler latch.All timers are count down. When the timer reaches “0016”, an un-derflow occurs at the next count pulse and the correspondingtimer latch is reloaded into the timer and the count is continued.When a timer underflows, the interrupt request bit correspondingto that timer is set to “1”. b0Timer XY mode register(TM : address 002316) Timer X operating mode bitsb1b00 0: Timer mode0 1: Pulse output mode1 0: Event counter mode1 1: Pulse width measurement mode CNTR0 active edge selection bit0: Interrupt at falling edgeCount at rising edge in eventcounter mode1: Interrupt at rising edgeCount at falling edge in eventcounter mode Timer X count stop bit0: Count start1: Count stop Timer Y operating mode bitsb5b40 0: Timer mode0 1: Pulse output mode1 0: Event counter mode1 1: Pulse width measurement mode CNTR1 active edge selection bit0: Interrupt at falling edgeCount at rising edge in eventcounter mode1: Interrupt at rising edgeCount at falling edge in eventcounter modeTimer Y count stop bit0: Count start1: Count stopTimer X and Timer YTimer X and Timer Y can each select in one of four operatingmodes by setting the timer XY mode register.(1) Timer ModeThe timer counts the count source selected by Timer count sourceselection bit.(2) Pulse Output ModeThe timer counts the count source selected by Timer count sourceselection bit. Whenever the contents of the timer reach “0016”, thesignal output from the CNTR0 (or CNTR1) pin is inverted. If theCNTR0 (or CNTR1) active edge selection bit is “0”, output beginsat “ H”.If it is “1”, output starts at “L”. When using a timer in this mode, setthe corresponding port P27 ( or port P40) direction register to out-put mode.b7(3) Event Counter ModeOperation in event counter mode is the same as in timer mode,except that the timer counts signals input through the CNTR0 orCNTR1 pin.When the CNTR0 (or CNTR1) active edge selection bit is “0”, therising edge of the CNTR0 (or CNTR1) pin is counted.When the CNTR0 (or CNTR1) active edge selection bit is “1”, thefalling edge of the CNTR0 (or CNTR1) pin is counted.(4) Pulse Width Measurement ModeIf the CNTR0 (or CNTR1) active edge selection bit is “0”, the timercounts the selected signals by the count source selection bit whilethe CNTR0 (or CNTR1) pin is at “H”. If the CNTR0 (or CNTR1) ac-tive edge selection bit is “1”, the timer counts it while the CNTR0(or CNTR1) pin is at “L”.The count can be stopped by setting “1” to the timer X (or timer Y)count stop bit in any mode. The corresponding interrupt requestbit is set each time a timer underflows.Fig. 15 Structure of timer XY mode register b7 b0 sNoteWhen switching the count source by the timer 12, X and Y countsource bits, the value of timer count is altered in unconsiderableamount owing to generating of a thin pulses in the count inputsignals.Therefore, select the timer count source before set the value tothe prescaler and the timer.When timer X/timer Y underflow while executing the instructionwhich sets “1” to the timer X/timer Y count stop bits, the timer X/timer Y interrupt request bits are set to “1”. Timer X/Timer Y in-terrupts are received if these interrupts are enabled at this time.The timing which interrupt is accepted has a case after the in-struction which sets “1” to the count stop bit, and a case afterthe next instruction according to the timing of the timer under-flow. When this interrupt is unnecessary, set “0” (disabled) to theinterrupt enable bit and then set “1” to the count stop bit.Timer count source selection register(TCSS : address 002816) Timer X count source selection bit0 : f(XIN)/16 (f(XCIN)/16 at low-speed mode)1 : f(XIN)/2 (f(XCIN)/2 at low-speed mode) Timer Y count source selection bit0 : f(XIN)/16 (f(XCIN)/16 at low-speed mode)1 : f(XIN)/2 (f(XCIN)/2 at low-speed mode)Timer 12 count source selection bit0 : f(XIN)/16 (f(XCIN)/16 at low-speed mode)1 : f(XCIN) Not used (returns “0” when read)Fig. 16 Structure of timer count source selection registerTimer 1 and Timer 2The count source of prescaler 12 is the oscillation frequencywhich is selected by timer 12 count source selection bit. The out-put of prescaler 12 is counted by timer 1 and timer 2, and a timerunderflow sets the interrupt request bit.Rev.1.01 Jul 01, 2003 page 20 of 89

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7516 Group Data bus f(XIN)/16 (f(XCIN)/16 at low-speed mode)Prescaler X latch (8) f(XIN)/2 Pulse width (f(XCIN)/2 at low-speed mode)Timer mode measurement Timer X count source selection bitPulse output modemode Timer X latch (8)Prescaler X (8)Event counter modeTimer X count stop bit Timer X (8) To timer X interrupt request bit P27/CNTR0/SRDY1CNTR0 active edge selection bit “0” “1” To CNTR0 interrupt request bitCNTR0 active edge selection “1”bit“0”QQToggle flip-flopTRTimer X latch write pulse Pulse output mode Port P27direction register Port P27latchPulse output mode Data bus f(XIN)/16(f(XCIN)/16 at low-speed mode) Prescaler Y latch (8) Pulse width Timer modemeasure-ment modePulse output modePrescaler Y (8)Event counter mode Timer Y count stop bitTimer Y latch (8)f(XIN)/2(f(XCIN)/2 at low-speed mode)Timer Y count source selection bit CNTR1 active edge selection bit “0” “1”Timer Y (8) To timer Y interrupt request bitP40/CNTR1 CNTR1 active edge selection “1”bit“0”To CNTR1 interrupt request bitQ Toggle flip-flopTQRPort P40direction register Pulse output mode Port P40 latch Timer Y latch write pulse Pulse output mode Data busPrescaler 12 latch (8)Timer 1 latch (8)Timer 2 latch (8) f(XIN)/16(f(XCIN)/16 at low-speed mode)f(XCIN) Timer 12 count source selection bitPrescaler 12 (8) Timer 1 (8) Timer 2 (8)To timer 2 interrupt request bit To timer 1 interrupt request bitFig. 17 Block diagram of timer X, timer Y, timer 1, and timer 2Rev.1.01 Jul 01, 2003 page 21 of 89

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7516 GroupSERIAL I/OqSERIAL I/O1Serial I/O1 can be used as either clock synchronous or asynchro-nous (UART) serial I/O. A dedicated timer is also provided forbaud rate generation.(1) Clock Synchronous Serial I/O ModeClock synchronous serial I/O mode can be selected by setting theserial I/O1 mode selection bit of the serial I/O1 control register (bit6 of address 001A16) to “1”.For clock synchronous serial I/O, the transmitter and the receivermust use the same clock. If an internal clock is used, transfer isstarted by a write signal to the TB/RB.Data busAddress 001816Receive buffer registerP24/RXDReceive shift registerShift clockP26/SCLKSerial I/O1 synchronousclock selection bit Frequency division ratio 1/(n+1)Baud rate generator1/4Address 001C16Clock control circuitShift clockP25/TXDTransmit shift registerTransmit buffer registerAddress 001816Data busTransmit shift completion flag (TSC)Transmit interrupt source selection bitTransmit interrupt request (TI)Transmit buffer empty flag (TBE)Serial I/O1 status registerAddress 001916Serial I/O1 control registerAddress 001A16Receive buffer full flag (RBF)Receive interrupt request (RI)Clock control circuitXINBRG count source selection bit1/4P27/SRDY1F/FFalling-edge detectorFig. 18 Block diagram of clock synchronous serial I/O1Transfer shift clock(1/2 to 1/2048 of the internal clock, or an external clock) Serial output TxDSerial input RxDD0D0D1D1D2D2D3D3D4D4D5D5D6D6D7D7Receive enable signal SRDY1Write pulse to receive/transmit buffer register (address 001816)TBE = 0RBF = 1TSC = 1Overrun error (OE) detectionTBE = 1TSC = 0Notes1: As the transmit interrupt (TI), either when the transmit buffer has emptied (TBE=1) or after the transmit shift operation has ended (TSC=1), by setting the transmit interrupt source selection bit (TIC) of the serial I/O1 control register.2: If data is written to the transmit buffer register when TSC=0, the transmit clock is generated continuously and serial data is output continuously from the TxD pin. 3: The receive interrupt (RI) is set when the receive buffer full flag (RBF) becomes “1” .Fig. 19 Operation of clock synchronous serial I/O1 functionRev.1.01 Jul 01, 2003 page 22 of 89

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7516 Group(2) Asynchronous Serial I/O (UART) ModeClock asynchronous serial I/O mode (UART) can be selected byclearing the serial I/O1 mode selection bit (b6) of the serial I/O1control register to “0”.Eight serial data transfer formats can be selected, and the transferformats used by a transmitter and receiver must be identical.The transmit and receive shift registers each have a buffer, but thetwo buffers have the same address in memory. Since the shift reg-ister cannot be written to or read from directly, transmit data iswritten to the transmit buffer register, and receive data is readfrom the receive buffer register.The transmit buffer register can also hold the next data to betransmitted, and the receive buffer register can hold a characterwhile the next character is being received. Data busAddress 001816Serial I/O1 control registerAddress 001A16 Receive buffer full flag (RBF)OEReceive buffer registerReceive interrupt request (RI)Character length selection bit ST detector7 bitsReceive shift register 1/168 bits UART control registerSP detectorPEFE Address 001B16Clock control circuit Serial I/O1 synchronous clock selection bit ncy division ratio 1/(n+1)BRG count source selection bitFreque Baud rate generator Address 001C161/4 ST/SP/PA generator1/16 P25/TXDCharacter length selection bitTransmit shift register Transmit buffer registerAddress 001816 Data bus P24/RXDP26/SCLK XIN Transmit shift completion flag (TSC) Transmit interrupt source selection bit Transmit interrupt request (TI)Transmit buffer empty flag (TBE)Serial I/O1 status registerAddress 001916Fig. 20 Block diagram of UART serial I/O1Rev.1.01 Jul 01, 2003 page 23 of 89

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7516 GroupTransmit or receive clockTransmit buffer write signalTBE=0TSC=0TBE=1Serial output TXDSTTBE=0TBE=1TSC=1D0D11 start bit7 or 8 data bit1 or 0 parity bit1 or 2 stop bit (s)SPSTD0D1SPGenerated at 2nd bit in 2-stop-bit mode Receive buffer read signalRBF=0RBF=1RBF=1Serial input RXDSTD0D1SPSTD0D1SPNotes 1: Error flag detection occurs at the same time that the RBF flag becomes “1” (at 1st stop bit, during reception).2: As the transmit interrupt (TI), when either the TBE or TSC flag becomes “1,” can be selected to occur depending on the setting of the transmit interrupt source selection bit (TIC) of the serial I/O1 control register.3: The receive interrupt (RI) is set when the RBF flag becomes “1.”4: After data is written to the transmit buffer when TSC=1, 0.5 to 1.5 cycles of the data shift cycle is necessary until changing to TSC=0.Fig. 21 Operation of UART serial I/O1 function[Transmit Buffer Register/Receive BufferRegister (TB/RB)] 001816The transmit buffer register and the receive buffer register are lo-cated at the same address. The transmit buffer is write-only andthe receive buffer is read-only. If a character bit length is 7 bits, theMSB of data stored in the receive buffer is “0”.[Serial I/O1 Control Register (SIOCON)] 001A16The serial I/O1 control register consists of eight control bits for theserial I/O1 function.[UART Control Register (UARTCON)] 001B16The UART control register consists of four control bits (bits 0 to 3)which are valid when asynchronous serial I/O is selected and setthe data format of an data transfer and one bit (bit 4) which is al-ways valid and sets the output structure of the P25/TXD pin.[Serial I/O1 Status Register (SIOSTS)] 001916The read-only serial I/O1 status register consists of seven flags(bits 0 to 6) which indicate the operating status of the serial I/O1function and various errors.Three of the flags (bits 4 to 6) are valid only in UART mode.The receive buffer full flag (bit 1) is cleared to “0” when the receivebuffer register is read.If there is an error, it is detected at the same time that data istransferred from the receive shift register to the receive buffer reg-ister, and the receive buffer full flag is set. A write to the serial I/O1status register clears all the error flags OE, PE, FE, and SE (bit 3to bit 6, respectively). Writing “0” to the serial I/O1 enable bit SIOE(bit 7 of the serial I/O1 control register) also clears all the statusflags, including the error flags.Bits 0 to 6 of the serial I/O1 status register are initialized to “0” atreset, but if the transmit enable bit (bit 4) of the serial I/O1 controlregister has been set to “1”, the transmit shift completion flag (bit2) and the transmit buffer empty flag (bit 0) become “1”.[Baud Rate Generator (BRG)] 001C16The baud rate generator determines the baud rate for serial trans-fer.The baud rate generator divides the frequency of the count sourceby 1/(n + 1), where n is the value written to the baud rate genera-tor.Rev.1.01 Jul 01, 2003 page 24 of 89

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7516 Group b7 b0 Serial I/O1 status register (SIOSTS : address 001916) Transmit buffer empty flag (TBE)0: Buffer full1: Buffer emptyReceive buffer full flag (RBF)0: Buffer empty1: Buffer fullTransmit shift completion flag (TSC)0: Transmit shift in progress1: Transmit shift completedOverrun error flag (OE)0: No error1: Overrun errorParity error flag (PE)0: No error1: Parity errorFraming error flag (FE)0: No error1: Framing errorSumming error flag (SE)0: (OE) U (PE) U (FE)=01: (OE) U (PE) U (FE)=1Not used (returns “1” when read) b7 b0Serial I/O1 control register 16)(SIOCON : address 001ABRG count source selection bit (CSS)0: f(XIN) 1: f(XIN)/4Serial I/O1 synchronous clock selection bit (SCS)0: BRG output divided by 4 when clock synchronous serial I/O1 is selected, BRG output divided by 16 when UART is selected. 1: External clock input when clock synchronous serial I/O1 is selected, external clock input divided by 16 when UART is selected. SRDY1 output enable bit (SRDY)0: P27 pin operates as ordinary I/O pin1: P27 pin operates as SRDY1 output pinTransmit interrupt source selection bit (TIC)0: Interrupt when transmit buffer has emptied1: Interrupt when transmit shift operation is completedTransmit enable bit (TE)0: Transmit disabled1: Transmit enabledReceive enable bit (RE)0: Receive disabled1: Receive enabledSerial I/O1 mode selection bit (SIOM)0: Clock asynchronous (UART) serial I/O1: Clock synchronous serial I/OSerial I/O1 enable bit (SIOE)0: Serial I/O1 disabled (pins P24 to P27 operate as ordinary I/O pins)1: Serial I/O1 enabled (pins P24 to P27 operate as serial I/O1 pins) b7 b0 UART control register U A R T CON : address 001B16)( Character length selection bit (CHAS)0: 8 bits1: 7 bitsParity enable bit (PARE)0: Parity checking disabled1: Parity checking enabledParity selection bit (PARS)0: Even parity1: Odd parityStop bit length selection bit (STPS)0: 1 stop bit1: 2 stop bitsP25/TXD P-channel output disable bit (POFF)0: CMOS output (in output mode)1: N-channel open drain output (in output mode)Not used (return “1” when read)Fig. 22 Structure of serial I/O1 control registerssNotes on serial I/O11. When using the serial I/O1, clear the I2C-BUS interface enablebit to “0” or the SDA/SCL interrupt pin selection bit to “0”.2. When setting the transmit enable bit of serial I/O1 to “1”, theserial I/O1 transmit interrupt request bit is automatically set to“1”. When not requiring the interrupt occurrence synchronizedwith the transmission enalbed, take the following sequence.➀Set the serial I/O1 transmit interrupt enable bit to “0” (dis-abled).➁Set the transmit enable bit to “1”.➂Set the serial I/O1 transmit interrupt request bit to “0” after 1or more instructions have been executed.➃Set the serial I/O1 transmit interrupt enable bit to “1” (en-abled).Rev.1.01 Jul 01, 2003 page 25 of 89

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7516 GroupqSERIAL I/O2The serial I/O2 can be operated only as the clock synchronous type.As a synchronous clock for serial transfer, either internal clock orexternal clock can be selected by the serial I/O2 synchronous clockselection bit (b6) of serial I/O2 control register 1.The internal clock incorporates a dedicated divider and permits se-lecting 6 types of clock by the internal synchronous clock selectionbits (b2, b1, b0) of serial I/O2 control register 1.Regarding SOUT2 and SCLK2 being output pins, either CMOS outputformat or N-channel open-drain output format can be selected by theP01/SOUT2, P02/SCLK2 P-channel output disable bit (b7) ofserial I/O2 control register 1.When the internal clock has been selected, a transfer starts by awrite signal to the serial I/O2 register (address 001716). After comple-tion of data transfer, the level of the SOUT2 pin goes to high imped-ance automatically but bit 7 of the serial I/O2 control register 2 is notset to “1” automatically.When the external clock has been selected, the contents of the serialI/O2 register is continuously sifted while transfer clocks are input.Accordingly, control the clock externally. Note that the SOUT2 pin doesnot go to high impedance after completion of data transfer.To cause the SOUT2 pin to go to high impedance in the case wherethe external clock is selected, set bit 7 of the serial I/O2 control reg-ister 2 to “1” when SCLK2 is “H” after completion of data transfer. Afterthe next data transfer is started (the transfer clock falls), bit 7 of theserial I/O2 control register 2 is set to “0” and the SOUT2 pin is put intothe active state.Regardless of the internal clock to external clock, the interrupt re-quest bit is set after the number of bits (1 to 8 bits) selected by theoptional transfer bit is transferred. In case of a fractional number ofbits less than 8 bits as the last data, the received data to be stored inthe serial I/O2 register becomes a fractional number of bits close toMSB if the transfer direction selection bit of serial I/O2 control regis-ter 1 is LSB first, or a fractional number of bits close to LSB if thetransfer direction selection bit is MSB first. For the remaining bits, thepreviously received data is shifted.At transmit operation using the clock synchronous serial I/O, the SCMP2signal can be output by comparing the state of the transmit pin SOUT2with the state of the receive pin SIN2 in synchronization with a rise ofthe transfer clock. If the output level of the SOUT2 pin is equal to theinput level to the SIN2 pin, “L” is output from the SCMP2 pin. If not, “H”is output. At this time, an INT2 interrupt request can also be gener-ated. Select a valid edge by bit 2 of the interrupt edge selection reg-ister (address 003A16).b7 b0 Serial I/O2 control register 1 (SIO2CON1 : address 001516) Internal synchronous clock selection bitsb2 b1 b00 0 0: f(XIN)/8 (f(XCIN)/8 in low-speed mode)0 0 1: f(XIN)/16 (f(XCIN)/16 in low-speed mode)0 1 0: f(XIN)/32 (f(XCIN)/32 in low-speed mode)0 1 1: f(XIN)/64 (f(XCIN)/64 in low-speed mode)1 1 0: f(XIN)/128 f(XCIN)/128 in low-speed mode)1 1 1: f(XIN)/256 (f(XCIN)/256 in low-speed mode)Serial I/O2 port selection bit0: I/O port1: SOUT2,SCLK2 output pinSRDY2 output enable bit 0: P03 pin is normal I/O pin1: P03 pin is SRDY2 output pinTransfer direction selection bit0: LSB first1: MSB firstSerial I/O2 synchronous clock selection bit 0: External clock1: Internal clockP01/SOUT2 ,P02/SCLK2 P-channel output disable bit0: CMOS output (in output mode)1: N-channel open-drain output (in output mode )b7 b0 Serial I/O2 control register 2(SIO2CON2 : address 001616) Optional transfer bitsb2 b1 b00 0 0: 1 bit0 0 1: 2 bit0 1 0: 3 bit0 1 1: 4 bit1 0 0: 5 bit1 0 1: 6 bit1 1 0: 7 bit1 1 1: 8 bitNot used ( returns \"0\" when read)Serial I/O2 I/O comparison signal control bit0: P43 I/O1: SCMP2 outputSOUT2 pin control bit (P01)0: Output active1: Output high-impedanceFig. 23 Structure of Serial I/O2 control registers 1, 2[Serial I/O2 Control Registers 1, 2 (SIO2CON1 /SIO2CON2)] 001516, 001616The serial I/O2 control registers 1 and 2 are containing various se-lection bits for serial I/O2 control as shown in Figure 23.Rev.1.01 Jul 01, 2003 page 26 of 89

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7516 Group Internal synchronous clock selection bits XCIN Divider1/8“10” “00”“01”1/161/321/641/1281/256 Main clock division ratio selection bits (Note)Data busXIN P03 latch P03/SRDY2 “0” Serial I/O2 synchronous clock selection bit Synchronous circuitSCLK2SRDY2“1” “0”“1” SRDY2 output enable bitExternal clock P02 latch “0” Optional transfer bits (3)Serial I/O counter 2 (3) Serial I/O2interrupt requestP02/SCLK2 “1” Serial I/O2 port selection bit “0” P01 latch P01/SOUT2“1” Serial I/O2 port selection bit P00/SIN2Serial I/O2 register (8)P43 latch “0” “1”Serial I/O2 I/O comparison signal control bitQP43/SCMP2/INT2DNote: Either high-speed, middle-speed or low-speed mode is selected by bits 6 and 7 of CPU mode register.Fig. 24 Block diagram of Serial I/O2 Transfer clock (Note 1) Write-in signal toserial I/O2 register (Note 2) Serial I/O2 output SOUT2 D0D1.D2D3D4D5D6D7Serial I/O2 input SIN2 Receive enable signal SRDY2 Serial I/O2 interrupt request bit set Notes1: When the internal clock is selected as a transfer clock, the f(XIN) clock division (f(XCIN) in low-speed mode) can be selected by setting bits 0 to 2 of serial I/O2 control register 1.2: When the internal clock is selected as a transfer clock, the SOUT2 pin has high impedance after transfer completion.Fig. 25 Timing chart of Serial I/O2Rev.1.01 Jul 01, 2003 page 27 of 89

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7516 GroupSCMP2SCLK2 SOUT2SIN2 Judgement of I/O data comparisonFig. 26 SCMP2 output operationRev.1.01 Jul 01, 2003 page 28 of 89

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7516 GroupMULTI-MASTER I2C-BUS INTERFACEThe multi-master I2C-BUS interface is a serial communications cir-cuit, conforming to the Philips I2C-BUS data transfer format. Thisinterface, offering both arbitration lost detection and a synchro-nous functions, is useful for the multi-master serialcommunications.Figure 27 shows a block diagram of the multi-master I2C-BUS in-terface and Table 7 lists the multi-master I2C-BUS interfacefunctions.This multi-master I2C-BUS interface consists of the I2C addressregister, the I2C data shift register, the I2C clock control register,the I2C control register, the I2C status register, the I2C start/stopcondition control register and other control circuits.When using the multi-master I2C-BUS interface, set 1 MHz ormore to φ.Note: Mitsubishi Electric Corporation assumes no responsibility for in-fringement of any third-party’s rights or originating in the use of theconnection control function between the I2C-BUS interface and theports SCL1, SCL2, SDA1 and SDA2 with the bit 6 of I2C control regis-ter (002E16).Table 7 Multi-master I2C-BUS interface functionsItemFunctionIn conformity with Philips I2C-BUSstandard: 10-bit addressing format 7-bit addressing format High-speed clock mode Standard clock modeIn conformity with Philips I2C-BUSstandard: Master transmission Master reception Slave transmission Slave reception16.1 kHz to 400 kHz (at φ = 4 MHz)FormatCommunication modeSCL clock frequencySystem clock φ = f(XIN)/2 (high-speed mode)φ = f(XIN)/8 (middle-speed mode) b7 I2C address registerb0Interrupt generating circuit Interrupt request signal(IICIRQ) SAD6SAD5SAD4SAD3SAD2SAD1SAD0RWBS0D Data control circuit Address comparatorb7I2C data shift registerS0Serial data(SDA)Noise elimination circuitb0b7MSTTRXBBPINb0 ALAASAD0LRB SISSIPSSC4SSC3SSC2SSC1SSC0 S2DALcircuitS1Internal data busI2C status registerI2C start/stop condition control registerBB circuitSerial clock(SCL) Noise elimination circuitClock control circuit b7ACKACKBIT b0 FAST CCR4CCR3CCR2CCR1CCR0MODE b7TISS10BITTSELSADI2C clock control register S1Db0 ALSES0BC2BC1BC0 S2I2C clock control registerClock division2S1D I C control registerSystem clock (φ)Bit counterFig. 27 Block diagram of multi-master I2C-BUS interface✽ : Purchase of MITSUBISHI ELECTRIC CORPORATIONS I2C components conveys a license under the Philips I2C Patent Rights to use these componentsan I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips.Rev.1.01 Jul 01, 2003 page 29 of 89

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7516 Group

[I2C Data Shift Register (S0)] 002B16

The I2C data shift register (S0 : address 002B16) is an 8-bit shiftregister to store receive data and write transmit data.

When transmit data is written into this register, it is transferred tothe outside from bit 7 in synchronization with the SCL clock, andeach time one-bit data is output, the data of this register areshifted by one bit to the left. When data is received, it is input tothis register from bit 0 in synchronization with the SCL clock, andeach time one-bit data is input, the data of this register are shiftedby one bit to the left. The minimum 2 machine cycles are requiredfrom the rising of the SCL clock until input to this register.

The I2C data shift register is in a write enable status only when theI2C-BUS interface enable bit (ES0 bit : bit 3 of address 002E16) ofthe I2C control register is “1”. The bit counter is reset by a write in-struction to the I2C data shift register. When both the ES0 bit andthe MST bit of the I2C status register (address 002D16) are “1,” theSCL is output by a write instruction to the I2C data shift register.Reading data from the I2C data shift register is always enabled re-gardless of the ES0 bit value.

b7 b0 SAD6SAD5SAD4SAD3SAD2SAD1SAD0RWB I2C address register(S0D: address 002C16) Read/write bit Slave address Fig. 28 Structure of I2C address register

[I2C Address Register (S0D)] 002C16

The I2C address register (address 002C16) consists of a 7-bitslave address and a read/write bit. In the addressing mode, theslave address written in this register is compared with the addressdata to be received immediately after the START condition is de-tected.

•Bit 0: Read/write bit (RWB)This is not used in the 7-bit addressing mode. In the 10-bit ad-dressing mode, the first address data to be received is comparedwith the contents (SAD6 to SAD0 + RWB) of the I2C address reg-ister.

The RWB bit is cleared to “0” automatically when the stop condi-tion is detected.

•Bits 1 to 7: Slave address (SAD0–SAD6)

These bits store slave addresses. Regardless of the 7-bit address-ing mode and the 10-bit addressing mode, the address datatransmitted from the master is compared with the contents ofthese bits.

Rev.1.01 Jul 01, 2003 page 30 of 89

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7516 Group

[I2C Clock Control Register (S2)] 002F16

The I2C clock control register (address 002F16) is used to set ACKcontrol, SCL mode and SCL frequency.

•Bits 0 to 4: SCL frequency control bits (CCR0–CCR4)These bits control the SCL frequency. Refer to Table 8.•Bit 5: SCL mode specification bit (FAST MODE)

This bit specifies the SCL mode. When this bit is set to “0,” thestandard clock mode is selected. When the bit is set to “1,” thehigh-speed clock mode is selected.

When connecting the bus of the high-speed mode I2C bus stan-dard (maximum 400 kbits/s), use 8 MHz or more oscillationfrequency f(XIN) and 2 division clock.•Bit 6: ACK bit (ACK BIT)

This bit sets the SDA status when an ACK clock✽ is generated.When this bit is set to “0,” the ACK return mode is selected andSDA goes to “L” at the occurrence of an ACK clock. When the bitis set to “1,” the ACK non-return mode is selected. The SDA isheld in the “H” status at the occurrence of an ACK clock.

However, when the slave address agree with the address data inthe reception of address data at ACK BIT = “0,” the SDA is auto-matically made “L” (ACK is returned). If there is a disagreementbetween the slave address and the address data, the SDA is auto-matically made “H” (ACK is not returned).

✽ACK clock: Clock for acknowledgment

b7 ACK

b0 ACKFAST

3CCR2CCR1CCR0

BITMODECCR4CCR

I2C clock control register(S2 : address 002F16) SCL frequency control bits Refer to Table 8. SCL mode specification bit 0 : Standard clock mode 1 : High-speed clock dACK bit 0 : ACK is returned. 1 : ACK is not td ACK clock bit 0 : No ACK clock 1 : ACK clock Fig. 29 Structure of I2C clock control register

Table 8 Set values of I2C clock control register and SCL

frequency

Setting value ofCCR4–CCR0CCR4CCR3CCR2CCR1CCR00000000

0000000

0000111

0011001

0101010

SCL frequency (Note 1)(at φ = 4 MHz, unit : kHz)

Standard clockHigh-speed clock

modemodeSetting disabledSetting disabledSetting disabled– (Note 2)– (Note 2)10083.3500/CCR value(Note 3)

17.216.616.1

Setting disabledSetting disabledSetting disabled

333250400 (Note 3)

1661000/CCR value

(Note 3)34.5

33.332.3

•Bit 7: ACK clock bit (ACK)

This bit specifies the mode of acknowledgment which is an ac-knowledgment response of data transfer. When this bit is set to“0,” the no ACK clock mode is selected. In this case, no ACK clockoccurs after data transmission. When the bit is set to “1,” the ACKclock mode is selected and the master generates an ACK clockeach completion of each 1-byte data transfer. The device fortransmitting address data and control data releases the SDA atthe occurrence of an ACK clock (makes SDA “H”) and receives theACK bit generated by the data receiving device.

Note:Do not write data into the I2C clock control register during transfer. If

data is written during transfer, the I2C clock generator is reset, sothat data cannot be transferred normally.

…………011

111

111

111

Notes1:Duty of SCL clock output is 50 %. The duty becomes 35 to 45 %

only when the high-speed clock mode is selected and CCR value= 5 (400 kHz, at φ = 4 MHz). “H” duration of the clock fluctuatesfrom –4 to +2 machine cycles in the standard clock mode, andfluctuates from –2 to +2 machine cycles in the high-speed clockmode. In the case of negative fluctuation, the frequency does notincrease because “L” duration is extended instead of “H” durationreduction.

These are value when SCL clock synchronization by the synchro-nous function is not performed. CCR value is the decimalnotation value of the SCL frequency control bits CCR4 to CCR0.2:Each value of SCL frequency exceeds the limit at φ = 4 MHz ormore. When using these setting value, use φ of 4 MHz or less.3:The data formula of SCL frequency is described below:φ/(8 ✕ CCR value) Standard clock mode

φ/(4 ✕ CCR value) High-speed clock mode (CCR value ≠ 5)φ/(2 ✕ CCR value) High-speed clock mode (CCR value = 5)Do not set 0 to 2 as CCR value regardless of φ frequency.

Set 100 kHz (max.) in the standard clock mode and 400 kHz(max.) in the high-speed clock mode to the SCL frequency by set-ting the SCL frequency control bits CCR4 to CCR0.

Rev.1.01 Jul 01, 2003 page 31 of 89

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7516 Group[I2C Control Register (S1D)] 002E16The I2C control register (address 002E16) controls data communi-cation format.•Bits 0 to 2: Bit counter (BC0–BC2)These bits decide the number of bits for the next 1-byte data to betransmitted. The I2C interrupt request signal occurs immediatelyafter the number of count specified with these bits (ACK clock isadded to the number of count when ACK clock is selected by ACKclock bit (bit 7 of address 002F16)) have been transferred, andBC0 to BC2 are returned to “0002”.Also when a START condition is received, these bits become“0002” and the address data is always transmitted and received in8 bits.•Bit 3: I2C interface enable bit (ES0)This bit enables to use the multi-master I2C-BUS interface. Whenthis bit is set to “0,” the use disable status is provided, so that theSDA and the SCL become high-impedance. When the bit is set to“1,” use of the interface is enabled.When ES0 = “0,” the following is performed.•PIN = “1,” BB = “0” and AL = “0” are set (which are bits of the I2Cstatus register at address 002D16 ).•Writing data to the I2C data shift register (address 002B16) is dis-abled.•Bit 4: Data format selection bit (ALS)This bit decides whether or not to recognize slave addresses.When this bit is set to “0,” the addressing format is selected, sothat address data is recognized. When a match is found between aslave address and address data as a result of comparison or whena general call (refer to “I2C Status Register,” bit 1) is received,transfer processing can be performed. When this bit is set to “1,”the free data format is selected, so that slave addresses are notrecognized.•Bit 5: Addressing format selection bit (10BIT SAD)This bit selects a slave address specification format. When this bitis set to “0,” the 7-bit addressing format is selected. In this case,only the high-order 7 bits (slave address) of the I2C address regis-ter (address 002C16) are compared with address data. When thisbit is set to “1,” the 10-bit addressing format is selected, and allthe bits of the I2C address register are compared with addressdata.•Bit 6: SDA/SCL pin selection bitThis bit selects the input/output pins of SCL and SDA of the multi-master I2C-BUS interface.•Bit 7: I2C-BUS interface pin input level selection bitThis bit selects the input level of the SCL and SDA pins of themulti-master I2C-BUS interface. SCL Multi-master I2 C-BUS interface TSEL SCL1/P23 SCL2/TxD/P25 TSEL TSEL SDA TSEL SDA1/P22 SDA2/RxD/P24Fig. 30 SDA/SCL pin selection bitb7TISSTSEL10 BITSADb0I2C control register ALSES0BC2BC1BC0(S1D : address 002E16)Bit counter (Number of transmit/receive bits) b2b1b0000: 8001: 7010: 6011: 5100: 4101: 3110: 2111: 1I2C-BUS interface enable bit 0 : Disabled 1 : Enabled Data format selection bit 0 : Addressing format 1 : Free data format Addressing format selection bit 0 : 7-bit addressing format 1 : 10-bit addressing format SDA/SCL pin selection bit 0 : Connect to ports P22, P231 : Connect to ports P24, P25I2C-BUS interface pin input level selection bit 0 : CMOS input1 : SMBUS inputFig. 31 Structure of I2C control registerRev.1.01 Jul 01, 2003 page 32 of 89

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7516 Group

[I2C Status Register (S1)] 002D16

The I2C status register (address 002D16) controls the I2C-BUS in-terface status. The low-order 4 bits are read-only bits and thehigh-order 4 bits can be read out and written to.

Set “00002” to the low-order 4 bits, because these bits become thereserved bits at writing.

•Bit 0: Last receive bit (LRB)

This bit stores the last bit value of received data and can also beused for ACK receive confirmation. If ACK is returned when anACK clock occurs, the LRB bit is set to “0.” If ACK is not returned,this bit is set to “1.” Except in the ACK mode, the last bit value ofreceived data is input. The state of this bit is changed from “1” to“0” by executing a write instruction to the I2C data shift register(address 002B16).

•Bit 1: General call detecting flag (AD0)

When the ALS bit is “0”, this bit is set to “1” when a general call✽whose address data is all “0” is received in the slave mode. By ageneral call of the master device, every slave device receives con-trol data after the general call. The AD0 bit is set to “0” bydetecting the STOP condition or START condition, or reset.

✽General call:The master transmits the general call address “0016” to all

slaves.

•Bit 2: Slave address comparison flag (AAS)

This flag indicates a comparison result of address data when theALS bit is “0”.

➀In the slave receive mode, when the 7-bit addressing format isselected, this bit is set to “1” in one of the following conditions:• The address data immediately after occurrence of a STARTcondition agrees with the slave address stored in the high-or-der 7 bits of the I2C address register (address 002C16).•A general call is received.

➁In the slave receive mode, when the 10-bit addressing format isselected, this bit is set to “1” with the following condition:

•When the address data is compared with the I2C address reg-ister (8 bits consisting of slave address and RWB bit), the firstbytes agree.

➂ This bit is set to “0” by executing a write instruction to the I2Cdata shift register (address 002B16) when ES0 is set to “1” orreset.

•Bit 3: Arbitration lost✽ detecting flag (AL)

In the master transmission mode, when the SDA is made “L” byany other device, arbitration is judged to have been lost, so thatthis bit is set to “1.” At the same time, the TRX bit is set to “0,” sothat immediately after transmission of the byte whose arbitrationwas lost is completed, the MST bit is set to “0.” The arbitration lostcan be detected only in the master transmission mode. When ar-bitration is lost during slave address transmission, the TRX bit isset to “0” and the reception mode is set. Consequently, it becomespossible to detect the agreement of its own slave address and ad-dress data transmitted by another master device.

✽Arbitration lost :The status in which communication as a master is dis-abled.

•Bit 4: SCL pin low hold bit (PIN)

This bit generates an interrupt request signal. Each time 1-bytedata is transmitted, the PIN bit changes from “1” to “0.” At thesame time, an interrupt request signal occurs to the CPU. The PINbit is set to “0” in synchronization with a falling of the last clock (in-cluding the ACK clock) of an internal clock and an interruptrequest signal occurs in synchronization with a falling of the PINbit. When the PIN bit is “0,” the SCL is kept in the “0” state andclock generation is disabled. Figure 33 shows an interrupt requestsignal generating timing chart.

The PIN bit is set to “1” in one of the following conditions:

•Executing a write instruction to the I2C data shift register (ad-dress 002B16). (This is the only condition which the prohibition ofthe internal clock is released and data can be communicated ex-cept for the start condition detection.)•When the ES0 bit is “0”•At reset

•When writing “1” to the PIN bit by software

The conditions in which the PIN bit is set to “0” are shown below:•Immediately after completion of 1-byte data transmission (includ-ing when arbitration lost is detected)

•Immediately after completion of 1-byte data reception

•In the slave reception mode, with ALS = “0” and immediately af-ter completion of slave address agreement or general calladdress reception

•In the slave reception mode, with ALS = “1” and immediately af-ter completion of address data reception•Bit 5: Bus busy flag (BB)

This bit indicates the status of use of the bus system. When thisbit is set to “0,” this bus system is not busy and a START conditioncan be generated. The BB flag is set/reset by the SCL, SDA pinsinput signal regardless of master/slave. This flag is set to “1” bydetecting the start condition, and is set to “0” by detecting the stopcondition. The condition of these detecting is set by the start/stopcondition setting bits (SSC4–SSC0) of the I2C start/stop conditioncontrol register (address 003016). When the ES0 bit of the I2Ccontrol register (address 002E16) is “0” or reset, the BB flag is setto “0.”

For the writing function to the BB flag, refer to the sections“START Condition Generating Method” and “STOP Condition Gen-erating Method” described later.

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7516 Group

•Bit 6: Communication mode specification bit (transfer direc-tion specification bit: TRX)

This bit decides a direction of transfer for data communication.When this bit is “0,” the reception mode is selected and the data ofa transmitting device is received. When the bit is “1,” the transmis-sion mode is selected and address data and control data areoutput onto the SDA in synchronization with the clock generatedon the SCL.

This bit is set/reset by software and hardware. About set/reset byhardware is described below. This bit is set to “1” by hardwarewhen all the following conditions are satisfied:• When ALS is “0”

•In the slave reception mode or the slave transmission mode•When the R/W bit reception is “1”

This bit is set to “0” in one of the following conditions:•When arbitration lost is detected.•When a STOP condition is detected.

•When writing “1” to this bit by software is invalid by the STARTcondition duplication preventing function (Note).

•With MST = “0” and when a START condition is detected.•With MST = “0” and when ACK non-return is detected.•At reset

•Bit 7: Communication mode specification bit (master/slave

specification bit: MST)

This bit is used for master/slave specification for data communica-tion. When this bit is “0,” the slave is specified, so that a STARTcondition and a STOP condition generated by the master are re-ceived, and data communication is performed in synchronizationwith the clock generated by the master. When this bit is “1,” themaster is specified and a START condition and a STOP conditionare generated. Additionally, the clocks required for data communi-cation are generated on the SCL.

This bit is set to “0” in one of the following conditions.

•Immediately after completion of 1-byte data transfer when arbi-tration lost is detected

•When a STOP condition is detected.

•Writing “1” to this bit by software is invalid by the START condi-tion duplication preventing function (Note).•At reset

Note:START condition duplication preventing function

The MST, TRX, and BB bits is set to “1” at the same time after con-firming that the BB flag is “0” in the procedure of a START conditionoccurrence. However, when a START condition by another masterdevice occurs and the BB flag is set to “1” immediately after the con-tents of the BB flag is confirmed, the START condition duplicationpreventing function makes the writing to the MST and TRX bits in-valid. The duplication preventing function becomes valid from therising of the BB flag to reception completion of slave address.

b7 b0I2C status register(S1 : address 002D16) Last receive bit (Note) 0 :Last bit = “0” 1 :Last bit = “1” General call detecting flag(Note) 0 :No general call detected 1 :General call detected Slave address comparison flag (Note) 0 : Address disagreement 1 : Address agreement Arbitration lost detecting flag(Note) 0 :Not detected 1 :Detected SCL pin low hold bit 0 : SCL pin low hold 1 : SCL pin low releaseBus busy flag 0 : Bus free 1 : Bus busy Communication mode specification bits 00 :Slave receive mode 01 :Slave transmit mode 10 :Master receive mode 11 :Master transmit mode MSTTRXBBPINALAASAD0LRB Note: These bits and flags can be read out, but cannotbe written.Write “0” to these bits at writing.Fig. 32 Structure of I2C status register

SCL PINIICIRQFig. 33 Interrupt request signal generating timing

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7516 GroupSTART Condition Generating MethodWhen writing “1” to the MST, TRX, and BB bits of the I2C statusregister (address 002D16) at the same time after writing the slaveaddress to the I2C data shift register (address 002B16) with thecondition in which the ES0 bit of the I2C control register (address002E16) and the BB flag are “0”, a START condition occurs. Afterthat, the bit counter becomes “0002” and an SCL for 1 byte is out-put. The START condition generating timing is different in thestandard clock mode and the high-speed clock mode. Refer toFigure 34, the START condition generating timing diagram, andTable 9, the START condition generating timing table.START/STOP Condition Detecting OperationThe START/STOP condition detection operations are shown inFigures 36, 37, and Table 11. The START/STOP condition is setby the START/STOP condition set bit.The START/STOP condition can be detected only when the inputsignal of the SCL and SDA pins satisfy three conditions: SCL re-lease time, setup time, and hold time (see Table 11).The BB flag is set to “1” by detecting the START condition and isreset to “0” by detecting the STOP condition.The BB flag set/reset timing is different in the standard clock modeand the high-speed clock mode. Refer to Table 11, the BB flag set/reset time.Note:When a STOP condition is detected in the slave mode (MST = 0), aninterrupt request signal “IICIRQ” occurs to the CPU. I2C status register write signal SCLSDA Setuptime Hold timeSCLSDA SCL release time Hold time BB flag reset time SetuptimeFig. 34 START condition generating timing diagramTable 9 START condition generating timing tableStandard clock modeHigh-speed clock modeItem5.0 µs (20 cycles)2.5 µs (10 cycles)Setup time5.0 µs (20 cycles)2.5 µs (10 cycles)Hold timeNote:Absolute time at φ = 4 MHz. The value in parentheses denotes thenumber of φ cycles.BB flagFig. 36 START condition detecting timing diagramSCL release timeSCLSDABB flagSetuptime Hold time BB flag reset timeSTOP Condition Generating MethodWhen the ES0 bit of the I2C control register (address 002E16) is“1,” write “1” to the MST and TRX bits, and write “0” to the BB bitof the I2C status register (address 002D16) simultaneously. Then aSTOP condition occurs. The STOP condition generating timing isdifferent in the standard clock mode and the high-speed clockmode. Refer to Figure 35, the STOP condition generating timingdiagram, and Table 10, the STOP condition generating timingtable. I2C status register write signal Fig. 37 STOP condition detecting timing diagramTable 11 START condition/STOP condition detecting conditionsStandard clock modeHigh-speed clock modeSCL release timeSetup timeHold timeBB flag set/reset timeSSC value + 1 cycle (6.25 µs)4 cycles (1.0 µs)SSC value + 1cycle < 4.0 µs (3.125 µs)2 cycles (1.0 µs)2SSC value + 1cycle < 4.0 µs (3.125 µs)2 cycles (0.5 µs)2SSC value –1+ 2 cycles (3.375 µs)3.5 cycles (0.875 µs)2SCLSDASetuptimeHold timeNote:Unit : Cycle number of system clock φSSC value is the decimal notation value of the START/STOP condi-tion set bits SSC4 to SSC0. Do not set “0” or an odd number to SSCvalue. The value in parentheses is an example when the I2C START/STOP condition control register is set to “1816” at φ = 4 MHz.Fig. 35 STOP condition generating timing diagramTable 10 STOP condition generating timing tableStandard clock modeHigh-speed clock modeItem5.0 µs (20 cycles)3.0 µs (12 cycles)Setup time4.5 µs (18 cycles)2.5 µs (10 cycles)Hold timeNote:Absolute time at φ = 4 MHz. The value in parentheses denotes thenumber of φ cycles.Rev.1.01 Jul 01, 2003 page 35 of 89

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7516 Group

[I2C START/STOP Condition Control Register(S2D)] 003016

The I2C START/STOP condition control register (address 003016)controls START/STOP condition detection.

•Bits 0 to 4: START/STOP condition set bit (SSC4–SSC0)

SCL release time, setup time, and hold time change the detectioncondition by value of the main clock divide ratio selection bit andthe oscillation frequency f(XIN) because these time are measuredby the internal system clock. Accordingly, set the proper value tothe START/STOP condition set bits (SSC4 to SSC0) in consideredof the system clock frequency. Refer to Table 11.

Do not set “000002” or an odd number to the START/STOP condi-tion set bit (SSC4 to SSC0).

Refer to Table 12, the recommended set value to START/STOPcondition set bits (SSC4–SSC0) for each oscillation frequency.•Bit 5: SCL/SDA interrupt pin polarity selection bit (SIP)

An interrupt can occur when detecting the falling or rising edge ofthe SCL or SDA pin. This bit selects the polarity of the SCL orSDA pin interrupt pin.

•Bit 6: SCL/SDA interrupt pin selection bit (SIS)

This bit selects the pin of which interrupt becomes valid betweenthe SCL pin and the SDA pin.

Note: When changing the setting of the SCL/SDA interrupt pin polarity se-lection bit, the SCL/SDA interrupt pin selection bit, or the I2C-BUSinterface enable bit ES0, the SCL/SDA interrupt request bit may beset. When selecting the SCL/SDA interrupt source, disable the inter-rupt before the SCL/SDA interrupt pin polarity selection bit, the SCL/SDA interrupt pin selection bit, or the I2C-BUS interface enable bitES0 is set. Reset the request bit to “0” after setting these bits, andenable the interrupt.

Address Data Communication

There are two address data communication formats, namely, 7-bitaddressing format and 10-bit addressing format. The respectiveaddress communication formats are described below.➀ 7-bit addressing format

To adapt the 7-bit addressing format, set the 10BIT SAD bit ofthe I2C control register (address 002E16) to “0.” The first 7-bitaddress data transmitted from the master is compared with thehigh-order 7-bit slave address stored in the I2C address register(address 002C16). At the time of this comparison, address com-parison of the RWB bit of the I2C address register (address002C16) is not performed. For the data transmission formatwhen the 7-bit addressing format is selected, refer to Figure 39,(1) and (2).

➁ 10-bit addressing format

To adapt the 10-bit addressing format, set the 10BIT SAD bit ofthe I2C control register (address 002E16) to “1.” An addresscomparison is performed between the first-byte address datatransmitted from the master and the 8-bit slave address storedin the I2C address register (address 002C16). At the time of thiscomparison, an address comparison between the RWB bit ofthe I2C address register (address 002C16) and the R/W bitwhich is the last bit of the address data transmitted from themaster is made. In the 10-bit addressing mode, the RWB bitwhich is the last bit of the address data not only specifies thedirection of communication for control data, but also is pro-cessed as an address data bit.

When the first-byte address data agree with the slave address,the AAS bit of the I2C status register (address 002D16) is set to“1.” After the second-byte address data is stored into the I2Cdata shift register (address 002B16), perform an address com-parison between the second-byte data and the slave addressby software. When the address data of the 2 bytes agree withthe slave address, set the RWB bit of the I2C address register(address 002C16) to “1” by software. This processing can makethe 7-bit slave address and R/W data agree, which are re-ceived after a RESTART condition is detected, with the value ofthe I2C address register (address 002C16). For the data trans-mission format when the 10-bit addressing format is selected,refer to Figure 39, (3) and (4).

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7516 Group b7 SISSIPSSC4SSC3SSC2SSC1SSC0b0 I2C START/STOP condition control register (S2D : address 003016) START/STOP condition set bitSCL/SDA interrupt pin polarity selection bit0 :Falling edge active 1 :Rising edge active SCL/SDA interrupt pin selection bit0 :SDA valid1 :SCL validReservedDo not write “1” to this bit.Fig. 38 Structure of I2C START/STOP condition control registerTable 12 Recommended set value to START/STOP condition set bits (SSC4–SSC0) for each oscillation frequencyOscillationfrequencyf(XIN) (MHz)8842Main clockdivide ratio2822Systemclock φ(MHz)4121START/STOPconditioncontrol registerXXX11010XXX11000XXX00100XXX01100XXX01010XXX00100SCL release time(µs)6.75 µs (27 cycles)6.25 µs (25 cycles)5.0 µs (5 cycles)6.5 µs (13 cycles)5.5 µs (11 cycles)5.0 µs (5 cycles)Setup time(µs)3.375 µs (13.5 cycles)3.125 µs (12.5 cycles)2.5 µs (2.5 cycles)3.25 µs (6.5 cycles)2.75 µs (5.5 cycles)2.5 µs (2.5 cycles)Hold time(µs)3.375 µs (13.5 cycles)3.125 µs (12.5 cycles)2.5 µs (2.5 cycles)3.25 µs (6.5 cycles)2.75 µs (5.5 cycles)2.5 µs (2.5 cycles)Note:Do not set an odd number to the START/STOP condition set bit (SSC4 to SSC0). (1) A master-transmitter transnmits data to a slave-receiverSSlave addressR/W 7 bits“0”A DataA Data A/AP1 to 8 bits (2) A master-receiver receives data from a slave-transmitterS Slave addressR/W 7 bits “1”A DataA Data 1 to 8 bitsAP 1 to 8 bits 1 to 8 bits (3) A master-transmitter transmits data to a slave-receiver with a 10-bit address Slave addressSlave address A/AADataA2nd bytesDataSR/WA1st 7 bits 1 to 8 bits1 to 8 bits7 bits“0”8 bits (4) A master-receiver receives data from a slave-transmitter with a 10-bit address Slave address Slave address SrSlave addressR/WA2nd bytesASR/WA1st 7 bits1st 7 bits 7 bits “0” 8 bits 7 bits “1”P Data 1 to 8 bitsA Data 1 to 8 bitsAP S : START conditionA : ACK bitSr : Restart condition P : STOP conditionR/W : Read/Write bit: Master to slave: Slave to masterFig. 39 Address data communication formatRev.1.01 Jul 01, 2003 page 37 of 89

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7516 Group

Example of Master Transmission

An example of master transmission in the standard clock mode, atthe SCL frequency of 100 kHz and in the ACK return mode isshown below.

➀ Set a slave address in the high-order 7 bits of the I2C addressregister (address 002C16) and “0” into the RWB bit.

➁ Set the ACK return mode and SCL = 100 kHz by setting “8516”in the I2C clock control register (address 002F16).

➂ Set “0016” in the I2C status register (address 002D16) so thattransmission/reception mode can become initializing condition.➃ Set a communication enable status by setting “0816” in the I2Ccontrol register (address 002E16).

➄ Confirm the bus free condition by the BB flag of the I2C statusregister (address 002D16).

➅ Set the address data of the destination of transmission in thehigh-order 7 bits of the I2C data shift register (address 002B16)and set “0” in the least significant bit.

➆ Set “F016” in the I2C status register (address 002D16) to gener-ate a START condition. At this time, an SCL for 1 byte and anACK clock automatically occur.

➇ Set transmit data in the I2C data shift register (address 002B16).At this time, an SCL and an ACK clock automatically occur.

➈ When transmitting control data of more than 1 byte, repeat step➇.

➉ Set “D016” in the I2C status register (address 002D16) to gener-ate a STOP condition if ACK is not returned from slavereception side or transmission ends.

Example of Slave Reception

An example of slave reception in the high-speed clock mode, atthe SCL frequency of 400 kHz, in the ACK non-return mode andusing the addressing format is shown below.

➀ Set a slave address in the high-order 7 bits of the I2C addressregister (address 002C16) and “0” in the RWB bit.

➁ Set the no ACK clock mode and SCL = 400 kHz by setting“2516” in the I2C clock control register (address 002F16).

➂ Set “0016” in the I2C status register (address 002D16) so thattransmission/reception mode can become initializing condition.➃ Set a communication enable status by setting “0816” in the I2Ccontrol register (address 002E16).

➄ When a START condition is received, an address comparison isperformed.

➅ •When all transmitted addresses are “0” (general call):

AD0 of the I2C status register (address 002D16) is set to “1”and an interrupt request signal occurs.

• When the transmitted addresses agree with the address setin ➀:

AAS of the I2C status register (address 002D16) is set to “1”and an interrupt request signal occurs.

• In the cases other than the above AD0 and AAS of the I2C sta-tus register (address 002D16) are set to “0” and no interruptrequest signal occurs.

➆ Set dummy data in the I2C data shift register (address 002B16).➇ When receiving control data of more than 1 byte, repeat step ➆.➈ When a STOP condition is detected, the communication ends.

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7516 Group

sPrecautions when using multi-master I2C-BUS interface

(1) Read-modify-write instruction

The precautions when the read-modify-write instruction such asSEB, CLB etc. is executed for each register of the multi-masterI2C-BUS interface are described below.

•I2C data shift register (S0: address 002B16)

When executing the read-modify-write instruction for this regis-ter during transfer, data may become a value not intended.•I2C address register (S0D: address 002C16)

When the read-modify-write instruction is executed for this regis-ter at detecting the STOP condition, data may become a valuenot intended. It is because H/W changes the read/write bit(RWB) at the above timing.

•I2C status register (S1: address 002D16)

Do not execute the read-modify-write instruction for this registerbecause all bits of this register are changed by H/W.•I2C control register (S1D: address 002E16)

When the read-modify-write instruction is executed for this regis-ter at detecting the START condition or at completing the bytetransfer, data may become a value not intended. Because H/Wchanges the bit counter (BC0-BC2) at the above timing.•I2C clock control register (S2: address 002F16)

The read-modify-write instruction can be executed for this regis-ter.

•I2C START/STOP condition control register (S2D: address003016)

The read-modify-write instruction can be executed for this regis-ter.

(2) START condition generating procedure using multi-master

1. Procedure example (The necessary conditions of the generat-ing procedure are described in Items 2 to 5 below.LDA —SEI

BBS 5, S1, BUSBUSYBUSFREE:STA S0

LDM #$F0, S1CLI

••••••

5. Disable interrupts during the following three process steps:• BB flag confirming

• Writing of slave address value

• Trigger of START condition generating

When the condition of the BB flag is bus busy, enable interruptsimmediately.(3) RESTART condition generating procedure

1. Procedure example (The necessary conditions for the proce-dure are described in items 2 to 4 below.)

Execute the following procedure when the PIN bit is “0.”

•••

LDM #$00, S1LDA —SEISTA S0

LDM #$F0, S1CLI

•••

(Select slave receive mode)

(Take out of slave address value)(Disable interrupt)

(Write slave address value)

(Trigger RESTART condition generation)(Enable interrupt)

2. Select the slave receive mode when the PIN bit is “0.” Do notwrite “1” to the PIN bit. Neither “0” nor “1” is specified as input tothe BB bit.

The TRX bit becomes “0” and the SDA pin is released.

3. The SCL pin is released by writing the slave address value tothe I2C data shift register.

4. Disable interrupts during the following two process steps:• Write slave address value

• Trigger RESTART condition generation

(4) Writing to I2C status register

Do not execute an instruction to set the PIN bit to “1” from “0” andan instruction to set the MST and TRX bits to “0” from “1” simulta-neously. Because it may enter the state that the SCL pin isreleased and the SDA pin is released after about one machinecycle. Do not execute an instruction to set the MST and TRX bitsto “0” from “1” simultaneously when the PIN bit is “1.” Because itmay become the same as above.

(5) Process of after STOP condition generating

Do not write data in the I2C data shift register S0 and the I2C sta-tus register S1 until the bus busy flag BB becomes “0” aftergenerating the STOP condition in the master mode. Because theSTOP condition waveform might not be normally generated.Reading to the above registers do not have the problem.

(Taking out of slave address value)(Interrupt disabled)

(BB flag confirming and branch process)(Writing of slave address value)

(Trigger of START condition generating)(Interrupt enabled)

BUSBUSY:CLI•

••

(Interrupt enabled)

2. Use “Branch on Bit Set” of “BBS 5, $002D, –” for the BB flagconfirming and branch process.

3. Use “STA $2B, STX $2B” or “STY $2B” of the zero page ad-dressing instruction for writing the slave address value to theI2C data shift register.

4. Execute the branch instruction of Item 2 and the store instruc-tion of Item 3 continuously, as shown in the procedure exampleabove.

Rev.1.01 Jul 01, 2003 page 39 of 89

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7516 GroupPULSE WIDTH MODULATION (PWM)The 7516 group has a PWM function with an 8-bit resolution,based on a signal that is the clock input XIN or that clock input di-vided by 2.PWM OperationWhen bit 0 (PWM enable bit) of the PWM control register is set to“1”, operation starts by initializing the PWM output circuit, andpulses are output starting at an “H”.If the PWM register or PWM prescaler is updated during PWMoutput, the pulses will change in the cycle after the one in whichthe change was made.Data SettingThe PWM output pin also functions as port P44. Set the PWMperiod by the PWM prescaler, and set the “H” term of output pulseby the PWM register.If the value in the PWM prescaler is n and the value in the PWMregister is m (where n = 0 to 255 and m = 0 to 255) :PWM period = 255 ✕ (n+1) / f(XIN)= 31.875 ✕ (n+1) µs(when f(XIN) = 8 MHz,count source selection bit = “0”)Output pulse “H” term = PWM period ✕ m / 255= 0.125 ✕ (n+1) ✕ m µs (when f(XIN) = 8 MHz,count source selection bit = “0”) 31.875 ✕ m ✕ (n+1)µs255PWM output T = [31.875 ✕ (n+1)] µs m: Contents of PWM registern : Contents of PWM prescalerT : PWM period (when f(XIN) = 8 MHz, count source selection bit = “0”)Fig. 40 Timing of PWM period Data bus PWM prescaler pre-latch PWM register pre-latchTransfer control circuitPWM prescaler latchCount source selection bit “0” PWM prescaler1/2 “1”PWM register latchPort P44PWM register XIN(XCIN at low-speed mode) Port P44 latch PWM enable bitFig. 41 Block diagram of PWM functionRev.1.01 Jul 01, 2003 page 40 of 89

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7516 Group b7 b0 PWM control register(PWMCON : address 001D16) PWM function enable bit 0: PWM disabled1: PWM enabledCo unt source selection bit0: f(XIN) (f(XCIN) at low-speed mode)1: f(XIN)/2 (f(XCIN)/2 at low-speed mode)Not used (return “0” when read)Fig. 42 Structure of PWM control registerA PWM outputT PWM registerwrite signalBC B=CT2TT(Changes “H” term from “A” to “B”.)T2 PWM prescalerwrite signal(Changes PWM period from “T” to “T2”.)When the contents of the PWM register or PWM prescaler have changed, the PWMoutput will change from the next period after the change.Fig. 43 PWM output timing when PWM register or PWM prescaler is changedsNoteThe PWM starts after the PWM function enable bit is set to enable and “L” level is output from the PWM pin.The length of this “L” level output is as follows:n+12 • f(XIN)n+1f(XIN)sec(Count source selection bit = 0, where n is the value set in the prescaler)sec(Count source selection bit = 1, where n is the value set in the prescaler)Rev.1.01 Jul 01, 2003 page 41 of 89

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7516 GroupA-D CONVERTER[A-D Conversion Registers (ADL, ADH)]003516, 003616The A-D conversion registers are read-only registers that store theresult of an A-D conversion. Do not read these registers during anA-D conversionb7b0AD control register(ADCON : address 003416)Analog input pin selection bits b2 b1 b0 [AD Control Register (ADCON)] 003416The AD control register controls the A-D conversion process. Bits0 to 2 select a specific analog input pin. Bit 4 indicates thecompletion of an A-D conversion. The value of this bit remains at“0” during an A-D conversion and changes to “1” when an A-Dconversion ends. Writing “0” to this bit starts the A-D conversion.0 0 0: P30/AN00 0 1: P31/AN10 1 0: P32/AN20 1 1: P33/AN31 0 0: P34/AN41 0 1: P35/AN51 1 0: P36/AN61 1 1: P37/AN7Not used (returns “0” when read)A-D conversion completion bit0: Conversion in progress1: Conversion completedNot used (returns “0” when read)Comparison Voltage GeneratorThe comparison voltage generator divides the voltage betweenAVSS and VREF into 1024 and outputs the divided voltages.Fig. 44 Structure of AD control registerChannel SelectorThe channel selector selects one of ports P30/AN0 to P37/AN7 andinputs the voltage to the comparator.10-bit reading(Read address 003616 before 003516)b7Comparator and Control CircuitThe comparator and control circuit compare an analog input volt-age with the comparison voltage, and the result is stored in theA-D conversion registers. When an A-D conversion is completed,the control circuit sets the A-D conversion completion bit and theA-D interrupt request bit to “1”.Note that because the comparator consists of a capacitor cou-pling, set f(XIN) to 500 kHz or more during an A-D conversion.When the A-D converter is operated at low-speed mode, f(XIN)and f(XCIN) do not have the lower limit of frequency, because ofthe A-D converter has a built-in self-oscillation circuit.(Address 003616)b7b0b9b8b0(Address 003516)b7b6b5b4b3b2b1b0Note : The high-order 6 bits of address 003616 become “0”at reading.8-bit reading (Read only address 003516)b7(Address 003516)b0b9b8b7b6b5b4b3b2Fig. 45 Structure of A-D conversion registersData busAD control register(Address 003416) b7b03P30/AN0P31/AN1P32/AN2P33/AN3P34/AN4P35/AN5P36/AN6P37/AN7A-D control circuitChannel selectorA-D interrupt requestComparatorA-D conversion high-order register(Address 003616)A-D conversion low-order register(Address 003516) 10Resistor ladderVREF AVSSFig. 46 Block diagram of A-D converterRev.1.01 Jul 01, 2003 page 42 of 89

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7516 GroupWATCHDOG TIMERThe watchdog timer gives a mean of returning to the reset statuswhen a program cannot run on a normal loop (for example, be-cause of a software run-away). The watchdog timer consists of an8-bit watchdog timer L and an 8-bit watchdog timer H.Standard Operation of Watchdog TimerWhen any data is not written into the watchdog timer control reg-ister (address 003916) after reset, the watchdog timer is in thestop state. The watchdog timer starts to count down by writing anoptional value into the watchdog timer control register (address003916) and an internal reset occurs at an underflow of the watch-dog timer H.Accordingly, programming is usually performed so that writing tothe watchdog timer control register (address 003916) may bestarted before an underflow. When the watchdog timer control reg-ister (address 003916) is read, the values of the high-order 6 bitsof the watchdog timer H, STP instruction disable bit, and watch-dog timer H count source selection bit are read.qInitial value of watchdog timerAt reset or writing to the watchdog timer control register (address003916), each watchdog timer H and L are set to “FF16.” “FF16” is set when watchdog timer control register is written to. 1/16 Watchdog timer L (8)qWatchdog timer H count source selection bit operationBit 7 of the watchdog timer control register (address 003916) per-mits selecting a watchdog timer H count source. When this bit isset to “0”, the count source becomes the underflow signal ofwatchdog timer L. The detection time is set to 131.072 ms at f(XIN)= 8 MHz frequency and 32.768 s at f(XCIN) = 32 kHz frequency.When this bit is set to “1”, the count source becomes the signaldivided by 16 for f(XIN) (or f(XCIN)). The detection time in this caseis set to 512 µs at f(XIN) = 8 MHz frequency and 128 ms at f(XCIN)= 32 kHz frequency. This bit is cleared to “0” after reset.qOperation of STP instruction disable bitBit 6 of the watchdog timer control register (address 003916) per-mits disabling the STP instruction when the watchdog timer is inoperation.When this bit is “0”, the STP instruction is enabled.When this bit is “1”, the STP instruction is disabled, once the STPinstruction is executed, an internal reset occurs. When this bit isset to “1”, it cannot be rewritten to “0” by program. This bit iscleared to “0” after reset.XCIN “10”Main clock divisionratio selection bits(Note)XIN “00”“01” “0” “1” Watchdog timer H (8) Data bus “FF16” is set when watchdog timer control register is written to.Watchdog timer H count source selection bitSTP instruction disable bitSTP instruction RESET Resetcircuit Internal reset Note: Any one of high-speed, middle-speed or low-speed mode is selected by bits 7 and 6 of the CPU mode register. Fig. 47 Block diagram of Watchdog timer b7 b0Watchdog timer control register(WDTCON : address 003916) Watchdog timer H (for read-out of high-order 6 bit)STP instruction disable bit0: STP instruction enabled1: STP instruction disabledWatchdog timer H count source selection bit0: Watchdog timer L underflow1: f(XIN)/16 or f(XCIN)/16Fig. 48 Structure of Watchdog timer control registerRev.1.01 Jul 01, 2003 page 43 of 89

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7516 GroupRESET CIRCUITTo reset the microcomputer, RESET pin must be held at an “L”level for 20 cycles or more of XIN. Then the RESET pin is returnedto an “H” level (the power source voltage must be between 2.7 Vand 5.5 V, and the oscillation must be stable), reset is released.After the reset is completed, the program starts from the addresscontained in address FFFD16 (high-order byte) and addressFFFC16 (low-order byte). Make sure that the reset input voltage isless than 0.54 V for VCC of 2.7 V. RESET VCC Power source voltage0VReset input voltage0V Poweron (Note) 0.2VCC Note : Reset release voltage; Vcc = 2.7 V RESETVCC Power source voltage detection circuit Fig. 49 Reset circuit exampleXIN φRESET RESETOUTAddress??????FFFC?ADLFFFD ADH,LReset address from the vector table. Data SYNC?ADH XIN: 8 to 13 clock cycles Notes1: The frequency relation of f(XIN) and f(φ) is f(XIN) = 8 • f(φ).2: The question marks (?) indicate an undefined state that depends on the previous state. 3: All signals except XIN and RESET are internals.Fig. 50 Reset sequenceRev.1.01 Jul 01, 2003 page 44 of 89

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7516 Group

AddressRegister contents (1)(2)(3)(4)(5)(6)(7)(8)(9) Port P0 (P0)Port P0 direction register (P0D)Port P1 (P1)Port P1 direction register (P1D)Port P2 (P2)Port P2 direction register (P2D)Port P3 (P3)Port P3 direction register (P3D)Port P4 (P4) AddressRegister contents (37)A-D control register (ADCON) 00341600010000000016000116000216000316000416000516000616000716000816000916001516 00160016001600160016001600160016001600160016(38)A-D conversion low-order register (ADL)003516XXXXXXXX(39)A-D conversion high-order register (ADH)003616000000XX(40)MISRG(41)Watchdog timer control register (WDTCON)(42)Interrupt edge selection register (INTEDGE)(43)CPU mode register (CPUM)(44)Interrupt request register 1 (IREQ1)(45)Interrupt request register 2 (IREQ2)(46)Interrupt control register 1 (ICON1)(47)Interrupt control register 2 (ICON2)(48)Processor status register (49)Program counter003816 001600391600111111003A160016003B1601001000003C16003D16003E16003F16(PS)(PCH)(PCL)0016001600160016XXXXX1XX (10)Port P4 direction register (P4D)(11)Serial I/O2 control register 1 (SIO2CON1)(12)Serial I/O2 control register 2 (SIO2CON2)(13)Serial I/O2 register (SIO2)(14)Transmit/Receive buffer register (TB/RB)(15)Serial I/O1 status register (SIOSTS)(16)Serial I/O1 control register (SIOCON)(17)UART control register (UARTCON)(18)Baud rate generator (BRG)(19)PWM control register (PWMCON)(20)PWM prescaler (PREPWM)(21)PWM register (PWM)(22)Prescaler 12 (PRE12)(23)Timer 1 (T1)(24)Timer 2 (T2)(25)Timer XY mode register (TM)(26)Prescaler X (PREX)(27)Timer X (TX)(28)Prescaler Y (PREY)(29)Timer Y (TY)(30)Timer count source selection register (TCSS)(31)I2C data shift register (S0)(32)I2C address regiter (S0D)(33)I2C status register (S1)(34)I2C control register (S1D)(35)I2C clock control register (S2)00161600000111001716XXXXXXXX001816XXXXXXXX00191610000000001A160016FFFD16 contentsFFFC16 contents Note :X : Not fixedSince the initial values for other than above mentioned registers and RAM contents are indefinite at reset, they must be set.001B1611100000001C16XXXXXXXX001D160016001E16XXX XXXXX001F16XXXXXXXX002016002116002216002316002416002516002616002716002816FF16011600160016FF16FF16FF16FF160016002B16XXXXXXXX002C160016002D160001000X002E16002F1600160016(36)I2C start/stop condition control register (S2D)003016000XXXXXFig. 51 Internal status at reset

Rev.1.01 Jul 01, 2003 page 45 of 89

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7516 GroupCLOCK GENERATING CIRCUITThe 7516 group has two built-in oscillation circuits: main clock XIN-XOUT oscillation circuit and sub clock XCIN-XCOUT oscillationcircuit. An oscillation circuit can be formed by connecting a reso-nator between XIN and XOUT (XCIN and XCOUT). Use the circuitconstants in accordance with the resonator manufacturer’s recom-mended values. No external resistor is needed between XIN andXOUT since a feed-back resistor exists on-chip. However, an exter-nal feed-back resistor is needed between XCIN and XCOUT.Immediately after power on, only the XIN oscillation circuit startsoscillating, and XCIN and XCOUT pins function as I/O ports.RESET pin until the oscillation is stable since a wait time will notbe generated.(2) Wait modeIf the WIT instruction is executed, the internal clock φ stops at an“H” level, but the oscillator does not stop. The internal clock φ re-starts at reset or when an interrupt is received. Since the oscillatordoes not stop, normal operation can be started immediately afterthe clock is restarted.To ensure that the interrupts will be received to release the STP orWIT state, their interrupt enable bits must be set to “1” before ex-ecuting of the STP or WIT instruction.When releasing the STP state, the prescaler 12 and timer 1 willstart counting the clock XIN divided by 16. Accordingly, set thetimer 1 interrupt enable bit to “0” before executing the STP instruc-tion.Frequency Control(1) Middle-speed modeThe internal clock φ is the frequency of XIN divided by 8. After re-set is released, this mode is selected.(2) High-speed modeThe internal clock φ is half the frequency of XIN.sNoteWhen using the oscillation stabilizing time set after STP instructionreleased bit set to “1”, evaluate time to stabilize oscillation of theused oscillator and set the value to the timer 1 and prescaler 12.(3) Low-speed modeThe internal clock φ is half the frequency of XCIN.sNoteIf you switch the mode between middle/high-speed and low-speed, stabilize both XIN and XCIN oscillations. The sufficient timeis required for the sub-clock to stabilize, especially immediately af-ter power on and at returning from the stop mode. When switchingthe mode between middle/high-speed and low-speed, set the fre-quency on condition that f(XIN) > 3•f(XCIN). XCIN XCOUT XIN XOUT Rf (4) Low power dissipation modeThe low power consumption operation can be realized by stoppingthe main clock XIN in low-speed mode. To stop the main clock, setbit 5 of the CPU mode register to “1.” When the main clock XIN isrestarted (by setting the main clock stop bit to “0”), set sufficienttime for oscillation to stabilize.The sub-clock XCIN-XCOUT oscillation circuit can not directly inputclocks that are generated externally. Accordingly, make sure tocause an external resonator to oscillate. Rd CCINCCOUT CIN COUTFig. 52 Ceramic resonator circuitOscillation Control(1) Stop modeIf the STP instruction is executed, the internal clock φ stops at an“H” level, and XIN and XCIN oscillation stops. When the oscillationstabilizing time set after STP instruction released bit is “0,” theprescaler 12 is set to “FF16” and timer 1 is set to “0116.” When theoscillation stabilizing time set after STP instruction released bit is“1,” set the sufficient time for oscillation of used oscillator to stabi-lize since nothing is set to the prescaler 12 and timer 1.Either XIN or XCIN divided by 16 is input to the prescaler 12 ascount source. Oscillator restarts when an external interrupt is re-ceived, but the internal clock φ is not supplied to the CPU (remainsat “H”) until timer 1 underflows. The internal clock φ is supplied forthe first time, when timer 1 underflows. This ensures time for theclock oscillation using the ceramic resonators to be stabilized.When the oscillator is restarted by reset, apply “L” level to the XCIN XCOUT XIN XOUT Rf Rd CCINCCOUTOpen External oscillationcircuitVcc Vss Fig. 53 External clock input circuitRev.1.01 Jul 01, 2003 page 46 of 89

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7516 GroupsNotes on middle-speed mode automaticswitch set bitWhen the middle-speed mode automatic switch set bit is set to “1”while operating in the low-speed mode, by detecting the rising/fall-ing edge of the SCL or SDA pin, XIN oscillation automatically startsand the mode is automatically switched to the middle-speedmode. The timing which changes from the low-speed mode to themiddle-speed mode can be set as 4.5 to 5.5 cycle, or 6.5 to 7.5cycle in the low-speed mode by the middle-speed mode automaticswitch waiting time set bit. Select according to the oscillation startcharacteristic of the XIN oscillator to be used. b7 b0 MISRG(MISRG : address 003816) Oscillation stabilizing time set after STP instruction released bit0: Automatically set “0116” to Timer 1,“FF16” to Prescaler 121: Automatically set nothing Middle-speed mode automatic switch set bit 0: Not set automatically1: Automatic switching enable (Notes 1, 2)Middle-speed mode automatic switch wait time set bit 0: 4.5 to 5.5 machine cycles1: 6.5 to 7.5 machine cycles Middle-speed mode automatic switch start bit(Depending on program) 0: Invalid1: Automatic switch start (Note 2) Not used (return “0” when read) Notes 1: While operating in the low-speed mode, the mode can be automatically switched to the middle-speed mode by the SCL/SDA interrupt. 2:When the mode is automatically switched from the low-speed mode tothe middle-speed mode, the value of CPU mode register (address 003B16) changes.Fig. 54 Structure of MISRGXCIN XCOUT “1” “0”Port XCswitch bit XIN XOUT Main clock division ratio selection bits (Note 1)Low-speed mode High-speed or middle-speed modeTimer 12 count source selection bit1/2 1/41/2 Prescaler 12FF16 Timer 10116Reset orSTP instruction(Note 2)Main clock division ratio selection bits (Note 1)Middle-speed modeHigh-speed orlow-speed modeMain clock stop bit Timing φ (internal clock)QSR STP instruction WIT instructionSQRQSR STP instruction Reset Reset Interrupt disable flag l Interrupt request Notes 1: Any one of high-speed, middle-speed or low-speed mode is selected by bits 7 and 6 of the CPU mode register.When low-speed mode is selected, set port Xc switch bit (b4) to “1”.2: When bit 0 of MISRG = “0”Fig. 55 System clock generating circuit block diagram (Single-chip mode)Rev.1.01 Jul 01, 2003 page 47 of 89

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7516 Group Reset CM7 = 0CM6 = 1CM5 = 0 (8 MHz oscillating)CM4 = 0 (32 kHz stopped)Middle-speed mode (f(φ) = 1 MHz)CM6“1” ←→ “0” CM7 = 0CM6 = 0CM5 = 0 (8 MHz oscillating)CM4 = 0 (32 kHz stopped)High-speed mode(f(φ) = 4 MHz) M4←”C” “0“1M6→C” ←“1” “0→ C“0M4C” ←“1M6→ “1” ←”→ “0” CM4“1” ←→ “0” Middle-speed mode (f(φ) = 1 MHz)CM7 = 0CM6 = 1CM5 = 0 (8 MHz oscillating)CM4 = 1 (32 kHz oscillating)CM6“1” ←→ “0” CM“07CM” ←“16→ “1” ←”→ “0”CM7 = 0CM6 = 0CM5 = 0 (8 MHz oscillating)CM4 = 1 (32 kHz oscillating)Low-speed mode (f(φ)=16 kHz) CM7 = 1CM6 = 0CM5 = 0 (8 MHz oscillating)CM4 = 1 (32 kHz oscillating) CM7“1” ←→ “0” CM4“1” ←→ “0”High-speed mode(f(φ) = 4 MHz)b7 b4CPU mode register(CPUM : address 003B16) CM4 : Port Xc switch bit 0 : I/O port function (stop oscillating) 1 : XCIN-XCOUT oscillating functionCM5 : Main clock (XIN- XOUT) stop bit 0 : Operating 1 : StoppedCM7, CM6: Main clock division ratio selection bits b7 b6 0 0 : φ = f(XIN)/2 ( High-speed mode) 0 1 : φ = f(XIN)/8 (Middle-speed mode) 1 0 : φ = f(XCIN)/2 (Low-speed mode) 1 1 : Not availableLow-speed mode (f(φ)=16 kHz)CM7 = 1CM6 = 0CM5 = 1 (8 MHz stopped)CM4 = 1 (32 kHz oscillating) Notes1 : Switch the mode by the allows shown between the mode blocks. (Do not switch between the modes directly without an allow.)2 : The all modes can be switched to the stop mode or the wait mode and return to the source mode when the stop mode or the wait mode isended.3 : Timer operates in the wait mode.4 : When bit 0 of MISRG is “0” and the stop mode is ended, a delay of approximately 1 ms occurs by connecting timer 1 in middle/high-speedmode.5 : When bit 0 of MISRG is “0” and the stop mode is ended, the following is performed.(1) After the clock is restarted, a delay of approximately 250 ms occurs in low-speed mode if Timer 12 count source selection bit is “0”.(2) After the clock is restarted, a delay of approximately 16 ms occurs in low-speed mode if Timer 12 count source selection bit is “1”.6 :Wait until oscillation stabilizes after oscillating the main clock XIN before the switching from the low-speed mode to middle/high-speedmode.7 : The example assumes that 8 MHz is being applied to the XIN pin and 32 kHz to the XCIN pin. φ indicates the internal clock.Fig. 56 State transitions of system clockRev.1.01 Jul 01, 2003 page 48 of 89

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7516 Group

FLASH MEMORY MODE

The M37516F8 (flash memory version) has an internal newDINOR (DIvided bit line NOR) flash memory that can be rewrittenwith a single power source when VCC is 5 V, and 2 power sourceswhen VPP is 5 V and VCC is 3.0-5.5 V in the CPU rewrite and stan-dard serial I/O modes.

For this flash memory, three flash memory modes are available inwhich to read, program, and erase: the parallel I/O and standardserial I/O modes in which the flash memory can be manipulatedusing a programmer and the CPU rewrite mode in which the flashmemory can be manipulated by the Central Processing Unit(CPU).

Summary

Table 13 lists the summary of the M37516F8 (flash memory ver-sion).

The flash memory of the M37516F8 is divided into User ROM areaand Boot ROM area as shown in Figure 57.

In addition to the ordinary User ROM area to store the MCU op-eration control program, the flash memory has a Boot ROM areathat is used to store a program to control rewriting in CPU rewriteand standard serial I/O modes. This Boot ROM area has had astandard serial I/O mode control program stored in it whenshipped from the factory. However, the user can write a rewritecontrol program in this area that suits the user’s application sys-tem. This Boot ROM area can be rewritten in only parallel I/Omode.

Table 13 Summary of M37516F8 (flash memory version)

Item

Power source voltage

VPP voltage (For Program/Erase)Flash memory modeErase block division

User ROM areaBoot ROM area

Specifications

Vcc = 2.7– 5.5 V (Note 1)Vcc = 2.7–3.6 V (Note 2)4.5-5.5 V, f(XIN) = 8 MHz

3 modes (Parallel I/O mode, Standard serial I/O mode, CPU rewrite mode)1 block (32 Kbytes)

1 block (4 Kbytes) (Note 3)Byte programBatch erasing

Program/Erase control by software command6 commands100 times

Available in parallel I/O mode and standard serial I/O mode

Program methodErase method

Program/Erase control methodNumber of commands

Number of program/Erase timesROM code protection

Notes1: The power source voltage must be Vcc = 4.5–5.5 V at program and erase operation.

2: The power source voltage can be Vcc = 3.0–3.6 V also at program and erase operation.

3: The Boot ROM area has had a standard serial I/O mode control program stored in it when shipped from the factory. This Boot ROM area can berewritten in only parallel I/O mode.

Rev.1.01 Jul 01, 2003 page 49 of 89

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7516 Group(1) CPU Rewrite ModeIn CPU rewrite mode, the internal flash memory can be operatedon (read, program, or erase) under control of the Central Process-ing Unit (CPU).In CPU rewrite mode, only the User ROM area shown in Figure 57can be rewritten; the Boot ROM area cannot be rewritten. Makesure the program and block erase commands are issued for onlythe User ROM area and each block area.The control program for CPU rewrite mode can be stored in eitherUser ROM or Boot ROM area. In the CPU rewrite mode, becausethe flash memory cannot be read from the CPU, the rewrite con-trol program must be transferred to internal RAM area to beexecuted before it can be executed.Microcomputer Mode and Boot ModeThe control program for CPU rewrite mode must be written intothe User ROM or Boot ROM area in parallel I/O mode beforehand.(If the control program is written into the Boot ROM area, the stan-dard serial I/O mode becomes unusable.)See Figure 57 for details about the Boot ROM area.Normal microcomputer mode is entered when the microcomputeris reset with pulling CNVSS pin low. In this case, the CPU startsoperating using the control program in the User ROM area.When the microcomputer is reset by pulling the P41/INT0 pin high,the CNVss pin high, the CPU starts operating using the controlprogram in the Boot ROM area (program start address is FFFC16,FFFD16 fixation). This mode is called the “Boot” mode.Block AddressBlock addresses refer to the maximum address of each block.These addresses are used in the block erase command. In caseof the M37516F8, it has only one block.Parallel I/O mode 800016 FFFF16 Block 1 : 32 kbyte User ROM area BSEL = 0 F00016 FFFF16 4 kbyte Boot ROM area BSEL = 1 CPU rewrite mode, standard serial I/O mode 800016 Product nameM37516F8 Flash memorystart address800016 FFFF16Block 1 : 32 kbyte User ROM areaF00016 FFFF16 4 kbyte Boot ROM areaUser area / Boot area selection bit = 1User area / Boot area selection bit = 0 Notes 1: The Boot ROM area can be rewritten in only parallel input/output mode. (Access to any other areas is inhibited.)2: To specify a block, use the maximum address in the block.Fig. 57 Block diagram of built-in flash memoryRev.1.01 Jul 01, 2003 page 50 of 89

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7516 GroupOutline Performance (CPU Rewrite Mode)CPU rewrite mode is usable in the single-chip or Boot mode. Theonly User ROM area can be rewritten in CPU rewrite mode.In CPU rewrite mode, the CPU erases, programs and reads the in-ternal flash memory by executing software commands. Thisrewrite control program must be transferred to the RAM before itcan be executed.The MCU enters CPU rewrite mode by applying 5 V ± 0.5 V to theCNVSS pin and setting “1” to the CPU Rewrite Mode Select Bit (bit1 of address 0FFE16). Software commands are accepted once themode is entered.Use software commands to control program and erase operations.Whether a program or erase operation has terminated normally orin error can be verified by reading the status register.Figure 58 shows the flash memory control register.Bit 0 is the RY/BY status flag used exclusively to read the operat-ing status of the flash memory. During programming and eraseoperations, it is “0” (busy). Otherwise, it is “1” (ready).Bit 1 is the CPU Rewrite Mode Select Bit. When this bit is set to“1”, the MCU enters CPU rewrite mode. Software commands areaccepted once the mode is entered. In CPU rewrite mode, theCPU becomes unable to access the internal flash memory directly.Therefore, use the control program in the RAM for write to bit 1. Toset this bit to “1”, it is necessary to write “0” and then write “1” insuccession. The bit can be set to “0” by only writing “0”.Bit 2 is the CPU Rewrite Mode Entry Flag. This flag indicates “1” inCPU rewrite mode, so that reading this flag can check whetherCPU rewrite mode has been entered or not.Bit 3 is the flash memory reset bit used to reset the control circuitof internal flash memory. This bit is used when exiting CPU rewritemode and when flash memory access has failed. When the CPURewrite Mode Select Bit is “1”, setting “1” for this bit resets thecontrol circuit. To set this bit to “1”, it is necessary to write “0” andthen write “1” in succession. To release the reset, it is necessaryto set this bit to “0”.Bit 4 is the User Area/Boot Area Select Bit. When this bit is set to“1”, Boot ROM area is accessed, and CPU rewrite mode in BootROM area is available. In Boot mode, this bit is set to “1” auto-matically. Reprogramming of this bit must be in the RAM.Figure 59 shows a flowchart for setting/releasing CPU rewritemode. b7b0 Flash memory control register (address 0FFE16) (Note 1)FMCRRY/BY status flag0: Busy (being programmed or erased)1: ReadyCPU rewrite mode select bit (Note 2)0: Normal mode (Software commands invalid)1: CPU rewrite mode (Software commands acceptable) CPU rewrite mode entry flag0: Normal mode1: CPU rewrite mode Flash memory reset bit (Note 3)0: Normal operation1: ResetUser ROM area / Boot ROM area select bit (Note 4)0: User ROM area accessed1: Boot ROM area accessedReserved bits (Indefinite at read/ “0” at write) Notes1: The contents of flash memory control register are “XXX00001” just after reset release. In the mask ROM version, this address is reserved area.2: For this bit to be set to “1”, the user needs to write “0” and then “1” to it in succession. If it is not this procedure, this bit will not be set to “1”. Additionally, it is required to ensure that no interrupt will be generated during that interval.Use the control program in the area except the built-in flash memory for write to this bit.3: This bit is valid when the CPU rewrite mode select bit is “1”. Set this bit 3 to “0” subsequently aftersetting bit 3 to “1”.4: Use the control program in the area except the built-in flash memory for write to this bit.Fig. 58 Structure of flash memory control registerRev.1.01 Jul 01, 2003 page 51 of 89

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7516 Group StartSingle-chip mode or Boot mode (Note 1)Set CPU mode register (Note 2) Transfer CPU rewrite mode control program to RAM Setting Jump to control program transferred in RAM (Subsequent operations are executed by control program in this RAM) Set CPU rewrite mode select bit to “1” (by writing “0” and then “1” in succession) Check CPU rewrite mode entry flagUsing software command execute erase, program, or other operation Execute read array command or reset flash memory by setting flash memory reset bit (by writing “1” and then “0” in succession) (Note 3) Write “0” to CPU rewrite mode select bit ReleasedEndNotes1: When starting the MCU in the single-chip mode, supply 4.5 V to 5.5 V to the CNVsspin until checking the CPU rewrite mode entry flag.2: Set bits 6, 7 (main clock division ratio selection bits) at CPU mode register (003B16).3: Before exiting the CPU rewrite mode after completing erase or program operation,always be sure to execute the read array command or reset the flash memory.Fig. 59 CPU rewrite mode set/release flowchartRev.1.01 Jul 01, 2003 page 52 of 89

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7516 Group

Precautions on CPU Rewrite Mode

Described below are the precautions to be observed when rewritingthe flash memory in CPU rewrite mode.

(1) Operation speed

During CPU rewrite mode, set the internal clock frequency 4.0MHz or less using the main clock division ratio selection bits (bit6, 7 at 003B16).

(2) Instructions inhibited against use

The instructions which refer to the internal data of the flashmemory cannot be used during CPU rewrite mode .

(3) Interrupts inhibited against use

The interrupts cannot be used during CPU rewrite mode be-cause they refer to the internal data of the flash memory.

(4) Watchdog timer

In case of the watchdog timer has been running already, the in-ternal reset generated by watchdog timer underflow does nothappen, because of watchdog timer is always clearing duringprogram or erase operation.

(5) Reset

Reset is always valid. In case of CNVSS = H when reset is re-leased, boot mode is active. So the program starts from the ad-dress contained in address FFFC16 and FFFD16 in boot ROMarea.

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7516 GroupSoftware Commands (CPU Rewrite Mode)Table 14 lists the software commands.After setting the CPU Rewrite Mode Select Bit of the flash memorycontrol register to “1”, execute a software command to specify anerase or program operation.Each software command is explained below.qRead Array Command (FF16)The read array mode is entered by writing the command code“FF16” in the first bus cycle. When an address to be read is input inone of the bus cycles that follow, the contents of the specified ad-dress are read out at the data bus (D0 to D7).The read array mode is retained intact until another command iswritten.qRead Status Register Command (7016)The read status register mode is entered by writing the commandcode “7016” in the first bus cycle. The contents of the status regis-ter are read out at the data bus (D0 to D7) by a read in the secondbus cycle.The status register is explained in the next section.qClear Status Register Command (5016)This command is used to clear the bits SR1, SR4, and SR5 of thestatus register after they have been set. These bits indicate thatoperation has ended in an error. To use this command, write thecommand code “5016” in the first bus cycle.qProgram Command (4016)Program operation starts when the command code “4016” is writ-ten in the first bus cycle. Then, if the address and data to programare written in the 2nd bus cycle, program operation (data program-ming and verification) will start.Whether the write operation is completed can be confirmed by_____reading the status register or the RY/BY Status Flag of the flashmemory control register. When the program starts, the read statusregister mode is entered automatically and the contents of the sta-tus register is read at the data bus (D0 to D7). The status registerbit 7 (SR7) is set to “0” at the same time the write operation startsand is returned to “1” upon completion of the write operation. Inthis case, the read status register mode remains active until thenext command is written.____The RY/BY Status Flag is “0” (busy) during write operation and “1”(ready) when the write operation is completed as is the status reg-ister bit 7.At program end, program results can be checked by reading bit 4(SR4) of the status register. Start Write 4016 Write Write addressWrite data Status registerread SR7 = 1 ?orRY/BY = 1 ? YESNO SR4 = 0 ? YESProgram completed(Read array command“FF16” write)NO ProgramerrorFig. 60 Program flowchartTable 14 List of software commands (CPU rewrite mode)Command Read array Read status registerClear status register ProgramErase all blocks Block erase Cycle number121222Mode Write WriteWrite WriteWrite WriteFirst bus cycle DataAddress (D0 to D7) FF16X(Note 1) X7016XXXX Second bus cycle DataModeAddress(D0 to D7) Read WriteWrite WriteX WA(Note 3)X BA(Note 4) SRD(Note 2) WD(Note 3)2016 D0165016401620162016Notes 1: X denotes a given address in the User ROM area .2: SRD = Status Register Data3: WA = Write Address, WD = Write Data4: BA = Block Address to be erased (Input the maximum address of each block.)Rev.1.01 Jul 01, 2003 page 54 of 89

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7516 GroupqErase All Blocks Command (2016/2016)By writing the command code “2016” in the first bus cycle and theconfirmation command code “2016” in the second bus cycle thatfollows, the operation of erase all blocks (erase and erase verify)starts.Whether the erase all blocks command is terminated can be con-____firmed by reading the status register or the RY/BY Status Flag offlash memory control register. When the erase all blocks operationstarts, the read status register mode is entered automatically andthe contents of the status register can be read out at the data bus(D0 to D7). The status register bit 7 (SR7) is set to “0” at the sametime the erase operation starts and is returned to “1” upon comple-tion of the erase operation. In this case, the read status registermode remains active until another command is written.____The RY/BY Status Flag is “0” during erase operation and “1” whenthe erase operation is completed as is the status register bit 7(SR7).After the erase all blocks end, erase results can be checked byreading bit 5 (SRS) of the status register. For details, refer to thesection where the status register is detailed.qBlock Erase Command (2016/D016)By writing the command code “2016” in the first bus cycle and theconfirmation command code “D016” and the blobk address in thesecond bus cycle that follows, the block erase (erase and eraseverify) operation starts for the block address of the flash memoryto be specified.Whether the block erase operation is completed can be confirmed____by reading the status register or the RY/BY Status Flag of flashmemory control register. At the same time the block erase opera-tion starts, the read status register mode is automatically entered,so that the contents of the status register can be read out. Thestatus register bit 7 (SR7) is set to “0” at the same time the blockerase operation starts and is returned to “1” upon completion ofthe block erase operation. In this case, the read status registermode remains active until the read array command (FF16) is writ-ten.____The RY/BY Status Flag is “0” during block erase operation and “1”when the block erase operation is completed as is the status reg-ister bit 7.After the block erase ends, erase results can be checked by read-ing bit 5 (SRS) of the status register. For details, refer to thesection where the status register is detailed. Start Write 2016 Write 2016/D016Block address2016:Erase all blocks commandD016:Block erase command Status registerreadSR7 = 1 ?orRY/BY = 1 ? NO YES NO SR5 = 0 ? YES Erase error Erase completed(Read comand “FF16”write)Fig. 61 Erase flowchartRev.1.01 Jul 01, 2003 page 55 of 89

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7516 Group

Status Register (SRD)

The status register shows the operating status of the flashmemory and whether erase operations and programs ended suc-cessfully or in error. It can be read in the following ways:

(1) By reading an arbitrary address from the User ROM area afterwriting the read status register command (7016)

(2) By reading an arbitrary address from the User ROM area in theperiod from when the program starts or erase operation startsto when the read array command (FF16) is input.Also, the status register can be cleared by writing the clear statusregister command (5016).

After reset, the status register is set to “8016”.

Table 15 shows the status register. Each bit in this register is ex-plained below.

•Sequencer status (SR7)

The sequencer status indicates the operating status of the flashmemory. This bit is set to “0” (busy) during write or erase operationand is set to “1” when these operations ends.

After power-on, the sequencer status is set to “1” (ready).

•Erase status (SR5)

The erase status indicates the operating status of erase operation.If an erase error occurs, it is set to “1”. When the erase status iscleared, it is set to “0”.

•Program status (SR4)

The program status indicates the operating status of write opera-tion. When a write error occurs, it is set to “1”.

The program status is set to “0” when it is cleared.

If “1” is written for any of the SR5 and SR4 bits, the program,erase all blocks, and block erase commands are not accepted.Before executing these commands, execute the clear status regis-ter command (5016) and clear the status register.

Also, if any commands are not correct, both SR5 and SR4 are setto “1”.

Table 15 Definition of each bit in status register (SRD)

SymbolSR7 (bit7)SR6 (bit6)SR5 (bit5)SR4 (bit4)SR3 (bit3)SR2 (bit2)SR1 (bit1)SR0 (bit0)

Status nameSequencer statusReservedErase statusProgram statusReservedReservedReservedReserved

Definition

“1” “0”

Ready-Terminated in errorTerminated in error

----Busy-Terminated normallyTerminated normally

----

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7516 GroupFull Status CheckBy performing full status check, it is possible to know the execu-tion results of erase and program operations. Figure 62 shows afull status check flowchart and the action to be taken when eacherror occurs.Read status register YESSR4 = 1 andSR5 = 1 ? NOCommandsequence error Execute the clear status register command (5016) to clear the status register. Try performing the operation one more time after confirming that the command is entered correctly. Should an erase error occur, the block in error cannot be used. Should a program error occur, the block in error cannot be used. SR5 = 0 ? YESSR4 = 0 ? YES NO Erase error NO Program errorEnd (erase, program)Note: When one of SR5 and SR4 is set to “1”, none of the read array, the program, erase all blocks, and block erase commands is accepted. Execute the clear status register command (5016) before executing these commands. Fig. 62 Full status check flowchart and remedial procedure for errorsRev.1.01 Jul 01, 2003 page 57 of 89

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7516 GroupFunctions To Inhibit Rewriting Flash MemoryVersionTo prevent the contents of internal flash memory from being readout or rewritten easily, this MCU incorporates a ROM code protectfunction for use in parallel I/O mode and an ID code check func-tion for use in standard serial I/O mode.qROM Code Protect Function (in Parallel I/O Mode)The ROM code protect function is the function to inhibit readingout or modifying the contents of internal flash memory by usingthe ROM code protect control (address FFDB16) in parallel I/Omode. Figure 63 shows the ROM code protect control (addressFFDB16). (This address exists in the User ROM area.)If one or both of the pair of ROM Code Protect Bits is set to “0”,the ROM code protect is turned on, so that the contents of internalflash memory are protected against readout and modification. TheROM code protect is implemented in two levels. If level 2 is se-lected, the flash memory is protected even against readout by ashipment inspection LSI tester, etc. When an attempt is made toselect both level 1 and level 2, level 2 is selected by default.If both of the two ROM Code Protect Reset Bits are set to “00”, theROM code protect is turned off, so that the contents of internalflash memory can be read out or modified. Once the ROM codeprotect is turned on, the contents of the ROM Code Protect ResetBits cannot be modified in parallel I/O mode. Use the serial I/O orCPU rewrite mode to rewrite the contents of the ROM Code Pro-tect Reset Bits. b7 b011ROM code protect control register (address FFDB16) (Note 1)ROMCP Reserved bits (“1” at read/write)ROM code protect level 2 set bits (ROMCP2) (Notes 2, 3)b3b20 0: Protect enabled0 1: Protect enabled1 0: Protect enabled1 1: Protect disabledROM code protect reset bits (Note 4)b5b40 0: Protect removed0 1: Protect set bits effective1 0: Protect set bits effective1 1: Protect set bits effectiveROM code protect level 1 set bits (ROMCP1) (Note 2)b7b60 0: Protect enabled0 1: Protect enabled1 0: Protect enabled1 1: Protect disabledNotes1: This area is on the ROM in the mask ROM version.2: When ROM code protect is turned on, the internal flash memory is protectedagainst readout or modification in parallel I/O mode.3: When ROM code protect level 2 is turned on, ROM code readout by a shipmentinspection LSI tester, etc. also is inhibited.4: The ROM code protect reset bits can be used to turn off ROM code protect level 1and ROM code protect level 2. However, since these bits cannot be modified inparallel I/O mode, they need to be rewritten in standard serial I/O mode or CPUrewrite mode.Fig. 63 Structure of ROM code protect controlRev.1.01 Jul 01, 2003 page 58 of 89

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7516 Group

ID Code Check Function (in Standard serialI/O mode)

Use this function in standard serial I/O mode. When the contentsof the flash memory are not blank, the ID code sent from the pro-grammer is compared with the ID code written in the flash memoryto see if they match. If the ID codes do not match, the commandssent from the programmer are not accepted. The ID code consistsof 8-bit data, and its areas are FFD416 to FFDA16. Write a pro-gram which has had the ID code preset at these addresses to theflash memory.

Address FFD416 FFD516 FFD616 FFD716 FFD816FFD916FFDA16FFDB16 ID1ID2ID3 ID4 ID5ID6ID7ROM code protect controlInterrupt vector areaFig. 64 ID code store addresses

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7516 Group

(2) Parallel I/O Mode

Parallel I/O mode is the mode which parallel output and input soft-ware command, address, and data required for the operations(read, program, erase, etc.) to a built-in flash memory. Use the ex-clusive external equipment flash programmer which supports the7516 Group (flash memory version). Refer to each programmermaker’s handling manual for the details of the usage.

User ROM and Boot ROM Areas

In parallel I/O mode, the user ROM and boot ROM areas shown inFigure 57 can be rewritten. Both areas of flash memory can be oper-ated on in the same way.

Program and block erase operations can be performed in the user ROMarea. The user ROM area and its block is shown in Figure 57.

The boot ROM area is 4 Kbytes in size. It is located at addressesF00016 through FFFF16. Make sure program and block erase opera-tions are always performed within this address range. (Access to anylocation outside this address range is prohibited.)

In the Boot ROM area, an erase block operation is applied to onlyone 4 Kbyte block. The boot ROM area has had a standard serial I/Omode control program stored in it when shipped from the Mitsubishifactory. Therefore, using the device in standard serial I/O mode, youdo not need to write to the boot ROM area.

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7516 Group

(3) Standard serial I/O Mode

The standard serial I/O mode inputs and outputs the softwarecommands, addresses and data needed to operate (read, pro-gram, erase, etc.) the internal flash memory. This I/O is clocksynchronized serial. This mode requires the exclusive externalequipment (serial programmer).

The standard serial I/O mode is different from the parallel I/Omode in that the CPU controls flash memory rewrite (uses theCPU rewrite mode), rewrite data input and so forth. The standardserial I/O mode is started by connecting “H” to the P26 (SCLK) pinand “H” to the P41 (INT0) pin and “H” to the CNVSS pin (apply 4.5V to 5.5 V to Vpp from an external source), and releasing the re-set operation. (In the ordinary microcomputer mode, set CNVsspin to “L” level.)

This control program is written in the Boot ROM area when theproduct is shipped from Mitsubishi. Accordingly, make note of thefact that the standard serial I/O mode cannot be used if the BootROM area is rewritten in parallel I/O mode. Figure 65 shows thepin connection for the standard serial I/O mode.

In standard serial I/O mode, serial data I/O uses the four serial I/Opins SCLK, RxD, TxD and SRDY1 (BUSY). The SCLK1 pin is thetransfer clock input pin through which an external transfer clock isinput. The TxD pin is for CMOS output. The SRDY1 (BUSY) pinoutputs “L” level when ready for reception and “H” level when re-ception starts.

Serial data I/O is transferred serially in 8-bit units.

In standard serial I/O mode, only the User ROM area shown inFigure 44 can be rewritten. The Boot ROM area cannot.

In standard serial I/O mode, a 7-byte ID code is used. When thereis data in the flash memory, commands sent from the peripheralunit (programmer) are not accepted unless the ID code matches.

Outline Performance (Standard Serial I/OMode)

In standard serial I/O mode, software commands, addresses anddata are input and output between the MCU and peripheral units(serial programmer, etc.) using 4-wire clock-synchronized serialI/O (serial I/O1).

In reception, software commands, addresses and program dataare synchronized with the rise of the transfer clock that is input tothe SCLK pin, and are then input to the MCU via the RxD pin. Intransmission, the read data and status are synchronized with thefall of the transfer clock, and output from the TxD pin.

The TxD pin is for CMOS output. Transfer is in 8-bit units with LSBfirst.

When busy, such as during transmission, reception, erasing orprogram execution, the SRDY1 (BUSY) pin is “H” level. Accord-ingly, always start the next transfer after the SRDY1 (BUSY) pin is“L” level.

Also, data and status registers in a memory can be read after in-putting software commands. Status, such as the operating state ofthe flash memory or whether a program or erase operation endedsuccessfully or not, can be checked by reading the status register.Here following explains software commands, status registers, etc.

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7516 GroupTable 16 Description of pin function (Standard Serial I/O Mode) Pin VCC,VSS CNVSS RESETXINXOUT AVSSVREF P00 to P07 P10 to P17 P20 to P23 P24 P25 P26P27 P30 to P37P40, P42 to P47 P41 Name Power input CNVSS Reset input Clock input Clock output Analog power supply input Reference voltage input Input port P0 Input port P1 Input port P2 RxD input TxD output SCLK inputBUSY output Input port P3Input port P4 Input port P4I/O DescriptionApply program/erase protection voltage to Vcc pin and 0 V to Vss pin.IIIOConnect to VCC when VCC = 4.5 V to 5.5 V.Connect to Vpp (=4.5 V to 5.5 V) when VCC = 2.7 V to 4.5 V.Reset input pin. While reset is “L” level, a 20 cycle or longer clockmust be input to XIN pin.Connect a ceramic resonator or crystal oscillator between XIN and XOUT pins. To input an externally generated clock, input it to XIN pin and open XOUT pin. Connect AVSS to VSS . Enter the reference voltage for AD from this pin, or open. Input “H” or “L”, or open. Input “H” or “L”, or open. Input “H” or “L”, or open.This pin is for serial data input. This pin is for serial data output. This pin is for serial clock input.This pin is for BUSY signal output. Input “H” or “L”, or open.Input “H” or “L”, or open. Input “H” when RESET is released only.IIIIIOIOIIIRev.1.01 Jul 01, 2003 page 62 of 89

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7516 Group P36/AN6 P37/AN7 P00/SIN2 P01/SOUT2 P02/SCLK2 P03/SRDY2 P04 P05 P06 P07 P10/(LED0) P11/(LED1)VCC 36 35 34 33 32 31 30 29 28 27 26 25 VSS 24 23 2221 20 19181716151413 P35/AN5 P34/AN4 P33/AN3 P32/AN2P31/AN1 P30/AN0 37 38 39 40 414243 4445464748VCC M37516F8HPP12/(LED2) P13/(LED3) P14/(LED4) P15/(LED5) P16/(LED6) P17/(LED7)VSSXOUTXINRESET P20/XCOUTP21/XCIN VREFAVSS P47P46P45✽1 RESETMode setup methodSignal CNVSSP41 SCLKRESET RXDTXD P41 4.5 to 5.5 VVCC ✽ 3VCC ✽ 3 ✽2 VSS VCCNotes 1: Connect oscillator circuit2: Connect to Vcc when Vcc = 4.5 V to 5.5 V.Connect to Vpp (=4.5 V to 5.5 V) when Vcc = 2.7 V to 4.5 V.3: It is necessary to apply Vcc only when reset is released. Fig. 65 Pin connection diagram in standard serial I/O modeRev.1.01 Jul 01, 2003 page 63 of 89

VPPValue BUSY SCLK P27/CNTR0/SRDY1 P26/SCLK P25/SCL2/TXD P24/SDA2/RXD P23/SCL1 P22/SDA1 CNVSS P44/INT3/PWM P43/INT2/SCMP2 P42/INT1 P41/INT0 P40/CNTR19 10 11 1212345678元器件交易网www.cecb2b.com

7516 GroupSoftware Commands (Standard Serial I/OMode)Table 17 lists software commands. In standard serial I/O mode,erase, program and read are controlled by transferring softwareTable 17 Software commands (Standard serial I/O mode)Control command1st bytetransferFF164116A71670165016F516Address(low)Size(low)VersiondataoutputAddress(middle)Size(high)Versiondataoutput2nd byteAddress(middle)Address(middle)D016SRDoutputSRD1output3rd byteAddress(high)Address(high)commands via the RxD pin. Software commands are explainedhere below.4th byteDataoutputDatainput5th byteDataoutputDatainput6th byteDataoutputDatainput.....Dataoutput to259th byteData inputto 259thbyteWhen ID isnot verifiedNotacceptableNotacceptableNotacceptableAcceptableNotacceptable123456Page readPage programErase all blocksRead status registerClear status registerID code checkAddress(high)Check-sumVersiondataoutputID sizeDatainputID1Torequirednumberof timesVersiondataoutputTo ID7AcceptableNotacceptable7Download functionFA168Version data output functionFB16VersiondataoutputVersiondata outputto 9th byteAcceptableNotes1: Shading indicates transfer from the internal flash memory microcomputer to a programmer. All other data is transferred from an external equipment(programmer) to the internal flash memory microcomputer.2: SRD refers to status register data. SRD1 refers to status register 1 data.3: All commands can be accepted when the flash memory is totally blank.4: Address high must be “0016”.Rev.1.01 Jul 01, 2003 page 64 of 89

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7516 GroupqPage Read CommandThis command reads the specified page (256 bytes) in the flashmemory sequentially one byte at a time. Execute the page readcommand as explained here following.(1) Transfer the “FF16” command code with the 1st byte.(2) Transfer addresses A8 to A15 and A16 to A23 (“0016”) with the2nd and 3rd bytes respectively.(3) From the 4th byte onward, data (D0 to D7) for the page (256bytes) specified with addresses A8 to A23 will be output se-quentially from the smallest address first synchronized with thefall of the clock. SCLK FF16RxDA8 toA15 A16 toA23data0data255TxDSRDY1(BUSY)Fig. 66 Timing for page readqRead Status Register CommandThis command reads status information. When the “7016” com-mand code is transferred with the 1st byte, the contents of thestatus register (SRD) with the 2nd byte and the contents of statusregister 1 (SRD1) with the 3rd byte are read. SCLK RxD7016SRDoutputSRD1outputTxDSRDY1(BUSY)Fig. 67 Timing for reading status registerRev.1.01 Jul 01, 2003 page 65 of 89

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7516 GroupqClear Status Register CommandThis command clears the bits (SR4, SR5) which are set when thestatus register operation ends in error. When the “5016” commandcode is sent with the 1st byte, the aforementioned bits arecleared. When the clear status register operation ends, the SRDY1(BUSY) signal changes from “H” to “L” level.SCLKRxD5016TxDSRDY1(BUSY)Fig. 68 Timing for clear status registerqPage Program CommandThis command writes the specified page (256 bytes) in the flashmemory sequentially one byte at a time. Execute the page pro-gram command as explained here following.(1) Transfer the “4116” command code with the 1st byte.(2) Transfer addresses A8 to A15 and A16 to A23 (“0016”) with the2nd and 3rd bytes respectively.(3) From the 4th byte onward, as write data (D0 to D7) for thepage (256 bytes) specified with addresses A8 to A23 is inputsequentially from the smallest address first, that page is auto-matically written.When reception setup for the next 256 bytes ends, the SRDY1(BUSY) signal changes from “H” to “L” level. The result of thepage program can be known by reading the status register. Formore information, see the section on the status register. SCLK 4116A8 toA15 A16 toA23 data255RxDdata0TxDSRDY1(BUSY)Fig. 69 Timing for page programRev.1.01 Jul 01, 2003 page 66 of 89

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7516 GroupqErase All Blocks CommandThis command erases the contents of all blocks. Execute theerase all blocks command as explained here following.(1) Transfer the “A716” command code with the 1st byte.(2) Transfer the verify command code “D016” with the 2nd byte.With the verify command code, the erase operation will startand continue for all blocks in the flash memory.When erase all blocks end, the SRDY1 (BUSY) signal changesfrom “H” to “L” level. The result of the erase operation can beknown by reading the status register. SCLK RxDA716D016TxDSRDY1(BUSY)Fig. 70 Timing for erase all blocksRev.1.01 Jul 01, 2003 page 67 of 89

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7516 GroupqDownload CommandThis command downloads a program to the RAM for execution.Execute the download command as explained here following.(1) Transfer the “FA16” command code with the 1st byte.(2) Transfer the program size with the 2nd and 3rd bytes.(3) Transfer the check sum with the 4th byte. The check sum isadded to all data sent with the 5th byte onward.(4) The program to execute is sent with the 5th byte onward.When all data has been transmitted, if the check sum matches,the downloaded program is executed. The size of the program willvary according to the internal RAM. SCLK Data sizeData sizeCheck (high) (low)sum RxDFA16ProgramdataTxDProgramdataSRDY1(BUSY)Fig. 71 Timing for downloadRev.1.01 Jul 01, 2003 page 68 of 89

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7516 GroupqVersion Information Output CommandThis command outputs the version information of the control pro-gram stored in the Boot ROM area. Execute the versioninformation output command as explained here following.(1) Transfer the “FB16” command code with the 1st byte.(2) The version information will be output from the 2nd byte on-ward. This data is composed of 8 ASCII code characters. SCLK RxDFB16 TxD ‘V’‘E’‘R’‘X’SRDY1(BUSY)Fig. 72 Timing for version information outputRev.1.01 Jul 01, 2003 page 69 of 89

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7516 GroupqID CheckThis command checks the ID code. Execute the boot ID checkcommand as explained here following.(1) Transfer the “F516” command code with the 1st byte.(2) Transfer addresses A0 to A7, A8 to A15 and A16 to A23 (“0016”)of the 1st byte of the ID code with the 2nd, 3rd, and 4th bytesrespectively.(3) Transfer the number of data sets of the ID code with the 5thbyte.(4) Transfer the ID code with the 6th byte onward, starting with the1st byte of the code. SCLK RxDF516D416FF160016 ID size ID1 ID7TxDSRDY1(BUSY)Fig. 73 Timing for ID checkqID CodeWhen the flash memory is not blank, the ID code sent from the se-rial programmer and the ID code written in the flash memory arecompared to see if they match. If the codes do not match, thecommand sent from the serial programmer is not accepted. An IDcode contains 8 bits of data. Area is, from the 1st byte, addressesFFD416 to FFDA16. Write a program into the flash memory, whichalready has the ID code set for these addresses. Address FFD416 FFD516 FFD616 FFD716 FFD816FFD916 FFDA16 FFDB16ID1ID2ID3ID4ID5ID6ID7 ROM code protect control Interrupt vector areaFig. 74 ID code storage addressesRev.1.01 Jul 01, 2003 page 70 of 89

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7516 Group

qStatus Register (SRD)

The status register indicates operating status of the flash memoryand status such as whether an erase operation or a programended successfully or in error. It can be read by writing the readstatus register command (7016). Also, the status register iscleared by writing the clear status register command (5016).

Table 18 lists the definition of each status register bit. After releas-ing the reset, the status register becomes “8016”.

•Sequencer status (SR7)

The sequencer status indicates the operating status of the flashmemory.

After power-on and recover from deep power down mode, the se-quencer status is set to “1” (ready).

This status bit is set to “0” (busy) during write or erase operationand is set to “1” upon completion of these operations.

•Erase status (SR5)

The erase status indicates the operating status of erase operation.If an erase error occurs, it is set to “1”. When the erase status iscleared, it is set to “0”.

•Program status (SR4)

The program status indicates the operating status of write opera-tion. If a program error occurs, it is set to “1”. When the programstatus is cleared, it is set to “0”.

Table 18 Definition of each bit of status register (SRD)

SRD0 bitsSR7 (bit7)SR6 (bit6)SR5 (bit5)SR4 (bit4)SR3 (bit3)SR2 (bit2)SR1 (bit1)SR0 (bit0)

Status nameSequencer statusReservedErase statusProgram statusReservedReservedReservedReserved

Definition

“1”

Ready-Terminated in errorTerminated in error

----

“0”

Busy

-Terminated normallyTerminated normally

----

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7516 Group

qStatus Register 1 (SRD1)

The status register 1 indicates the status of serial communica-tions, results from ID checks and results from check sumcomparisons. It can be read after the status register (SRD) by writ-ing the read status register command (7016). Also, status register1 is cleared by writing the clear status register command (5016).Table 19 lists the definition of each status register 1 bit. This regis-ter becomes “0016” when power is turned on and the flag status ismaintained even after the reset.

•Boot update completed bit (SR15)

This flag indicates whether the control program was downloadedto the RAM or not, using the download function.

•Check sum consistency bit (SR12)

This flag indicates whether the check sum matches or not when aprogram, is downloaded for execution using the download func-tion.

•ID check completed bits (SR11 and SR10)

These flags indicate the result of ID checks. Some commandscannot be accepted without an ID code check.

•Data reception time out (SR9)

This flag indicates when a time out error is generated during datareception. If this flag is attached during data reception, the re-ceived data is discarded and the MCU returns to the commandwait state.

Table 19 Definition of each bit of status register 1 (SRD1)

SRD1 bitsSR15 (bit7)SR14 (bit6)SR13 (bit5)SR12 (bit4)SR11 (bit3)SR10 (bit2)

Status name

Boot update completed bitReserved

Reserved

Checksum match bitID check completed bits

Definition

“1”

Update completed

--Match00011011

“0”Not Update

--Mismatch

Not verified

Verification mismatchReservedVerified

Normal operation

-

SR9 (bit1)SR8 (bit0)Data reception time outReservedTime out

-

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7516 GroupFull Status CheckResults from executed erase and program operations can beknown by running a full status check. Figure 75 shows a flowchartof the full status check and explains how to remedy errors whichoccur.Read status register YESSR4 = 1 andSR5 = 1 ?NOCommandsequence error Execute the clear status register command (5016) to clear the status register. Try performing the operation one more time after confirming that the command is entered correctly. Should an erase error occur, the block in error cannot be used. Should a program error occur, the block in error cannot be used. SR5 = 0 ? YESSR4 = 0 ? YES NO Erase error NOProgram errorEnd (Erase, program)Note: When one of SR5 to SR4 is set to “1” , none of the program, erase all blocks commands is accepted. Execute the clear status register command (5016) before executing these commands. Fig. 75 Full status check flowchart and remedial procedure for errorsRev.1.01 Jul 01, 2003 page 73 of 89

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7516 GroupExample Circuit Application for StandardSerial I/O ModeFigure 76 shows a circuit application for the standard serial I/Omode. Control pins will vary according to a programmer, thereforesee a programmer manual for more information. P41 Clock input BUSY output Data input Data outputSCLKSRDY1 (BUSY)RXDTXD M37516F8 VPP power source inputCNVssNotes 1: Control pins and external circuitry will vary according to peripheral unit. For more information, see the peripheral unit manual.2: In this example, the Vpp power supply is supplied from an external source (writer). To use the user’s power source, connect to 4.5 V to 5.5 V.3: It is necessary to apply Vcc to SCLK pin only when reset is released.Fig. 76 Example circuit application for standard serial I/O modeRev.1.01 Jul 01, 2003 page 74 of 89

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7516 Group

Flash memory Electrical characteristics

Table 20 Absolute maximum ratingsSymbolVCCVIVIVIVIVOVOPdToprTstg

Parameter

Power source voltage

Input voltageP00–P07, P10–P17, P20, P21,

P24–P27, P30–P37, P40–P47,VREF

Input voltageP22, P23Input voltageRESET, XINInput voltageCNVSS

Output voltageP00–P07, P10–P17, P20, P21,

P24–P27, P30–P37, P40–P47,XOUT

Output voltage P22, P23Power dissipation

Operating temperatureStorage temperature

Conditions

Ratings–0.3 to 6.5–0.3 to VCC +0.3

All voltages are based on VSS.Output transistors are cut off.

–0.3 to 5.8–0.3 to VCC +0.3–0.3 to 6.5–0.3 to VCC +0.3–0.3 to 5.8

30025±5–40 to 125

UnitVVVVVVVmW°C°C

Ta = 25 °C

Table 21 Flash memory mode Electrical characteristics(Ta = 25 oC, VCC = 4.5 to 5.5V unless otherwise noted)

Limits

SymbolIPP1IPP2IPP3VPPVCC

Parameter

VPP power source current (read)VPP power source current (program)VPP power source current (erase)VPP power source voltageVCC power source voltage

VPP = VCCVPP = VCCVPP = VCC

4.5

Microcomputer mode operation atVCC = 2.7 to 5.5V

Microcomputer mode operation atVCC = 2.7 to 3.6V

4.53.0

Conditions

Min.

Typ.

Max.10060305.55.53.6

UnitµAmAmAVVV

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7516 Group

NOTES ON PROGRAMMINGProcessor Status Register

The contents of the processor status register (PS) after a reset areundefined, except for the interrupt disable flag (I) which is “1.” Af-ter a reset, initialize flags which affect program execution. Inparticular, it is essential to initialize the index X mode (T) and thedecimal mode (D) flags because of their effect on calculations.

A-D Converter

The comparator uses capacitive coupling amplifier whose chargewill be lost if the clock frequency is too low.

Therefore, make sure that f(XIN) in the middle/high-speed mode isat least on 500 kHz during an A-D conversion.

Do not execute the STP instruction or the WIT instruction duringan A-D conversion.

Interrupts

The contents of the interrupt request bits do not change immedi-ately after they have been written. After writing to an interruptrequest register, execute at least one instruction before perform-ing a BBC or BBS instruction.

Instruction Execution Time

The instruction execution time is obtained by multiplying the fre-quency of the internal clock φ by the number of cycles needed toexecute an instruction.

The number of cycles required to execute an instruction is shownin the list of machine instructions.

The frequency of the internal clock φ is half of the XIN frequency inhigh-speed mode.

Decimal Calculations

•To calculate in decimal notation, set the decimal mode flag (D)to “1”, then execute an ADC or SBC instruction. After executingan ADC or SBC instruction, execute at least one instruction be-fore executing a SEC, CLC, or CLD instruction.

•In decimal mode, the values of the negative (N), overflow (V),and zero (Z) flags are invalid.

NOTES ON USAGE

Handling of Source Pins

In order to avoid a latch-up occurrence, connect a capacitor suit-able for high frequencies as bypass capacitor between powersource pin (VCC pin) and GND pin (VSS pin) and between powersource pin (VCC pin) and analog power source input pin (AVSSpin). Besides, connect the capacitor to as close as possible. Forbypass capacitor which should not be located too far from the pinsto be connected, a ceramic capacitor of 0.01 µF–0.1µF is recom-mended.

Timers

If a value n (between 0 and 255) is written to a timer latch, the fre-quency division ratio is 1/(n+1).

Multiplication and Division Instructions

•The index X mode (T) and the decimal mode (D) flags do not af-fect the MUL and DIV instruction.

•The execution of these instructions does not change the con-tents of the processor status register.

EPROM Version/One Time PROM Version/Flash Memory Version

The CNVss pin is connected to the internal memory circuit blockby a low-ohmic resistance, since it has the multiplexed function tobe a programmable power source pin (VPP pin) as well.

To improve the noise reduction, connect a track between CNVsspin and Vss pin or Vcc pin with 1 to 10 kΩ resistance.

The mask ROM version track of CNVss pin has no operational in-terference even if it is connected to Vss pin or Vcc pin via aresistor.

Ports

The contents of the port direction registers cannot be read. Thefollowing cannot be used:

•The data transfer instruction (LDA, etc.)

•The operation instruction when the index X mode flag (T) is “1”•The addressing mode which uses the value of a direction regis-ter as an index

•The bit-test instruction (BBC or BBS, etc.) to a direction register•The read-modify-write instructions (ROR, CLB, or SEB, etc.) toa direction register.

Use instructions such as LDM and STA, etc., to set the port direc-tion registers.

Electric Characteristic Differences AmongMask ROM, Flash Memory, and One TimePROM Version MCUs

There are differences in electric characteristics, operation margin,noise immunity, and noise radiation among mask ROM, flashmemory, and One Time PROM version MCUs due to the differ-ences in the manufacturing processes.

When manufacturing an application system with the flash memory,One Time PROM version and then switching to use of the maskROM version, perform sufficient evaluations for the commercialsamples of the mask ROM version.

Serial I/O

In serial I/O1 (clock synchronous mode), if the receive side is us-ing an external clock and it is to output the SRDY1 signal, set thetransmit enable bit, the receive enable bit, and the SRDY1 outputenable bit to “1.”

Serial I/O1 continues to output the final bit from the TXD pin aftertransmission is completed.

SOUT2 pin for serial I/O2 goes to high impedance after transmis-sion is completed.

When an external clock is used as synchronous clock in serialI/O1 or serial I/O2, write transmission data to the transmit bufferregister or serial I/O2 register while the transfer clock is “H.”

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7516 GroupDATA REQUIRED FOR MASK ORDERSThe following are necessary when ordering a mask ROM produc-tion:1. Mask ROM Order Confirmation Form✽2. Mark Specification Form✽3. Data to be written to ROM, in EPROM form (three identical cop-ies) or one floppy disk.ROM PROGRAMMING METHODThe built-in PROM of the blank One Time PROM version and buit-in EPROM version can be read or programmed with ageneral-purpose PROM programmer using a special programmingadapter. Set the address of PROM programmer in the user ROMarea.Table 22 Programming adapterPackageName of Programming Adapter48P6Q-APCA7419DATA REQUIRED FOR One Time PROMPROGRAMMING ORDERSThe following are necessary when ordering a PROM programmingservice:1. ROM Programming Confirmation Form✽2. Mark Specification Form✽ (only special mark with customer’strade mark logo)3. Data to be programmed to PROM, in EPROM form (three iden-tical copies) or one floppy disk.✽For the mask ROM confirmation and the mark specifications, re-fer to the “Renesas Technology Corp.” Homepage (http://www.renesas.com/en/rom).The PROM of the blank One Time PROM version is not tested orscreened in the assembly process and following processes. To en-sure proper operation after programming, the procedure shown inFigure 77 is recommended to verify programming. Programming with PROMprogrammerScreening (Caution)(150 °C for 40 hours)Verification withPROM programmer Functional check intarget deviceCaution : The screening temperature is far higherthan the storage temperature. Neverexpose to 150 °C exceeding 100 hours.Fig. 77 Programming and testing of One Time PROM versionRev.1.01 Jul 01, 2003 page 77 of 89

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7516 Group

ELECTRICAL CHARACTERISTICS

Table 23 Absolute maximum ratings (Executing flash memory mode, flash memory electrical characteristics is applied.)SymbolVCCVIVIVIVI

ParameterConditions

Power source voltage

Input voltageP00–P07, P10–P17, P20, P21,

P24–P27, P30–P37, P40–P47,VREF

Input voltageP22, P23Input voltageRESET, XIN

Input voltageM37516M4, M37516M6, M37516M8All voltages are based on VSS.

Output transistors are cut off.

M37516E6M37516F8

Output voltageP00–P07, P10–P17, P20, P21,

P24–P27, P30–P37, P40–P47,XOUT

Output voltage P22, P23Power dissipationTa = 25 °COperating temperatureStorage temperature

Ratings–0.3 to 6.5–0.3 to VCC +0.3–0.3 to 5.8–0.3 to VCC +0.3–0.3 to VCC +0.3–0.3 to 13–0.3 to 6.5–0.3 to VCC +0.3–0.3 to 5.8

300–20 to 85–40 to 125

UnitVVVVV

VOVOPdToprTstg

VVmW°C°C

Table 24 Recommended operating conditions (1)

(VCC = 2.7 to 5.5 V, Ta = –20 to 85 °C, unless otherwise noted)SymbolVCCVSSVREFAVSSVIAVIHVIHVIHVIHVIHVIHVILVILVILVILVILΣIOH(peak)ΣIOH(peak)ΣIOL(peak)ΣIOL(peak)ΣIOL(peak)ΣIOH(avg)ΣIOH(avg)ΣIOL(avg)ΣIOL(avg)ΣIOL(avg)

Parameter

Power source voltage (At 8 MHz)Power source voltage (At 4 MHz)Power source voltage

A-D convert reference voltageAnalog power source voltageAnalog input voltageAN0–AN7“H” input voltageP00–P07, P10–P17, P20–P27, P30–P37, P40–P47“H” input voltage (when I2C-BUS input level is selected)

SDA1, SCL1

“H” input voltage (when I2C-BUS input level is selected)

SDA2, SCL2

“H” input voltage (when SMBUS input level is selected)

SDA1, SCL1

“H” input voltage (when SMBUS input level is selected)

SDA2, SCL2

“H” input voltageRESET, XIN, CNVSS“L” input voltageP00–P07, P10–P17, P20–P27, P30–P37, P40–P47“L” input voltage (when I2C-BUS input level is selected)SDA1, SDA2, SCL1, SCL2“L” input voltage (when SMBUS input level is selected)

SDA1, SDA2, SCL1, SCL2

“L” input voltageRESET, CNVSS“L” input voltageXIN“H” total peak output current“H” total peak output current“L” total peak output current“L” total peak output current“L” total peak output current“H” total average output current“H” total average output current“L” total average output current“L” total average output current“L” total average output current

P00–P07, P10–P17, P30–P37 (Note)P20, P21, P24–P27, P40–P47 (Note)P00–P07, P30–P37 (Note)P10–P17 (Note)

P20–P27,P40–P47 (Note)P00–P07, P10–P17, P30–P37 (Note)P20, P21, P24–P27, P40–P47 (Note)P00–P07, P30–P37 (Note)P10–P17 (Note)

P20–P27,P40–P47 (Note)Min.4.02.72.0

0

AVSS0.8VCC0.7VCC0.7VCC1.41.40.8VCC

00000

VCCVCC5.8VCC5.8VCCVCC0.2VCC0.3VCC0.60.2VCC0.16VCC–80–80 80 120 80–40–40 40 60 40

LimitsTyp.5.05.0 0

Max.5.55.5VCC

UnitVVVVVVVVVVVVVVVVmAmAmAmAmAmAmAmAmAmA

Note :The total output current is the sum of all the currents flowing through all the applicable ports. The total average current is an average value measured

over 100 ms. The total peak current is the peak value of all the currents.

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7516 Group

Table 25 Recommended operating conditions (2)

(VCC = 2.7 to 5.5 V, Ta = –20 to 85 °C, unless otherwise noted)SymbolIOH(peak)IOL(peak)IOL(peak)IOH(avg)IOL(avg)IOL(avg)f(XIN)f(XIN)

“H” peak output current

Parameter

P00–P07, P10–P17, P20, P21, P24–P27, P30–P37,P40–P47 (Note 1)

“L” peak output currentP00–P07, P20–P27, P30–P37, P40–P47 (Note 1)“L” peak output currentP10–P17 (Note 1)“H” average output currentP00–P07, P10–P17, P20, P21, P24–P27, P30–P37,

P40–P47 (Note 2)

“L” average output current P00–P07, P20–P27, P30–P37, P40–P47 (Note 2)“L” peak output currentP10–P17 (Note 2)

Internal clock oscillation frequency (VCC = 4.0 to 5.5V) (Note 3)Internal clock oscillation frequency (VCC = 2.7 to 5.5V) (Note 3)

Min.

LimitsTyp.

Max.–101020–551584

UnitmAmAmAmAmAmAMHzMHz

Notes1:The peak output current is the peak current flowing in each port.

2: The average output current IOL(avg), IOH(avg) are average value measured over 100 ms.3: When the oscillation frequency has a duty cycle of 50%.

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7516 Group

Table 26 Electrical characteristics

(VCC = 2.7 to 5.5 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted)

Limits

Symbol

Parameter

“H” output voltage

P00–P07, P10–P17, P20, P21,P24–P27, P30–P37, P40–P47(Note)

“L” output voltage

P00–P07, P20–P27, P30–P37,P40–P47“L” output voltageP10–P17

Test conditionsIOH = –10 mAVCC = 4.0–5.5 VIOH = –1.0 mAVCC = 2.7–5.5 VIOL = 10 mAVCC = 4.0–5.5 VIOL = 1.0 mAVCC = 2.7–5.5 VIOL = 20 mAVCC = 4.0–5.5 VIOL = 10 mAVCC = 2.7–5.5 V

Min.VCC–2.0VCC–1.0

2.01.02.01.0

0.40.50.5

VI = VCCVI = VCCVI = VCCVI = VSS

VI = VSSVI = VSS

When clock stopped

5.05.0

4

–5.0–5.0

–4

2.0

5.5

Typ.

Max.

UnitVVVVVVVVVµAµAµAµAµAµAV

VOH

VOL

VOL

VT+–VT–VT+–VT–VT+–VT–IIHIIHIIHIILIILIILVRAM

Hysteresis

CNTR0, CNTR1, INT0–INT3Hysteresis

RxD, SCLK, SCIN2, SCLK2HysteresisRESET“H” input current

P00–P07, P10–P17, P20, P21,P24–P27, P30–P37, P40–P47

“H” input currentRESET, CNVSS“H” input currentXIN“L” input current

P00–P07, P10–P17, P20–P27P30–P37, P40–P47

“L” input currentRESET,CNVSS“L” input currentXINRAM hold voltage

Note: P25 is measured when the P25/TXD P-channel output disable bit of the UART control register (bit 4 of address 001B16) is “0”.

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7516 Group

Table 27 Electrical characteristics

(VCC = 2.7 to 5.5 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted)Symbol

Parameter

Test conditions

High-speed modef(XIN) = 8 MHz

f(XCIN) = 32.768 kHzOutput transistors “off”High-speed mode

f(XIN) = 8 MHz (in WIT state)f(XCIN) = 32.768 kHzOutput transistors “off”Low-speed mode

Except M37516F8HPf(XIN) = stopped

f(XCIN) = 32.768 kHz

M37516F8HPOutput transistors “off”

Low-speed mode

Except M37516F8HP

f(XIN) = stopped

f(XCIN) = 32.768 kHz (in WIT state)

M37516F8HPOutput transistors “off”

Low-speed mode (VCC = 3 V)Except M37516F8HPf(XIN) = stopped

f(XCIN) = 32.768 kHzM37516F8HPOutput transistors “off”

Low-speed mode (VCC = 3 V)Except M37516F8HPf(XIN) = stopped

f(XCIN) = 32.768 kHz (in WIT state)M37516F8HPOutput transistors “off”Middle-speed modef(XIN) = 8 MHzf(XCIN) = stopped

Output transistors “off”Middle-speed mode

f(XIN) = 8 MHz (in WIT state)f(XCIN) = stopped

Output transistors “off”

Increment when A-D conversion isexecuted

f(XIN) = 8 MHzAll oscillation stopped(in STP state)

Output transistors “off”

Ta = 25 °CTa = 85 °C

Limits

Min.

Typ.6.8

Max.13

Unit

mA

1.6602502070201505.020

10.05540

mAµAµAµAµAµAµAµAµA

200

ICC

Power sourcecurrent

4.07.0mA

1.5

mA

8000.1

1.010

µAµAµA

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7516 Group

Table 28 A-D converter characteristics

(VCC = 2.7 to 5.5 V, VSS = AVSS = 0 V, Ta = –20 to 85 °C, f(XIN) = 8 MHz, f(XCIN) = 32 kHz, unless otherwise noted)

Symbol––tCONV

Parameter

Resolution

Absolute accuracy (excluding quantization error)Conversion time

Test conditions

Limits

Min.

Typ.

Max.10±4 61

UnitbitLSBtc(φ)µskΩµAµAµA

High-speed mode,middle-speed modeLow-speed mode50

RLADDERIVREFII(AD)

Ladder resistor

Reference power source input currentA-D port input current

VREF “on”VREF = 5.0 VVREF “off”

40351500.5

2005.05.0

Rev.1.01 Jul 01, 2003 page 82 of 89

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7516 Group

TIMING REQUIREMENTS

Table 29 Timing requirements (1)

(VCC = 4.0 to 5.5 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted)

SymboltW(RESET)tC(XIN)tWH(XIN)tWL(XIN)tC(CNTR)tWH(CNTR)tWL(CNTR)tWH(INT)tWL(INT)tC(SCLK1)tWH(SCLK1)tWL(SCLK1)tsu(RxD-SCLK1)th(SCLK1-RxD)tC(SCLK2)tWH(SCLK2)tWL(SCLK2)tsu(SIN2-SCLK2)th(SCLK2-SIN2)

Parameter

Reset input “L” pulse widthExternal clock input cycle time

External clock input “H” pulse widthExternal clock input “L” pulse widthCNTR0, CNTR1 input cycle time

CNTR0, CNTR1 input “H” pulse widthCNTR0, CNTR1 input “L” pulse widthINT0 to INT3 input “H” pulse widthINT0 to INT3 input “L” pulse width

Serial I/O1 clock input cycle time (Note)

Serial I/O1 clock input “H” pulse width (Note)Serial I/O1 clock input “L” pulse width (Note)Serial I/O1 clock input set up timeSerial I/O1 clock input hold timeSerial I/O2 clock input cycle time

Serial I/O2 clock input “H” pulse widthSerial I/O2 clock input “L” pulse widthSerial I/O2 clock input set up timeSerial I/O2 clock input hold time

Limits

Min.201255050200808080808003703702201001000400400200200

Typ.

Max.

Unit XIN cycles

nsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsns

Note :When f(XIN) = 8 MHz and bit 6 of address 001A16 is “1” (clock synchronous).

Divide this value by four when f(XIN) = 8 MHz and bit 6 of address 001A16 is “0” (UART).

Table 30 Timing requirements (2)

(VCC = 2.7 to 5.5 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted)

SymboltW(RESET)tC(XIN)tWH(XIN)tWL(XIN)tC(CNTR)tWH(CNTR)tWL(CNTR)tWH(INT)tWL(INT)tC(SCLK1)tWH(SCLK1)tWL(SCLK1)tsu(RxD-SCLK1)th(SCLK1-RxD)tC(SCLK2)tWH(SCLK2)tWL(SCLK2)tsu(SIN2-SCLK2)th(SCLK2-SIN2)

Parameter

Reset input “L” pulse widthExternal clock input cycle time

External clock input “H” pulse widthExternal clock input “L” pulse widthCNTR0, CNTR1 input cycle time

CNTR0, CNTR1 input “H” pulse widthCNTR0, CNTR1 input “L” pulse widthINT0 to INT3 input “H” pulse widthINT0 to INT3 input “L” pulse width

Serial I/O1 clock input cycle time (Note)

Serial I/O1 clock input “H” pulse width (Note)Serial I/O1 clock input “L” pulse width (Note)Serial I/O1 clock input set up timeSerial I/O1 clock input hold timeSerial I/O2 clock input cycle time

Serial I/O2 clock input “H” pulse widthSerial I/O2 clock input “L” pulse widthSerial I/O2 clock input set up timeSerial I/O2 clock input hold time

Limits

Min.2025010010050023023023023020009509504002002000950950400300

Typ.

Max.

UnitXIN cycles

nsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsns

Note :When f(XIN) = 4 MHz and bit 6 of address 001A16 is “1” (clock synchronous).

Divide this value by four when f(XIN) = 8 MHz and bit 6 of address 001A16 is “0” (UART).

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7516 Group

Table 31 Switching characteristics 1

(VCC = 4.0 to 5.5 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted)

SymboltWH (SCLK1)tWL (SCLK1)td (SCLK1-TXD)tv (SCLK1-TXD)tr (SCLK1)tf (SCLK1)tWH (SCLK2)tWL (SCLK2)

td (SCLK2-SOUT2)tv (SCLK2-SOUT2)tf (SCLK2)tr (CMOS)tf (CMOS)

Parameter

Serial I/O1 clock output “H” pulse widthSerial I/O1 clock output “L” pulse widthSerial I/O1 output delay time (Note 1)Serial I/O1 output valid time (Note 1)Serial I/O1 clock output rising timeSerial I/O1 clock output falling timeSerial I/O2 clock output “H” pulse widthSerial I/O2 clock output “L” pulse widthSerial I/O2 output delay time (Note 2)Serial I/O2 output valid time (Note 2)Serial I/O2 clock output falling timeCMOS output rising time (Note 3)CMOS output falling time (Note 3)

Test conditionsLimits

Min.

tC(SCLK1)/2–30tC(SCLK1)/2–30

–30

Fig. 793030

tC(SCLK2)/2–160tC(SCLK2)/2–160

200

0

1010

303030

Typ.

Max.

Unitnsnsnsnsnsnsnsnsnsnsnsnsns

140

Notes1:For tWH(SCLK1), tWL(SCLK1), when the P25/TXD P-channel output disable bit of the UART control register (bit 4 of address 001B16) is “0”.

2:When the P01/SOUT2 and P02/SCLK2 P-channel output disable bit of the Serial I/O2 control register (bit 7 of address 001516) is “0”.3:The XOUT pin is excluded.

Table 32 Switching characteristics 2

(VCC = 2.7 to 5.5 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted)

SymboltWH (SCLK1)tWL (SCLK1)td (SCLK1-TXD)tv (SCLK1-TXD)tr (SCLK1)tf (SCLK1)tWH (SCLK2)tWL (SCLK2)

td (SCLK2-SOUT2)tv (SCLK2-SOUT2)tf (SCLK2)tr (CMOS)tf (CMOS)

Parameter

Serial I/O1 clock output “H” pulse widthSerial I/O1 clock output “L” pulse widthSerial I/O1 output delay time (Note 1)Serial I/O1 output valid time (Note 1)Serial I/O1 clock output rising timeSerial I/O1 clock output falling timeSerial I/O2 clock output “H” pulse widthSerial I/O2 clock output “L” pulse widthSerial I/O2 output delay time (Note 2)Serial I/O2 output valid time (Note 2)Serial I/O2 clock output falling timeCMOS output rising time (Note 3)CMOS output falling time (Note 3)

Test conditionsLimits

Min.

tC(SCLK1)/2–50tC(SCLK1)/2–50

–30

Fig. 795050

tC(SCLK2)/2–240tC(SCLK2)/2–240

400

0

2020

505050

Typ.

Max.

Unitnsnsnsnsnsnsnsnsnsnsnsnsns

350

Notes1:For tWH(SCLK1), tWL(SCLK1), when the P25/TXD P-channel output disable bit of the UART control register (bit 4 of address 001B16) is “0”.

2:When the P01/SOUT2 and P02/SCLK2 P-channel output disable bit of the Serial I/O2 control register (bit 7 of address 001516) is “0”.3:The XOUT pin is excluded.

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7516 GroupMULTI-MASTER I2C-BUS BUS LINE CHARACTERISTICSTable 33 Multi-master I2C-BUS bus line characteristicsSymboltBUFtHD;STAtLOWtRtHD;DATtHIGHtFtSU;DATtSU;STAtSU;STOBus free timeHold time for START conditionHold time for SCL clock = “0”Rising time of both SCL and SDA signalsData hold timeHold time for SCL clock = “1”Falling time of both SCL and SDA signalsData setup timeSetup time for repeated START conditionSetup time for STOP condition2504.74.004.0300ParameterStandard clock modeHigh-speed clock modeMin.4.74.04.71000Max.Min.1.30.61.320+0.1Cb00.620+0.1Cb1000.60.63003000.9Max.UnitµsµsµsnsµsµsnsnsµsµsNote:Cb = total capacitance of 1 bus lineSDAtBUFtLOWtRtFSrPtHD:STAtsu:STOSCLPStHD:STAtHD:DATtHIGHtsu:DATtsu:STAS: START conditionSr: RESTART conditionP: STOP conditionFig. 78 Timing diagram of multi-master I2C-BUSRev.1.01 Jul 01, 2003 page 85 of 89

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7516 Group1 kΩMeasurement output pin100pFMeasurement output pin100 pFCMOS outputN-channnel open-drainFig. 79 Circuit for measuring output switching characteris-tics (1)Fig. 80 Circuit for measuring output switching characteris-tics (2)Rev.1.01 Jul 01, 2003 page 86 of 89

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7516 GrouptC(CNTR)CNTR0CNTR1tWH(CNTR)0.8VCC0.2VCCtWL(CNTR)tWH(INT)tWL(INT)0.2VCCINT0 to INT30.8VCCtW(RESET)RESET0.2VCC0.8VCCtC(XIN)tWH(XIN)tWL(XIN)0.2VCC0.8VCCXINSCLK1SCLK2tftC(SCLK1), tC(SCLK2) tWL(SCLK1), tWL(SCLK2)tWH(SCLK1), tWH(SCLK2)tr0.2VCCtsu(RxD-SCLK1),tsu(SIN2-SCLK2)0.8VCCth(SCLK1-RxD), th(SCLK2-SIN2)RXDSIN2TXDSOUT2Fig. 81 Timing diagram0.8VCC0.2VCCtd(SCLK1-TXD), td(SCLK2-SOUT2)tv(SCLK1-TXD),tv(SCLK2-SOUT2)Rev.1.01 Jul 01, 2003 page 87 of 89

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7516 GroupPACKAGE OUTLINE48P6Q-AEIAJ Package CodeLQFP48-P-77-0.50MMPJEDEC Code–Weight(g)–Lead MaterialCu AlloyPlastic 48pin 7✕7mm body LQFPMDeHDD4837136b2I2Recommended Mount PadSymbolAA1A2bcDEeHDHELL1LpA312251324AFeL1ybLDetail FLpxyb2I2MDMExMDimension in MillimetersMinNomMax1.7––0.10.201.4––0.170.220.270.1050.1250.1756.97.07.16.97.07.10.5––8.89.09.28.89.09.20.350.50.651.0––0.450.60.75–0.25–––0.080.1––0°8°–0.225––1.0––7.4––––7.4HEEA2A1Rev.1.01 Jul 01, 2003 page 88 of 89

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Sales Strategic Planning Div. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, JapanKeep safety first in your circuit designs!1. Renesas Technology Corporation puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage. Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of nonflammable material or (iii) prevention against any malfunction or mishap.Notes regarding these materials1. These materials are intended as a reference to assist our customers in the selection of the Renesas Technology Corporation product best suited to the customer’s application; they do not convey any license under any intellectual property rights, or any other rights, belonging to Renesas Technology Corporation or a third party.2. Renesas Technology Corporation assumes no responsibility for any damage, or infringement of any third-party’s rights, originating in the use of any product data, diagrams, charts, programs, algorithms, or circuit application examples contained in these materials.3. All information contained in these materials, including product data, diagrams, charts, programs and algorithms represents information on products at the time of publication of these materials, and are subject to change by Renesas Technology Corporation without notice due to product improvements or other reasons. It is therefore recommended that customers contact Renesas Technology Corporation or an authorized Renesas Technology Corporation product distributor for the latest product information before purchasing a product listed herein. The information described here may contain technical inaccuracies or typographical errors. Renesas Technology Corporation assumes no responsibility for any damage, liability, or other loss rising from these inaccuracies or errors. Please also pay attention to information published by Renesas Technology Corporation by various means, including the Renesas Technology Corporation Semiconductor home page (http://www.renesas.com).4. When using any or all of the information contained in these materials, including product data, diagrams, charts, programs, and algorithms, please be sure to evaluate all information as a total system before making a final decision on the applicability of the information and products. Renesas Technology Corporation assumes no responsibility for any damage, liability or other loss resulting from the information contained herein.5. Renesas Technology Corporation semiconductors are not designed or manufactured for use in a device or system that is used under circumstances in which human life is potentially at stake. Please contact Renesas Technology Corporation or an authorized Renesas Technology Corporation product distributor when considering the use of a product contained herein for any specific purposes, such as apparatus or systems for transportation, vehicular, medical, aerospace, nuclear, or undersea repeater use.6. The prior written approval of Renesas Technology Corporation is necessary to reprint or reproduce in whole or in part these materials.7. If these products or technologies are subject to the Japanese export control restrictions, they must be exported under a license from the Japanese government and cannot be imported into a country other than the approved destination. Any diversion or reexport contrary to the export control laws and regulations of Japan and/or the country of destination is prohibited.8. Please contact Renesas Technology Corporation for further details on these materials or the products contained therein.http://www.renesas.com© 2002, 2003. Renesas Technology Corp., All rights reserved. Printed in Japan. 元器件交易网www.cecb2b.com

REVISION HISTORY

Rev.

Date

Page

0.1Feb. 03, 2000 –1.0Sep. 05, 20021

12345–67–9111517–871.01Jul. 01, 20034

80

First edition issued

7516 Group Data Sheet

Description

Summary

“qMemory size” of “FEATURES” is revised.

“qPower dissipation” of “FEATURES” is revised.Figure 2 is partly revised.Table 1 is partly revised.Figure 3 is added.

Clause of “GROUP EXPANSION” is added.

Clause of “CENTRAL PROCESSING UNIT (CPU)” is partly added.Figure 8 is partly revised.Figure 11 is partly revised.Pages 17–87 are added.Figure 3 is partly revised.Table 26 is partly revised.