3.0/3.3V I2C Combination Serial RTC, NVRAM
Supervisor and Microprocessor Supervisor
KEY FEATURES
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M41ST85W
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AUTOMATIC BATTERY SWITCHOVER and WRITE PROTECT FOR:–Internal Serial RTC and
–External low power SRAM (LPSRAM)400kHz I2C SERIAL INTERFACE3.0/3.3V OPERATING VOLTAGE–VCC = 2.7 to 3.6V
ULTRA-LOW BATTERY SUPPLY CURRENT of 500nA (max)
RoHS COMPLIANCE
Lead-free components are compliant with the RoHS Directive.
Figure 1. 28-pin SOIC PackageSNAPHAT (SH)Battery & Crystal281SOH28 (MH)Serial RTC Features■400kHz I2C■44 Bytes of General Purpose NVRAM■Counters for:
–Seconds, Minutes, Hours, Day, Date,
Month, and Year–Century
–10ths/100ths of seconds
–Clock Calibration register allows
compensation for crystal variations over temperature
■Programmable Alarm with Repeat Modes
–Functions in Battery Back-up Mode■Power-down Timestamp (HT Bit)■2.5 to 5.5V Oscillator Operating VoltageMicroprocessor Supervisor Features■Programmable Watchdog
–62.5ms to 128s time-out period■Power-on Reset/Low Voltage Detect
–Open drain reset output
–Reset voltage, VPFD = 2.60V (nom)–Two Reset input pins
–Watchdog can be steered to Reset output■Early Power-fail Warning circuit (PFI/PFO)
with 1.25V Precision Reference
Figure 2. 28-pin (300mil) SOIC PackageEMBEDDED CrystalSOX28 (MX)NVRAM Supervisor Features■Non-volatizes external LPSRAM
–Automatically switches to back-up battery
and deselects (write-protects) external LPSRAM via chip-enable gate
–Power-fail deselect (write protect) voltage,
VPFD = 2.60V (nom)
–Switchover , VSO = 2.50V (nom)■Battery Monitor (Battery Low flag)Other Features■Programmable Squarewave Generator (1Hz
to 32KHz)■–40°C to +85°C Operation■Package Options:
–28-lead SNAPHAT® IC (SOH28)
SNAPHAT Batter/Crystal top to be ordered separately.
–28-lead Embedded Crystal SOIC
(SOX28)
Rev 8.0
January 20061/34
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M41ST85W
TABLE OF CONTENTS
KEY FEATURES. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
Serial RTC Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1Microprocessor Supervisor Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1Figure 1.28-pin SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1Figure 2.28-pin (300mil) SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1NVRAM Supervisor Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1Other Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1SUMMARY DESCRIPTION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
Figure 3.Table 1.Figure 4.Figure 5.Figure 6.Figure 7.
Logic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5Signal Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .528-pin SOIC Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .528-pin, 300mil SOIC (MX) Connections. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6Hardware Hookup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
OPERATING MODES. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
2-Wire Bus Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8Figure 8.Serial Bus Data Transfer Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9Figure 9.Acknowledgement Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9Figure 10.WRITE Cycle Timing: RTC & External SRAM Control Signals. . . . . . . . . . . . . . . . . . . . .9READ Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10Figure 11.Slave Address Location. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10Figure 12.READ Mode Sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11Figure 13.Alternate READ Mode Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11WRITE Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12Figure 14.WRITE Mode Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12Data Retention Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12CLOCK OPERATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
Power-down Time-Stamp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13TIMEKEEPER® Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13Table 2.TIMEKEEPER® Register Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14Calibrating the Clock. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15Figure 15.Crystal Accuracy Across Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16Figure 16.Calibration Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16Setting Alarm Clock Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17Figure 17.Alarm Interrupt Reset Waveform. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17Table 3.Alarm Repeat Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17Figure 18.Back-Up Mode Alarm Waveform. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18Watchdog Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18Square Wave Output. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19Table 4.Square Wave Output Frequency. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
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M41ST85W
Power-on Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20Reset Inputs (RSTIN1 & RSTIN2). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20Figure 19.RSTIN1 & RSTIN2 Timing Waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20Table 5.Reset AC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20Power-fail INPUT/OUTPUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21Century Bit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21Output Driver Pin. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21Battery Low Warning. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21trec Bit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22Initial Power-on Defaults. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22Table 6.trec Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22Table 7.Default Values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
Table 8.Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23DC and AC PARAMETERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
Table 9.DC and AC Measurement Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24Figure 20.AC Testing Input/Output Waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24Table 10.Capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24Table 11.DC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25Figure 21.Bus Timing Requirements Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26Table 12.AC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26Figure 22.Power Down/Up Mode AC Waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27Table 13.Power Down/Up AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27PACKAGE MECHANICAL INFORMATION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
Figure 23.SOH28 – 28-lead Plastic Small Outline, Battery SNAPHAT, Package Outline. . . . . . . .28Table 14.SOH28 – 28-lead Plastic Small Outline, battery SNAPHAT, Package Mechanical Data28Figure 24.SH – 4-pin SNAPHAT Housing for 48mAh Battery & Crystal, Package Outline. . . . . . .29Table 15.SH – 4-pin SNAPHAT Housing for 48mAh Battery & Crystal, Mechanical Data. . . . . . .29Figure 25.SH – 4-pin SNAPHAT Housing for 120mAh Battery & Crystal, Package Outline. . . . . .30Table 16.SH – 4-pin SNAPHAT Housing for 120mAh Battery & Crystal, Mechanical Data. . . . . .30Figure 26.SOX28 – 28-lead Plastic Small Outline, 300mils, Embedded Crystal, Package Outline.31Table 17.SOX28 – 28-lead Plastic Small Outline, 300mils, Embedded Crystal, Mech. Data. . . . .31PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
Table 18.Ordering Information Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32Table 19.SNAPHAT Battery/Crystal Table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32REVISION HISTORY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
Table 20.Document Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
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M41ST85W
SUMMARY DESCRIPTION
The M41ST85W is a combination Serial Real-Time Clock, Microprocessor Supervisor, andNVRAM Supervisor. It is built in a low powerCMOS SRAM process and has a 64-byte memoryspace with 44 bytes of NVRAM and 20 memory-mapped RTC registers (see Table 2.,page14).The RTC registers are configured in binary codeddecimal (BCD) format.
The M41ST85W combines a 400kHz I2C SerialRTC with an Automatic Back-up Battery Switcho-ver circuit for powering an external LPSRAM aswell as the internal RTC. When power begins tofail, the switchover automatically connects to theback-up battery to keep the RTC and externalLPSRAM alive in the absence of system power.Access to the LPSRAM is also cut off via a chip-enable gate function, thereby write-protecting thememory. A programmable Watchdog and Power-on Reset/Low Voltage Detect function are the keyelements in the Microprocessor Supervisor sec-tion.
The Real-Time Clock includes a built-in32.768kHz oscillator (crystal-controlled), whichprovides the time base for the timekeeping andcalendar functions. Eight of the 20 clock registersprovide the basic clock/calendar functions whilethe other 12 bytes provide status/control for theAlarm, Watchdog, and Squarewave functions.RTC addresses and data are transferred seriallyvia the two-line, bi-directional I2C interface. Thebuilt-in address register is incremented automati-cally after each WRITE or READ data byte.
The M41ST85W has a built-in power sense circuitwhich detects power failures and automaticallyswitches to the back-up battery when a power fail-ure occurs. During an outage, the power to sustainthe SRAM and clock operations is typically sup-plied by a small lithium button-cell battery as is thecase when using the SNAPHAT® package option.Functions available to the user include a non-vol-atile, time-of-day clock/calendar, Alarm interrupts,Watchdog Timer, and programmable Squarewavegenerator. Other features include a Power-on Re-set as well as two additional debounce reset inputs(RSTIN1 and RSTIN2) which can also generate anoutput Reset (RST).The eight registers for basic clock/calendar func-tions contain the century, year, month, date, day,hour, minute, second, and tenths/hundredths of asecond in 24 hour BCD format. Corrections for 28,29 (leap year - valid until year 2100), 30 and 31day months are made automatically.
The M41ST85W is offered in two 28-lead SOICpackages. The 300mil SOH28 SNAPHAT IC pack-age mates with ST’s SNAPHAT Battery/Crystaltop (ordered separately). SNAPHAT battery op-tions include 48mAh and 120mAh. ST’s 300milSOX28 Embedded Crystal IC includes the 32KHzcrystal and is perfect for applications where a lowprofile is a must.
The SOH28 SNAPHAT SOIC includes socketswith gold plated contacts at both ends for directconnection to the SNAPHAT top. The SNAPHATbattery/crystal top is inserted atop the IC packageafter the completion of the surface mount assem-bly process which avoids potential battery andcrystal damage due to the high temperatures re-quired for device surface-mounting. The uniquedesign allows the battery to be replaced, thus ex-tending the life of the RTC and NVRAM indefinite-ly.
The SNAPHAT top is keyed to prevent reverse in-sertion. The SNAPHAT IC and SNAPHAT tops areshipped separately. The ICs are available in plas-tic anti-static tubes or in Tape & Reel form. TheSNAPHAT tops are shipped in plastic anti-statictubes. The part numbers are M4T28-BR12SH1(48mAh) and M4T32-BR12SH1 (120mAh). Forthe extended temperature requirement, the120mAh M4T32-BR12SH6 is available. For moreinformation, see Table 19.,page32.
Caution: Do not place the SNAPHAT battery/crys-tal top in conductive foam, as this will drain the lith-ium button-cell battery.
The 300mil SOX embedded crystal SOIC typicallyrequires a user-supplied battery for non-volatileoperation. Capacitor back-up can also be imple-mented with this package.
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M41ST85W
Figure 3. Logic DiagramVCCVBAT(1)Table 1. Signal Names
ECONEXIRQ/FT/OUTConditioned Chip Enable OutputExternal Chip Enable
Interrupt/Frequency Test/Out Output (Open Drain)Power Fail InputPower Fail Output
Reset Output (Open Drain)Reset 1 InputReset 2 InputSerial Clock InputSerial Data Input/OutputSquare Wave OutputWatchdog InputSupply VoltageVoltage OutputGround
Battery Supply VoltageNo ConnectNo Function
SCLSDAEXRSTIN1RSTIN2WDIPFIM41ST85WPFI
ECONRSTIRQ/FT/OUTSQWPFOVOUTPFORSTRSTIN1RSTIN2SCLSDASQWWDIVCCVOUT
VSSVSS
AI03658VBAT(1)NCNF
Note:1.For 28-pin, 300mil embedded crystal SOIC only.
Note:1.For 28-pin, 300mil embedded crystal SOIC only.
Figure 4. 28-pin SOIC ConnectionsSQWNCNCNCNCNCNCWDIRSTIN1RSTIN2NCNCPFOVSS281227326425524623722M41ST85W82192010191118121713161415AI03659Figure 5. 28-pin, 300mil SOIC (MX)
ConnectionsNFNFNFNFNCNCNCSQWWDIRSTIN1RSTIN2PFONCVSS281227326425524623722M41ST85W82192010191118121713161415VCCEXIRQ/FT/OUTVOUTNCPFISCLNCNCRSTNCSDAECONVBATAI06370dVCCEXIRQ/FT/OUTVOUTNCNCPFINCSCLNCRSTNCSDAECONNote:No Function (NF) pins should be tied to VSS. Pins 1, 2, 3, and
4 are internally shorted together.
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M41ST85W
Figure 6. Block DiagramREAL TIME CLOCKCALENDARSDAI2CINTERFACE44 BYTES USER RAMRTC w/ALARM& CALIBRATIONWATCHDOGSQUARE WAVEAFEWDSIRQ/FT/OUT(1)SCL(2)Crystal32KHzOSCILLATORSQWWDIVCCVOUTVBATVBL= 2.5VCOMPAREBLVSO = 2.5VCOMPAREVPFD = 2.65VRSTIN1RSTIN2COMPAREPORRST(1)EXPFI1.25V(Internal)COMPAREECONPFOAI03932Note:1.Open drain output
2.Crystal integrated into SOIC package for MX package option.
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M41ST85W
Figure 7. Hardware HookupRegulatorVINVCCVCCM41ST85WVOUTECONEXSCLFrom MCUSDAWDIRSTIN1PushbuttonResetRSTIN2RSTSQWPFOPFIR2VBATVSS(1)IRQ/FT/OUTTo RSTTo LED DisplayTo NMITo INTVCCELPSRAMUnregulatedVoltageR1AI03660Note:1.Required for embedded crystal (MX) package only.
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M41ST85W
OPERATING MODES
The M41ST85W clock operates as a slave deviceon the serial bus. Access is obtained by imple-menting a start condition followed by the correctslave address (D0h). The 64 bytes contained inthe device can then be accessed sequentially inthe following order:
1.Tenths/Hundredths of a Second Register2.Seconds Register3.Minutes Register
4.Century/Hours Register5.Day Register6.Date Register7.Month Register8.Year Register 9.Control Register10.Watchdog Register11 - 16. Alarm Registers17 - 19. Reserved
20. Square Wave Register21 - 64. User RAM
The M41ST85W clock continually monitors VCCfor an out-of-tolerance condition. Should VCC fallbelow VPFD, the device terminates an access inprogress and resets the device address counter.Inputs to the device will not be recognized at thistime to prevent erroneous data from being writtento the device from a an out-of-tolerance system.When VCC falls below VSO, the device automati-cally switches over to the battery and powersdown into an ultra low current mode of operation toconserve battery life. As system power returns andVCC rises above VSO, the battery is disconnected,and the power supply is switched to external VCC.Write protection continues until VCC reachesVPFD(min) plus trec (min).
For more information on Battery Storage Life referto Application Note AN1012.2-Wire Bus Characteristics
The bus is intended for communication betweendifferent ICs. It consists of two lines: a bi-direction-al data signal (SDA) and a clock signal (SCL).Both the SDA and SCL lines must be connected toa positive supply voltage via a pull-up resistor.The following protocol has been defined:
–Data transfer may be initiated only when the bus is not busy.
–During data transfer, the data line must remain stable whenever the clock line is High.
–Changes in the data line, while the clock line is High, will be interpreted as control signals.
Accordingly, the following bus conditions havebeen defined:
Bus not busy.Both data and clock lines remainHigh.
Start data transfer.A change in the state of thedata line, from High to Low, while the clock is High,defines the START condition.
Stop data transfer.A change in the state of thedata line, from Low to High, while the clock is High,defines the STOP condition.
Data Valid.The state of the data line representsvalid data when after a start condition, the data lineis stable for the duration of the high period of theclock signal. The data on the line may be changedduring the Low period of the clock signal. There isone clock pulse per bit of data.
Each data transfer is initiated with a start conditionand terminated with a stop condition. The numberof data bytes transferred between the start andstop conditions is not limited. The information istransmitted byte-wide and each receiver acknowl-edges with a ninth bit.
By definition a device that gives out a message iscalled “transmitter,” the receiving device that getsthe message is called “receiver.” The device thatcontrols the message is called “master.” The de-vices that are controlled by the master are called“slaves.”
Acknowledge.Each byte of eight bits is followedby one Acknowledge Bit. This Acknowledge Bit isa low level put on the bus by the receiver whereasthe master generates an extra acknowledge relat-ed clock pulse. A slave receiver which is ad-dressed is obliged to generate an acknowledgeafter the reception of each byte that has beenclocked out of the slave transmitter.
The device that acknowledges has to pull downthe SDA line during the acknowledge clock pulsein such a way that the SDA line is a stable Low dur-ing the High period of the acknowledge relatedclock pulse. Of course, setup and hold times mustbe taken into account. A master receiver must sig-nal an end of data to the slave transmitter by notgenerating an acknowledge on the last byte thathas been clocked out of the slave. In this case thetransmitter must leave the data line High to enablethe master to generate the STOP condition.
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M41ST85W
Figure 8. Serial Bus Data Transfer SequenceDATA LINESTABLEDATA VALIDCLOCKDATA STARTCONDITIONCHANGE OFDATA ALLOWEDSTOPCONDITIONAI00587Figure 9. Acknowledgement SequenceSTARTSCL FROMMASTERDATA OUTPUTBY TRANSMITTERDATA OUTPUTBY RECEIVERAI00601CLOCK PULSE FORACKNOWLEDGEMENT1289MSBLSBFigure 10. WRITE Cycle Timing: RTC & External SRAM Control SignalsEXtEXPDtEXPDECONAI036639/34
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M41ST85W
READ Mode
In this mode the master reads the M41ST85Wslave after setting the slave address (see Figure11.). Following the WRITE Mode Control Bit (R/W=0) and the Acknowledge Bit, the word address'An' is written to the on-chip address pointer. Nextthe START condition and slave address are re-peated followed by the READ Mode Control Bit (R/W=1). At this point the master transmitter be-comes the master receiver.
The data byte which was addressed will be trans-mitted and the master receiver will send an Ac-knowledge Bit to the slave transmitter. Theaddress pointer is only incremented on receptionof an Acknowledge Clock. The M41ST85W slavetransmitter will now place the data byte at addressAn+1 on the bus, the master receiver reads andacknowledges the new byte and the addresspointer is incremented to An+2.Figure 11. Slave Address LocationR/WThis cycle of reading consecutive addresses willcontinue until the master receiver sends a STOPcondition to the slave transmitter (see Figure12.,page11).
The system-to-user transfer of clock data will behalted whenever the address being read is a clockaddress (00h to 07h). The update will resume ei-ther due to a Stop Condition or when the pointerincrements to a non-clock or RAM address.
Note: This is true both in READ Mode and WRITEMode.
An alternate READ Mode may also be implement-ed whereby the master reads the M41ST85Wslave without first writing to the (volatile) addresspointer. The first address that is read is the lastone stored in the pointer (see Figure13.,page11).
STARTSLAVE ADDRESSAMSB110100LSB0AI0060210/34
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M41ST85W
Figure 12. READ Mode SequenceSTARTSTARTR/WBUS ACTIVITY:MASTERSDA LINESWORDADDRESS (An)SR/WDATA nDATA n+1ACKACKACKACKBUS ACTIVITY:SLAVEADDRESSSLAVEADDRESSDATA n+XSTOPPAI00899Figure 13. Alternate READ Mode SequenceSTARTSTOPDATA nACKACKDATA n+1ACKACKDATA n+XPNO ACKAI00895BUS ACTIVITY:MASTERSDA LINESBUS ACTIVITY:SLAVEADDRESSR/WNO ACKACK11/34
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M41ST85W
WRITE Mode
In this mode the master transmitter transmits tothe M41ST85W slave receiver. Bus protocol isshown in Figure 14.. Following the START condi-tion and slave address, a logic '0' (R/W=0) isplaced on the bus and indicates to the addresseddevice that word address An will follow and is to bewritten to the on-chip address pointer. The dataword to be written to the memory is strobed in nextFigure 14. WRITE Mode SequenceSTARTand the internal address pointer is incremented tothe next memory location within the RAM on thereception of an acknowledge clock. TheM41ST85W slave receiver will send an acknowl-edge clock to the master transmitter after it has re-ceived the slave address (see Figure11.,page10) and again after it has received theword address and each data byte.
BUS ACTIVITY:MASTERSDA LINER/WSWORDADDRESS (An)ACKACKDATA nDATA n+1DATA n+XACKACKBUS ACTIVITY:SLAVEADDRESSAI00591Data Retention Mode
With valid VCC applied, the M41ST85W can be ac-cessed as described above with READ or WRITECycles. Should the supply voltage decay, theM41ST85W will automatically deselect, write pro-tecting itself (and any external SRAM) when VCCfalls between VPFD(max) and VPFD(min). This isaccomplished by internally inhibiting access to theclock registers. At this time, the Reset pin (RST) isdriven active and will remain active until VCC re-turns to nominal levels. External RAM access is in-hibited in a similar manner by forcing ECON to ahigh level. This level is within 0.2 volts of the VBAT.ECON will remain at this level as long as VCC re-mains at an out-of-tolerance condition. When VCCfalls below the Battery Back-up Switchover Volt-age (VSO), power input is switched from the VCCpin to the SNAPHAT® battery, and the clock regis-ters and external SRAM are maintained from theattached battery supply.
All outputs become high impedance. The VOUT pinis capable of supplying 100 µA of current to the at-tached memory with less than 0.3 volts drop underthis condition. On power up, when VCC returns toa nominal value, write protection continues for trecby inhibiting ECON. The RST signal also remainsactive during this time (see Figure 22.,page27). Note: Most low power SRAMs on the market to-day can be used with the M41ST85W RTC SU-PERVISOR. There are, however some criteriawhich should be used in making the final choice of
an SRAM to use. The SRAM must be designed ina way where the chip enable input disables all oth-er inputs to the SRAM. This allows inputs to theM41ST85W and SRAMs to be “Don’t Care” onceVCC falls below VPFD(min). The SRAM should alsoguarantee data retention down to VCC=2.0 volts.The chip enable access time must be sufficient tomeet the system needs with the chip enable outputpropagation delays included. If the SRAM includesa second chip enable pin (E2), this pin should betied to VOUT.
If data retention lifetime is a critical parameter forthe system, it is important to review the data reten-tion current specifications for the particularSRAMs being evaluated. Most SRAMs specify adata retention current at 3.0 volts. Manufacturersgenerally specify a typical condition for room tem-perature along with a worst case condition (gener-ally at elevated temperatures). The system levelrequirements will determine the choice of whichvalue to use. The data retention current value ofthe SRAMs can then be added to the IBAT value ofthe M41ST85W to determine the total current re-quirements for data retention. The available bat-tery capacity for the SNAPHAT® top of your choicecan then be divided by this current to determinethe amount of data retention available (see Table19.,page32).
For a further more detailed review of lifetime calcu-lations, please see Application Note AN1012.
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M41ST85W
CLOCK OPERATION
The eight byte clock register (see Table2.,page14) is used to both set the clock and toread the date and time from the clock, in a binarycoded decimal format. Tenths/Hundredths of Sec-onds, Seconds, Minutes, and Hours are containedwithin the first four registers.
Note: A WRITE to any clock register will result inthe Tenths/Hundredths of Seconds being reset to“00,” and Tenths/Hundredths of Seconds cannotbe written to any value other than “00.”
Bits D6 and D7 of Clock Register 03h (Century/Hours Register) contain the CENTURY ENABLEBit (CEB) and the CENTURY Bit (CB). SettingCEB to a '1' will cause CB to toggle, either from '0'to '1' or from '1' to '0' at the turn of the century (de-pending upon its initial state). If CEB is set to a '0,'CB will not toggle. Bits D0 through D2 of Register04h contain the Day (day of week). Registers 05h,06h, and 07h contain the Date (day of month),Month and Years. The ninth clock register is theControl Register (this is described in the ClockCalibration section). Bit D7 of Register 01h con-tains the STOP Bit (ST). Setting this bit to a '1' willcause the oscillator to stop. If the device is expect-ed to spend a significant amount of time on theshelf, the oscillator may be stopped to reduce cur-rent drain. When reset to a '0' the oscillator restartswithin one second.
The eight Clock Registers may be read one byte ata time, or in a sequential block. The Control Reg-ister (Address location 08h) may be accessed in-dependently. Provision has been made to assurethat a clock update does not occur while any of theeight clock addresses are being read. If a clock ad-dress is being read, an update of the clock regis-ters will be halted. This will prevent a transition ofdata during the READ.
Power-down Time-Stamp
When a power failure occurs, the Halt Update Bit(HT) will automatically be set to a '1.' This will pre-vent the clock from updating the TIMEKEEPER®registers, and will allow the user to read the exacttime of the power-down event. Resetting the HTBit to a '0' will allow the clock to update the TIME-KEEPER registers with the current time. For moreinformation, see Application Note AN1572.TIMEKEEPER® Registers
The M41ST85W offers 20 internal registers whichcontain Clock, Alarm, Watchdog, Flag, SquareWave and Control data. These registers are mem-ory locations which contain external (user accessi-ble) and internal copies of the data (usuallyreferred to as BiPORT™ TIMEKEEPER cells). Theexternal copies are independent of internal func-tions except that they are updated periodically bythe simultaneous transfer of the incremented inter-nal copy. The internal divider (or clock) chain willbe reset upon the completion of a WRITE to anyclock address.
The system-to-user transfer of clock data will behalted whenever the address being read is a clockaddress (00h to 07h). The update will resume ei-ther due to a Stop Condition or when the pointerincrements to a non-clock or RAM address.
TIMEKEEPER and Alarm Registers store data inBCD. Control, Watchdog and Square Wave Reg-isters store data in Binary Format.
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M41ST85W
Table 2. TIMEKEEPER® Register Map
Address 00h01h02h03h04h05h06h07h08h09h0Ah0Bh0Ch0Dh0Eh0Fh10h11h12h13h
OUTWDSAFERPT4RPT3RPT2RPT1WDF000RS3ST0CEBTR00
CB000
0
Data
D7
D6
D5
D4
D3
D2
D1
D0
Function/RangeBCD FormatSecondsSecondsMinutesCentury/Hours
DayDateMonthYearControl
RB1
RB0
WatchdogAl MonthAl DateAl HourAl MinAl Sec
00000
FlagsReservedReservedReservedSQW
01-1201-3100-2300-5900-5900-9900-5900-590-1/00-2301-701-3101-1200-99
0.1 Seconds
10 Seconds10 Minutes
10 Hours010 Date
10M0
0
0.01 SecondsSecondsMinutes
Hours (24 Hour Format)
Day of Week
Date: Day of Month
MonthYear
Calibration
BMB2Al 10M
BMB1
BMB0
10 YearsFTBMB4SQWERPT5HT
SBMB3ABE
Alarm MonthAlarm DateAlarm HourAlarm MinutesAlarm Seconds
00000
00000
00000
AI 10 DateAI 10 Hour
Alarm 10 MinutesAlarm 10 SecondsAF000RS2
0000RS1
BL000RS0
Keys: S = Sign Bit
FT = Frequency Test BitST = Stop Bit
0 = Must be set to zero
BL = Battery Low Flag (Read only)
BMB0-BMB4 = Watchdog Multiplier BitsCEB = Century Enable BitCB = Century BitOUT = Output level
AFE = Alarm Flag Enable FlagRB0-RB1 = Watchdog Resolution BitsWDS = Watchdog Steering Bit
ABE = Alarm in Battery Back-Up Mode Enable BitRPT1-RPT5 = Alarm Repeat Mode BitsWDF = Watchdog flag (Read only)AF = Alarm flag (Read only)SQWE = Square Wave EnableRS0-RS3 = SQW FrequencyHT = Halt Update BitTR = trec Bit
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M41ST85W
Calibrating the Clock
The M41ST85W is driven by a quartz controlledoscillator with a nominal frequency of 32,768 Hz.The devices are tested not exceed +/–35 ppm(parts per million) oscillator frequency error at25oC, which equates to about +/–1.53 minutes permonth. When the Calibration circuit is properly em-ployed, accuracy improves to better than ±2 ppmat 25°C.
The oscillation rate of crystals changes with tem-perature (see Figure 15.,page16). Therefore, theM41ST85W design employs periodic counter cor-rection. The calibration circuit adds or subtractscounts from the oscillator divider circuit at the di-vide by 256 stage, as shown in Figure16.,page16. The number of times pulses whichare blanked (subtracted, negative calibration) orsplit (added, positive calibration) depends uponthe value loaded into the five Calibration Bits foundin the Control Register. Adding counts speeds theclock up, subtracting counts slows the clock down.The Calibration Bits occupy the five lower orderbits (D4-D0) in the Control Register (08h). Thesebits can be set to represent any value between 0and 31 in binary form. Bit D5 is a Sign Bit; '1' indi-cates positive calibration, '0' indicates negativecalibration. Calibration occurs within a 64 minutecycle. The first 62 minutes in the cycle may, onceper minute, have one second either shortened by128 or lengthened by 256 oscillator cycles. If a bi-nary '1' is loaded into the register, only the first 2minutes in the 64 minute cycle will be modified; ifa binary 6 is loaded, the first 12 will be affected,and so on.
Therefore, each calibration step has the effect ofadding 512 or subtracting 256 oscillator cycles forevery 125,829,120 actual oscillator cycles, that is+4.068 or –2.034 ppm of adjustment per calibra-tion step in the calibration register. Assuming thatthe oscillator is running at exactly 32,768 Hz, eachof the 31 increments in the Calibration byte wouldrepresent +10.7 or –5.35 seconds per monthwhich corresponds to a total range of +5.5 or –2.75minutes per month.
Two methods are available for ascertaining howmuch calibration a given M41ST85W may require.The first involves setting the clock, letting it run fora month and comparing it to a known accurate ref-erence and recording deviation over a fixed periodof time. Calibration values, including the number ofseconds lost or gained in a given period, can befound in Application Note AN934, “TIMEKEEP-ER® CALIBRATION.” This allows the designer togive the end user the ability to calibrate the clockas the environment requires, even if the final prod-uct is packaged in a non-user serviceable enclo-sure. The designer could provide a simple utilitythat accesses the Calibration byte.
The second approach is better suited to a manu-facturing environment, and involves the use of theIRQ/FT/OUT pin. The pin will toggle at 512Hz,when the Stop Bit (ST, D7 of 01h) is '0,' the Fre-quency Test Bit (FT, D6 of 08h) is '1,' the AlarmFlag Enable Bit (AFE, D7 of 0Ah) is '0,' and theWatchdog Steering Bit (WDS, D7 of 09h) is '1' orthe Watchdog Register (09h = 0) is reset.
Any deviation from 512 Hz indicates the degreeand direction of oscillator frequency shift at the testtemperature. For example, a reading of512.010124 Hz would indicate a +20 ppm oscilla-tor frequency error, requiring a –10 (XX001010) tobe loaded into the Calibration Byte for correction.Note that setting or changing the Calibration Bytedoes not affect the Frequency test output frequen-cy.
The IRQ/FT/OUT pin is an open drain outputwhich requires a pull-up resistor to VCC for properoperation. A 500 to10k resistor is recommended inorder to control the rise time. The FT Bit is clearedon power-down.
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M41ST85W
Figure 15. Crystal Accuracy Across TemperatureFrequency (ppm)200–20–40–60–80–100–120–140–160–40–30–20–1001020304050607080∆F= K x (T – T)2OFK= –0.036 ppm/°C ± 0.006 ppm/°CTO = 25°C ± 5°C22Temperature °CAI07888Figure 16. Calibration WaveformNORMALPOSITIVECALIBRATIONNEGATIVECALIBRATIONAI00594B16/34
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M41ST85W
Setting Alarm Clock Registers
Address locations 0Ah-0Eh contain the alarm set-tings. The alarm can be configured to go off at aprescribed time on a specific month, date, hour,minute, or second, or repeat every year, month,day, hour, minute, or second. It can also be pro-grammed to go off while the M41ST85W is in thebattery back-up to serve as a system wake-up call.Bits RPT5–RPT1 put the alarm in the repeat modeof operation. Table 3. shows the possible configu-rations. Codes not listed in the table default to theonce per second mode to quickly alert the user ofan incorrect alarm setting.
When the clock information matches the alarmclock settings based on the match criteria definedby RPT5–RPT1, the AF (Alarm Flag) is set. If AFE(Alarm Flag Enable) is also set, the alarm condi-tion activates the IRQ/FT/OUT pin as shown inFigure 17.. To disable alarm, write '0' to the AlarmDate Register and to RPT5–RPT1.
Note: If the address pointer is allowed to incre-ment to the Flag Register address, an alarm con-Figure 17. Alarm Interrupt Reset Waveformdition will not cause the Interrupt/Flag to occur until
the address pointer is moved to a different ad- dress. It should also be noted that if the last ad-dress written is the “Alarm Seconds,” the address
pointer will increment to the Flag address, causing this situation to occur.
The IRQ/FT/OUT output is cleared by a READ tothe Flags Register. A subsequent READ of theFlags Register is necessary to see that the valueof the Alarm Flag has been reset to '0.'
The IRQ/FT/OUT pin can also be activated in thebattery back-up mode. The IRQ/FT/OUT will golow if an alarm occurs and both ABE (Alarm in Bat-tery Back-up Mode Enable) and AFE are set. TheABE and AFE Bits are reset during power-up,therefore an alarm generated during power-up willonly set AF. The user can read the Flag Registerat system boot-up to determine if an alarm wasgenerated while the M41ST85W was in the dese-lect mode during power-up. Figure 18.,page18 il-lustrates the back-up mode alarm timing.
0Eh0Fh10hACTIVE FLAGIRQ/FT/OUTHIGH-ZAI03664Table 3. Alarm Repeat Modes
RPT5111110
RPT4111100
RPT3111000
RPT2110000
RPT1100000
Alarm SettingOnceperSecondOnceperMinuteOnceperHourOnceperDayOnceperMonthOnceperYear
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M41ST85W
Figure 18. Back-Up Mode Alarm WaveformVCCVPFDVSOtrecABE, AFE Bits in Interrupt RegisterAF bit in Flags RegisterIRQ/FT/OUTHIGH-ZHIGH-ZAI03920Watchdog Timer
The watchdog timer can be used to detect an out-of-control microprocessor. The user programs thewatchdog timer by setting the desired amount oftime-out into the Watchdog Register, address 09h.Bits BMB4-BMB0 store a binary multiplier and thetwo lower order bits RB1-RB0 select the resolu-tion, where 00=1/16 second, 01=1/4 second, 10=1second, and 11=4 seconds. The amount of time-out is then determined to be the multiplication ofthe five-bit multiplier value with the resolution. (Forexample: writing 00001110 in the Watchdog Reg-ister = 3*1 or 3 seconds).
Note: The accuracy of the timer is within ± the se-lected resolution.
If the processor does not reset the timer within thespecified period, the M41ST85W sets the WDF(Watchdog Flag) and generates a watchdog inter-rupt or a microprocessor reset.
The most significant bit of the Watchdog Registeris the Watchdog Steering Bit (WDS). When set toa '0,' the watchdog will activate the IRQ/FT/OUTpin when timed-out. When WDS is set to a '1,' thewatchdog will output a negative pulse on the RSTpin for trec. The Watchdog register, FT, AFE, ABEand SQWE Bits will reset to a '0' at the end of aWatchdog time-out when the WDS Bit is set to a'1.'
The watchdog timer can be reset by two methods:1) a transition (high-to-low or low-to-high) can beapplied to the Watchdog Input pin (WDI) or 2) themicroprocessor can perform a WRITE of theWatchdog Register. The time-out period thenstarts over.
Note: The WDI pin should be tied to VSS if notused.
In order to perform a software reset of the watch-dog timer, the original time-out period can be writ-ten into the Watchdog Register, effectivelyrestarting the count-down cycle.
Should the watchdog timer time-out, and the WDSBit is programmed to output an interrupt, a value of00h needs to be written to the Watchdog Registerin order to clear the IRQ/FT/OUT pin. This will alsodisable the watchdog function until it is again pro-grammed correctly. A READ of the Flags Registerwill reset the Watchdog Flag (Bit D7; Register0Fh).
The watchdog function is automatically disabledupon power-up and the Watchdog Register iscleared. If the watchdog function is set to output tothe IRQ/FT/OUT pin and the frequency test func-tion is activated, the watchdog function prevailsand the frequency test function is denied.
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M41ST85W
Square Wave Output
The M41ST85W offers the user a programmablesquare wave function which is output on the SQWpin. RS3-RS0 bits located in 13h establish thesquare wave output frequency. These frequenciesare listed in Table 4. Once the selection of theTable 4. Square Wave Output Frequency
Square Wave Bits
RS30000000011111111
RS20000111100001111
RS10011001100110011
RS00101010101010101
Square Wave
FrequencyNone32.7688.1924.0962.0481.0245122561286432168421
Units–kHzkHzkHzkHzkHzHzHzHzHzHzHzHzHzHzHz
SQW frequency has been completed, the SQWpin can be turned on and off under software con-trol with the Square Wave Enable Bit (SQWE) lo-cated in Register 0Ah.
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M41ST85W
Power-on Reset
The M41ST85W continuously monitors VCC.When VCC falls to the power fail detect trip point,the RST pulls low (open drain) and remains low onpower-up for trec after VCC passes VPFD(max).The RST pin is an open drain output and an appro-priate pull-up resistor should be chosen to controlrise time.
Reset Inputs (RSTIN1 & RSTIN2)The M41ST85W provides two independent inputswhich can generate an output reset. The durationand function of these resets is identical to a resetgenerated by a power cycle. Table 5. and Figure19. illustrate the AC reset characteristics of thisfunction. Pulses shorter than tRLRH1 and tRLRH2will not generate a reset condition. RSTIN1 andRSTIN2 are each internally pulled up to VCCthrough a 100kΩ resistor.
Figure 19. RSTIN1 & RSTIN2 Timing WaveformsRSTIN1tRLRH1RSTIN2tRLRH2RST (1)tR1HRHtR2HRHAI03665Note:With pull-up resistor
Table 5. Reset AC Characteristics
SymboltRLRH1(2)tRLRH2(3)tR1HRH(4)tR2HRH(4)
Note:1.
2.3.4.
Parameter(1)
RSTIN1 Low to RSTIN1 HighRSTIN2 Low to RSTIN2 HighRSTIN1 High to RST HighRSTIN2 High to RST HighMin2001004040
MaxUnitnsms
200200
msms
Valid for Ambient Operating Temperature: TA = –40 to 85°C; VCC = 2.7 to 3.6V (except where noted).Pulse width less than 50ns will result in no RESET (for noise immunity).Pulse width less than 20ms will result in no RESET (for noise immunity).Programmable (see Table 6.,page22).
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M41ST85W
Power-fail INPUT/OUTPUT
The Power-Fail Input (PFI) is compared to an in-ternal reference voltage (1.25V). If PFI is less thanthe power-fail threshold (VPFI), the Power-FailOutput (PFO) will go low. This function is intendedfor use as an undervoltage detector to signal a fail-ing power supply. Typically PFI is connectedthrough an external voltage divider (see Figure7.,page7) to either the unregulated DC input (if itis available) or the regulated output of the VCC reg-ulator. The voltage divider can be set up such thatthe voltage at PFI falls below VPFI several millisec-onds before the regulated VCC input to theM41ST85W or the microprocessor drops belowthe minimum operating voltage.
During battery back-up, the power-fail comparatorturns off and PFO goes (or remains) low. This oc-curs after VCC drops below VPFD(min). When pow-er returns, PFO is forced high, irrespective of VPFIfor the write protect time (trec), which is the timefrom VPFD(max) until the inputs are recognized. Atthe end of this time, the power-fail comparator isenabled and PFO follows PFI. If the comparator isunused, PFI should be connected to VSS and PFOleft unconnected.Century Bit
Bits D7 and D6 of Clock Register 03h contain theCENTURY ENABLE Bit (CEB) and the CENTURYBit (CB). Setting CEB to a '1' will cause CB to tog-gle, either from a '0' to '1' or from '1' to '0' at the turnof the century (depending upon its initial state). IfCEB is set to a '0,' CB will not toggle.Output Driver Pin
When the FT Bit, AFE Bit and watchdog registerare not set, the IRQ/FT/OUT pin becomes an out-put driver that reflects the contents of D7 of theControl Register. In other words, when D7 (OUTBit) and D6 (FT Bit) of address location 08h are a'0,' then the IRQ/FT/OUT pin will be driven low.Note: The IRQ/FT/OUT pin is an open drain whichrequires an external pull-up resistor.
Battery Low Warning
The M41ST85W automatically performs batteryvoltage monitoring upon power-up and at factory-programmed time intervals of approximately 24hours. The Battery Low (BL) Bit, Bit D4 of FlagsRegister 0Fh, will be asserted if the battery voltageis found to be less than approximately 2.5V. TheBL Bit will remain asserted until completion of bat-tery replacement and subsequent battery lowmonitoring tests, either during the next power-upsequence or the next scheduled 24-hour interval.If a battery low is generated during a power-up se-quence, this indicates that the battery is below ap-proximately 2.5 volts and may not be able tomaintain data integrity in the SRAM. Data shouldbe considered suspect and verified as correct. Afresh battery should be installed.
If a battery low indication is generated during the24-hour interval check, this indicates that the bat-tery is near end of life. However, data is not com-promised due to the fact that a nominal VCC issupplied. In order to insure data integrity duringsubsequent periods of battery back-up mode, thebattery should be replaced. The SNAPHAT topmay be replaced while VCC is applied to the de-vice.
Note: This will cause the clock to lose time duringthe interval the SNAPHAT battery/crystal top isdisconnected.
The M41ST85W only monitors the battery when anominal VCC is applied to the device. Thus appli-cations which require extensive durations in thebattery back-up mode should be powered-up peri-odically (at least once every few months) in orderfor this technique to be beneficial. Additionally, if abattery low is indicated, data integrity should beverified upon power-up via a checksum or othertechnique.
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M41ST85W
trec Bit
Bit D7 of Clock Register 04h contains the trec Bit(TR). trec refers to the automatic continuation ofthe deselect time after VCC reaches VPFD. This al-lows for a voltage settling time before WRITEsmay again be performed to the device after a pow-er-down condition. The trec Bit will allow the user toset the length of this deselect time as defined byTable 6..
Table 6. trec Definitions
trec Bit (TR)
001
Note:1.Default Setting
Initial Power-on Defaults
Upon initial application of power to the device, thefollowing register bits are set to a '0' state: Watch-dog Register, FT, AFE, ABE, SQWE, and TR. Thefollowing bits are set to a '1' state: ST, OUT, andHT (see Table 7.).
STOP Bit (ST)
01X
trec Time
Min964050
Max98200(1)2000
Unitsmsmsµs
Table 7. Default Values
Condition
Initial Power-up(2)
Subsequent Power-up (with battery back-up)(3)
TR0UC
ST1UC
HT11
Out1UC
FT00
AFE00
ABE00
SQWE00
WATCHDOG Register(1)
00
Note:1.WDS, BMB0-BMB4, RB0, RB1.
2.State of other control bits undefined.3.UC = Unchanged
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M41ST85W
MAXIMUM RATING
Stressing the device above the rating listed in the“Absolute Maximum Ratings” table may causepermanent damage to the device. These arestress ratings only and operation of the device atthese or any other conditions above those indicat-ed in the Operating sections of this specification isTable 8. Absolute Maximum Ratings
SymbolTSTG
Parameter
Storage Temperature (VCC Off, Oscillator Off)
SNAPHAT®
SOIC
Lead-free lead finish(1)
TSLD
Lead Solder Temperature for 10 seconds
Standard (SnPb)lead finish(2,3)
Value–40 to 85–55 to 150
260240–0.3 to VCC+0.3–0.3 to 4.6
201
Unit°C°C°C°CVVmAW
not implied. Exposure to Absolute Maximum Rat-ing conditions for extended periods may affect de-vice reliability. Refer also to theSTMicroelectronics SURE Program and other rel-evant quality documents.
VIOVCCIOPD
Input or Output VoltageSupply VoltageOutput CurrentPower Dissipation
Note:1.For SOH28 package, Lead-free (Pb-free) lead finish: Reflow at peak temperature of 260°C (total thermal budget not to exceed
245°C for greater than 30 seconds).
2.For SOH28 package, standard (SnPb) lead finish: Reflow at peak temperature of 225°C (total thermal budget not to exceed 180°Cfor between 90 to 150 seconds).
3.The SOX28 package has Lead-free (Pb-free) lead finish, but cannot be exposed to peak reflow temperature in excess of 240°C(use same reflow profile as standard (SnPb) lead finish).
CAUTION: Negative undershoots below –0.3V are not allowed on any pin while in the Battery Back-up mode.CAUTION: Do NOT wave solder SOIC to avoid damaging SNAPHAT sockets.23/34
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M41ST85W
DC AND AC PARAMETERS
This section summarizes the operating and mea-surement conditions, as well as the DC and ACcharacteristics of the device. The parameters inthe following DC and AC Characteristic tables arederived from tests performed under the Measure-Table 9. DC and AC Measurement Conditions
Parameter
VCC Supply Voltage
Ambient Operating TemperatureLoad Capacitance (CL)Input Rise and Fall TimesInput Pulse Voltages
Input and Output Timing Ref. Voltages
Note:Output High Z is defined as the point where data is no longer driven.
ment Conditions listed in the relevant tables. De-signers should check that the operating conditionsin their projects match the measurement condi-tions when using the quoted parameters.
M41ST85W2.7 to 3.6V–40 to 85°C
50pF≤ 50ns0.2 to 0.8VCC0.3 to 0.7VCC
Figure 20. AC Testing Input/Output Waveforms0.8VCC0.7VCC0.3VCCAI025680.2VCCTable 10. Capacitance
SymbolCINCOUT(3)tLP
Input CapacitanceOutput Capacitance
Low-pass filter input time constant (SDA and SCL)
Parameter(1,2)
Min
Max71050
UnitpFpFns
Note:1.Effective capacitance measured with power supply at 5V. Sampled only, not 100% tested.
2.At 25°C, f = 1MHz.
3.Outputs are deselected.
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Table 11. DC Characteristics
SymIBAT(2)ICC1ICC2ILI(3)ILO(4)
Parameter
Battery Current OSC ONBattery Current OSC OFFSupply Current
Supply Current (Standby)Input Leakage CurrentInput Leakage Current (PFI)Output Leakage Current
0V ≤ VIN ≤ VCCVOUT1 > VCC – 0.3VVOUT2 > VBAT – 0.3V
0.7VCC–0.32.5
IOH = –1.0mARST, IRQ/FT/OUTIOUT2 = –1.0µAIOL = 3.0mAIOL = 10mA
2.55
VCC = 3V(W)PFI Rising
1.225
2.601.250202.5
2.5
2.9
2.4
3.63.50.40.42.701.27570
3.0
Test Condition(1)
TA = 25°C, VCC = 0V, VBAT = 3V
f = 400kHz
SCL, SDA = VCC – 0.3V
or VSS + 0.3V
0V ≤ VIN ≤ VCC
–25
2M41ST85WMin
Typ40050
0.750.50±125±1100100VCC + 0.30.3VCC3.5(9)Max500
UnitnAnAmAmAµAnAµAmAµAVVVVVVVVVVmVV
IOUT1(5)VOUT Current (Active)IOUT2VIHVILVBATVOH
VOUT Current (Battery Back-up)Input High VoltageInput Low VoltageBattery VoltageOutput High Voltage(6)
Pull-up Supply Voltage (Open Drain)
VOHB(7)VOH (Battery Back-up)VOLVPFDVPFIVSO
Note:1.
2.3.4.5.6.7.
Output Low Voltage
Output Low Voltage (Open Drain)(8)Power Fail DeselectPFI Input ThresholdPFI Hysteresis
Battery Back-up Switchover
Valid for Ambient Operating Temperature: TA = –40 to 85°C; VCC = 2.7 to 3.6V (except where noted).Measured with VOUT and ECON open.
RSTIN1 and RSTIN2 internally pulled-up to VCC through 100KΩ resistor. WDI internally pulled-down to VSS through 100KΩ resistor.Outputs Deselected.
External SRAM must match RTC SUPERVISOR chip VCC specification.For PFO and SQW pins (CMOS).Conditioned output (ECON) can only sustain CMOS leakage current in the battery back-up mode. Higher leakage currents will re-duce battery life.
8.For IRQ/FT/OUT, RST pins (Open Drain): if pulled-up to supply other than VCC, this supply must be equal to, or less than 3.0V whenVCC = 0V (during battery back-up mode).
9.For rechargeable back-up, VBAT (max) may be considered VCC.
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Figure 21. Bus Timing Requirements SequenceSDAtBUFtHD:STAtRSCLtHIGHPStLOWtSU:DATtHD:DATtSU:STASRPtSU:STOtFtHD:STAAI00589Table 12. AC Characteristics
SymbolfSCLtBUFtEXPDtFtHD:DAT(2)tHD:STAtHIGHtLOWtRtSU:DATtSU:STAtSU:STO
SCL Clock Frequency
Time the bus must be free before a new transmission can startEX to ECON Propagation DelaySDA and SCL Fall TimeData Hold Time
START Condition Hold Time (after this period the first clock pulse is generated)Clock High PeriodClock Low PeriodSDA and SCL Rise TimeData Setup Time
START Condition Setup Time (only relevant for a repeated start condition)STOP Condition Setup Time
10060060006006001.3
300
Parameter(1)
Min01.3
15300Max400
UnitkHzµsnsnsµsnsnsµsnsnsnsns
Note:1.Valid for Ambient Operating Temperature: TA = –40 to 85°C; VCC = 2.7 to 3.6V (except where otherwise noted).
2.Transmitter must internally provide a hold time to bridge the undefined region (300ns max) of the falling edge of SCL.
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Figure 22. Power Down/Up Mode AC WaveformsVCCVPFD (max)VPFD (min)VSO tFtFBtPDPFOtDRtRBtrectRINPUTSRECOGNIZEDDON'T CARERECOGNIZEDRSTHIGH-ZOUTPUTSVALID(PER CONTROL INPUT)VALID(PER CONTROL INPUT)ECONAI03661Table 13. Power Down/Up AC Characteristics
SymboltF(2)tFB(3)tPDtPFDtRtRBtrec(4)
Parameter(1)
VPFD(max) to VPFD(min) VCC Fall TimeVPFD(min) to VSS VCC Fall TimeEX at VIH before Power DownPFI to PFO Propagation DelayVPFD(min) to VPFD(max) VCC Rise TimeVSS to VPFD(min) VCC Rise TimePower up Deselect Time
10140
200
Min300100
15
25
Typ
Max
Unitµsµsµsµsµsµsms
Note:1.Valid for Ambient Operating Temperature: TA = –40 to 85°C; VCC = 2.7 to 3.6V (except where otherwise noted).
2.VPFD(max) to VPFD(min) fall time of less than tF may result in deselection/write protection not occurring until200µs after VCC passes VPFD(min).
3.VPFD(min) to VSS fall time of less than tFB may cause corruption of RAM data.4.Programmable (see Table 6.,page22)
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PACKAGE MECHANICAL INFORMATION
Figure 23. SOH28 – 28-lead Plastic Small Outline, Battery SNAPHAT, Package OutlineA2BeACCPeBDNEHA1αL1SOH-ANote:Drawing is not to scale.Table 14. SOH28 – 28-lead Plastic Small Outline, battery SNAPHAT, Package Mechanical Data
Symbol
AA1A2BCDEeeBHLαNCP
1.27
0.052.340.360.1517.718.23–3.2011.510.410°28
0.10
millimeters
Typ
Min
Max3.050.362.690.510.3218.498.89–3.6112.701.278°
0.050
0.0020.0920.0140.0060.6970.324–0.1260.4530.0160°28
0.004
Typ
inches Min
Max0.1200.0140.1060.0200.0120.7280.350–0.1420.5000.0508°
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Figure 24. SH – 4-pin SNAPHAT Housing for 48mAh Battery & Crystal, Package OutlineA1AA3A2eADBeBLESHTK-ANote:Drawing is not to scale.Table 15. SH – 4-pin SNAPHAT Housing for 48mAh Battery & Crystal, Mechanical Data
Symbol
AA1A2A3BDEeAeBL
0.4621.2114.2215.553.202.036.736.48millimeters
Typ
Min
Max9.787.246.990.380.5621.8414.9915.953.612.29
0.01810.83500.55980.61220.12600.07990.26500.2551
Typ
inchesMin
Max0.38500.28500.27520.01500.02200.85980.59020.62800.14210.0902
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Figure 25. SH – 4-pin SNAPHAT Housing for 120mAh Battery & Crystal, Package OutlineA1AA3A2eADBeBLESHTK-ANote:Drawing is not to scale.Table 16. SH – 4-pin SNAPHAT Housing for 120mAh Battery & Crystal, Mechanical Data
Symbol
AA1A2A3BDEeAeBL
0.4621.2117.2715.553.202.038.007.24millimeters
Typ
Min
Max10.548.518.000.380.5621.8418.0315.953.612.29
0.0180.8350.6800.6120.1260.0800.3150.285
Typ
inchesMin
Max0.4150.3350.3150.0150.0220.8600.7100.6280.1420.090
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Figure 26. SOX28 – 28-lead Plastic Small Outline, 300mils, Embedded Crystal, Package OutlineD141h x 45°CEH1528A2BSO-ENote:Drawing is not to scale.AeA1dddA1αLTable 17. SOX28 – 28-lead Plastic Small Outline, 300mils, Embedded Crystal, Mech. Data
Symbol
AA1A2BCDdddEeHLαN
1.27
7.57–10.160.510°28millimeters
Typ
Min2.440.152.290.410.2017.91
Max2.690.312.390.510.3118.010.107.67–10.520.818°
0.050
0.298–0.4000.0200°28
Typ
inchesMin0.0960.0060.0900.0160.0080.705
Max0.1060.0120.0940.0200.0120.7090.0040.302–0.4140.0328°
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PART NUMBERING
Table 18. Ordering Information Scheme
Example:
M41ST
85W
MH
6
E
Device TypeM41ST
Supply Voltage and Write Protect Voltage85W = VCC = 2.7 to 3.6V; 2.55V ≤ VPFD ≤ 2.70V
PackageMH(1) = SOH28MX(2) = SOX28
Temperature Range6 = –40 to 85°C
Shipping MethodFor SOH28:
blank = Tubes (Not for New Design - Use E)E = ECOPACK Package, TubesF = ECOPACK Package, Tape & Reel
TR = Tape & Reel (Not for New Design - Use F)For SOX28:
blank = ECOPACK Package, TubesTR = ECOPACK Package, Tape & Reel
Note:1.The 28-pin SOIC package (SOH28) requires the SNAPHAT® battery/crystal package which is ordered separately under the part
number “M4TXX-BR12SHX” in plastic tube or “M4Txx-BR12SHXTR” in Tape & Reel form (see Table 19.).2.The SOX28 package includes an embedded 32,768Hz crystal.
Caution: Do not place the SNAPHAT battery package “M4Txx-BR12SH” in conductive foam as it will drain the lithium button-cell bat-tery.
For other options, or for more information on any aspect of this device, please contact the ST Sales Officenearest you.
Table 19. SNAPHAT Battery/Crystal Table
Part NumberM4T28-BR12SHM4T32-BR12SH
Description
Lithium Battery (48mAh) and Crystal SNAPHAT TopLithium Battery (120mAh) and Crystal SNAPHAT Top
PackageSHSH
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REVISION HISTORY
Table 20. Document Revision History
DateAugust 200024-Aug-0012-Oct-0018-Dec-00
Version1.01.11.22.0
First issue
Block Diagram added (Figure 3)
trec Table removed, cross references corrected
Reformatted, TOC added, and PFI Input Leakage Current added (Table 11)
Addition of trec information, table changed, one added (Tables 2, 6); changed PFI/PFO graphic (see Figure 6); change to DC and AC Characteristics, Order Information (Tables 11, 12, 18); note added to “Setting Alarm Clock Registers” section; added temp./voltage info. to tables (Table 10, 11, 6, 12, 13); addition of Default Values (Table 7)Note added to Clock Operation sectionChange in Product Maturity
Improve text in “Setting the Alarm Clock” sectionChange VPFD values in document
DC Characteristics VBAT changed; VOHB changed; PFI Hysteresis (PFI Rising) spec. added; and Crystal Electrical Characteristics table removed (Tables 11, 6)
Changed READ/WRITE Mode Sequences (Figure 12, 14); change in VPFD lower limit for 5V (M41ST85Y) part only (Table 11, 18)
Change trec Definition (Table 6); modify reflow time and temperature footnote (Table 8)Modify DC Characteristics table footnote, Default Values (Tables 11, 7)
Added embedded crystal (MX) package option; corrected initial power-up condition (Figure 2, 3, 5, 6, 7, 26, Table 1, 7, 18, 17)
Update diagrams (Figure 6, 7, 26); update values (Table 13, 5, 6, 7, 17)New Si changes (Table 13, 5, 6); corrected dimensions (Figure 26; Table 17)
Reformatted; correct dimensions; update Lead-free information (Figure 22, 15, 18; Table 8, 16, 18)
Update characteristics; add package shipping (Figure 5; Table 1, 11, 18)Update Maximum ratings (Table 8)
Updated template, Lead-free text, removed 5V references (Figure 3, 4, 5, 6, 7; Table 5, 8, 9, 11, 12, 13, 18, 19)
Revision Details
18-Jun-012.1
22-Jun-0126-Jul-0107-Aug-0120-Aug-0106-Sep-0103-Dec-0101-May-0203-Jul-0215-Nov-0224-Jan-0325-Feb-0320-May-0415-Jun-0413-Sep-0410-Jan-06
2.23.03.13.23.33.43.53.63.73.84.05.06.07.08.0
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Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not
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